1. Technical Field
The embodiments described herein generally relate to non-volatile memory, such as charge trapping memory.
2. Background
A Flash memory permits stored data to be retained even if power to the memory is removed. A Flash memory cell stores data either by storing electrical charge in an electrically isolated floating gate of a field effect transistor (FET) or by storing electrical charge in a dielectric layer underlying a control gate of a FET. The stored electrical charge controls the threshold of the FET, thereby controlling the memory state of the Flash memory cell.
Conventionally, a Flash memory cell is programmed using drain side hot carrier injection to inject charge carriers either onto a floating gate or into charge trapping sites in a dielectric layer underlying a control gate. High drain and gate voltages are used to speed up the programming process. Thus, the FET in the Flash memory cell conducts a high current during programming, which is undesirable in low voltage and low power applications. A split-gate cell is a type of Flash memory cell in which a select gate is placed adjacent a memory gate. A split gate cell provides lower current during hot-carrier-based programming operation. During the programming of the split-gate cell, the select gate is biased at a relatively low voltage, and only the memory gate is biased at the high voltage to provide the vertical electric field necessary for hot-carrier injection. Since the acceleration of the carriers takes place in the channel region mostly under the select gate, the relatively low voltage on the select gate above that region results in more efficient carrier acceleration in the horizontal direction compared to the conventional memory cell. That makes the hot-carrier injection more efficient with lower current and lower power consumption during the programming operation. A split-gate cell may be programmed using techniques other than hot-carrier injection, and depending on the technique, any advantage over the conventional memory cell during the programming operation may vary.
Fast read time is another advantage of the split-gate cell. Because the select gate is in series with the memory gate, the erased state of the memory gate can be near or in depletion mode (i.e., threshold voltage, Vt, less than zero volt). Even when the erased memory gate is in such depletion mode, the select gate in the off state prevents the channel from conducting substantial current. With the threshold voltage of the erase state at or below zero, the threshold voltage of the programmed state does not need to be very high while still providing a reasonable read margin between the erased and the programmed states. The resulting voltages applied to both the select gate and the memory gate in read operation are less than or equal to the supply voltage. Therefore, not having to pump the supply voltage to a higher level makes the read operation faster.
It is common to monolithically incorporate multiple types of field-effect devices on the same substrate as memory cells. Those non-memory devices perform, for example, decoding, charge-pumping, and other functions related to memory operations. The substrate may also include non-memory devices to provide functions that are not related to memory operations. Such non-memory devices incorporated on the same substrate as the memory cells may include transistors tailored for high-speed operations, while other transistors are tailored for handling high operating voltages. Integrating the processing of memory cells, such as a split-gate memory cell, with the processing of one or more types of non-memory transistors on the same substrate is challenging as each requires different fabrication parameters. Accordingly, there is a need for device and methods for integrating a memory cell and other devices on the same substrate to facilitate improved cost, performance, reliability, or manufacturability.
It is desirable to obviate or mitigate at least one of the problems, whether identified herein or elsewhere, or to provide an alternative to existing apparatuses or methods.
In an embodiment, a method of fabricating a semiconductor device. A dielectric is disposed on a substrate. A select gate is formed on the dielectric. A charge trapping layer is disposed on at least one region of the substrate adjacent to the select gate and on two sidewalls of the select gate. The charge trapping layer is removed from the two sidewalls of the select gate, while leaving the charge trapping layer on the at least one adjacent region. A memory gate is on the charge trapping layer on the at least one adjacent region.
In an embodiment, a semiconductor device includes a memory region, a first substrate region, and a second substrate region. There are first gates in the first substrate region. There are second gates in the second substrate region. There are select gates in the memory region. There are memory gates in the memory region, with each memory gate formed adjacent to a corresponding select gate. In the embodiment, sidewalls of the memory gates are older than (i.e., formed before) sidewalls of the second gates.
In an embodiment, a semiconductor device includes a select gate. There is a memory gate adjacent to the select gate. There is a charge trapping layer under the memory gate but not under the select gate or on a sidewall thereof. In this semiconductor device, a thickness of the charge trapping layer is substantially uniform adjacent the select gate and along the substrate. Additionally, the select gate has a rectangular cross section in a plane perpendicular to a junction between the memory gate and the select gate.
These and other advantages and features will become readily apparent in view of the following detailed description of embodiments of the invention. Note that the Summary and Abstract sections may set forth one or more, but not all exemplary embodiments of the present invention as contemplated by the inventor(s). It is to be appreciated that the Detailed Description section, and not the Summary and Abstract sections, is intended to be used to interpret the claims.
The accompanying drawings, which are incorporated herein and form part of the specification, illustrate the present invention and, together with the description, further serve to explain the principles of the present invention and to enable a person skilled in the relevant art(s) to make and use the present invention.
The features and advantages of the present invention will become more apparent from the detailed description set forth below when taken in conjunction with the drawings, in which like reference characters identify corresponding elements throughout. In the drawings, like reference numbers generally indicate identical, functionally similar, and/or structurally similar elements. The drawing in which an element first appears is indicated by the leftmost digit(s) in the corresponding reference number.
This specification discloses one or more embodiments that incorporate the features of this invention. The disclosed embodiment(s) merely exemplify the present invention. The scope of the present invention is not limited to the disclosed embodiment(s). The present invention is defined by the claims appended hereto.
The embodiment(s) described, and references in the specification to “one embodiment,” “an embodiment,” “an example embodiment,” etc., indicate that the embodiment(s) described may include a particular feature, structure, or characteristic, but every embodiment may not necessarily include the particular feature, structure, or characteristic. Moreover, such phrases are not necessarily referring to the same embodiment. Further, when a particular feature, structure, or characteristic is described in connection with an embodiment, it is understood that it is within the knowledge of one skilled in the art to effect such feature, structure, or characteristic in connection with other embodiments whether or not explicitly described.
Before describing the various embodiments in more detail, further explanation shall be given regarding certain terms that may be used throughout the descriptions.
The term “etch” or “etching” is used herein to generally describe a fabrication process of patterning a material, such that at least a portion of the material remains after the etch is completed. For example, it should be understood that the process of etching silicon involves the steps of patterning a masking layer (e.g., photoresist or a hard mask) above the silicon, and then removing the areas of silicon no longer protected by the masking layer. As such, the areas of silicon protected by the mask would remain behind after the etch process is complete. However, in another example, etching may also refer to a process that does not use a mask, but still leaves behind at least a portion of the material after the etch process is complete.
The above description serves to distinguish the term “etching” from “removing.” When etching a material, at least a portion of the material remains behind after the process is completed. However, “removing” is considered to be a broad term that may incorporate etching.
During the descriptions herein, various regions of the substrate upon which the field-effect devices are fabricated are mentioned. It should be understood that these regions may exist anywhere on the substrate and furthermore that the regions may not be mutually exclusive. That is, in some embodiments, portions of one or more regions may overlap. Although up to three different regions are described herein, it should be understood that any number of regions may exist on the substrate and may designate areas having certain types of devices or materials. In general, the regions are used to conveniently describe areas of the substrate that include similar devices and should not limit the scope or spirit of the described embodiments.
The terms “deposit” or “dispose” are used herein to describe the act of applying a layer of material to the substrate. Such terms are meant to describe any possible layer-forming technique including, but not limited to, thermal growth, sputtering, evaporation, chemical vapor deposition, epitaxial growth, electroplating, etc.
The term “substrate” as used throughout the descriptions is most commonly thought to be silicon. However, the substrate may also be any of a wide array of semiconductor materials such as germanium, gallium arsenide, indium phosphide, etc. In other embodiments, the substrate may be electrically non-conductive such as a glass or sapphire wafer.
The term “poly” as used throughout the descriptions is most commonly thought to be polycrystalline silicon. Poly comprises multiple small crystals, as opposed to being a single monocrystal. Poly can be doped, or may have metal or a metal silicide deposited over it.
“Poly” in this application is used as one example of a gate conductor. Other conductors may be used to form the gates, for example metals, alloys other doped semiconductors or conducting materials as would become apparent to a person having ordinary skill in the art. The use of “poly” in the description of the embodiments is not to be limiting.
Memory cell 100 includes two gates, a select gate 108 and a memory gate 110. Each gate may be a doped poly layer formed by well known, for example, deposit and etch techniques to define the gate structure. Select gate 108 is disposed over a dielectric layer 112. Memory gate 110 is disposed over a charge trapping dielectric 114 having one or more dielectric layers. In one example, charge trapping dielectric 114 includes a silicon nitride layer sandwiched between two silicon dioxide layers to create a three-layer stack collectively and commonly referred to as “ONO”. Other charge trapping dielectrics may include a silicon-rich nitride film, or any film that includes, but is not limited to, silicon, oxygen, and nitrogen in various stoichiometries. A vertical dielectric 116 is also disposed between select gate 108 and memory gate 110 for electrical isolation between the two gates. In some examples, vertical dielectric 116 and charge trapping dielectric 114 are the same dielectric, while other examples form one dielectric before the other (e.g., they can have different dielectric properties.) As such, vertical dielectric 116 need not include the same film structure as charge trapping dielectric 114. After the gates have been defined, regions 104 and 106 are created by implanting dopants using, for example, an ion implantation technique. Regions 104 and 106 form the source or drain of the split-gate transistor depending on what potentials are applied to each. In split gate transistors, for convenience, region 104 is commonly referred to as the drain, while region 106 is commonly referred to as the source, independent of the relative biases. It is to be understood that this description is meant to provide a general overview of a common split-gate architecture and that, in actual practice, many more detailed steps and layers are provided to form the final memory cell 100.
An example write, read, and erase operation will now be described as it relates to memory cell 100. In order to write a bit in memory cell 100, a positive voltage on the order of 5 volts, for example, is applied to region 106 while region 104 and substrate 102 are grounded. A low positive voltage on the order of 1.5 volts, for example, is applied to select gate 108 while a higher positive voltage on the order of 8 volts, for example, is applied to memory gate 110. As electrons are accelerated within a channel region between the source and drain, some of them will acquire sufficient energy to be injected upwards and get trapped inside charge trapping dielectric 114. This is known as hot electron injection. In one example of charge trapping dielectric 114, the electrons are trapped within a nitride layer of charge trapping dielectric 114. This nitride layer is also commonly referred to as the charge trapping layer. The trapped charge within charge trapping dielectric 114 store the “high” bit within memory cell 100, even after the various supply voltages are removed.
In order to “erase” the stored charge within memory cell 100 and return the state of memory cell 100 to a “low” bit, a positive voltage on the order of 5 volts, for example, is applied to region 106 while region 104 is floated or at a certain bias, and select gate 108 and substrate 102 are typically grounded. A high negative voltage on the order of −8 volts, for example, is applied to memory gate 110. The bias conditions between memory gate 110 and region 106 generate holes through band-to-band tunneling. The generated holes are sufficiently energized by the strong electric field under memory gate 110 and are injected upwards into charge trapping dielectric 114. The injected holes effectively erase the memory cell 100 to the “low” bit state.
In order to “read” the stored bit of memory cell 100, a low voltage is applied to each of the select gate, memory gate, and region 104 in the range between zero and 3 volts, for example, while region 105 and substrate 102 are typically grounded. The low voltage applied to the memory gate is chosen so that it lies substantially equidistant between the threshold voltage necessary to turn on the transistor when storing a “high” bit and the threshold voltage necessary to turn on the transistor when storing a “low” bit in order to clearly distinguish between the two states. For example, if the application of the low voltage during the “read” operation caused substantial current to flow between regions 104 and 106, then the memory cell holds a “low” bit and if the application of the low voltage during the “read” operation does not cause substantial current to flow between regions 104 and 106, then the memory cell holds a “high” bit.
An example source line (SL) runs along the X direction and is formed in a first metal layer (M1). Source line (SL) may be used to make electrical connection with doped region 106 of each memory cell 100 along a row extending in the X direction.
An example bit line (BL) runs along the Y direction and is formed in a second metal layer (M2). Bit line (BL) may be used to make electrical connection with doped region 104 of each memory cell 100 along a column extending in the Y direction.
It is to be understood that the circuit connections shown in
Periphery region 304 may include integrated circuit components such as resistors, capacitors, inductors, etc., as well as transistors. In the illustrated embodiment, periphery region 304 includes a plurality of high-voltage transistors 306 and low-voltage transistors 308. In one example, high-voltage transistors 306 exist in a separate region of substrate 102 than low-voltage transistors 308. High-voltage transistors 306 are capable of handling voltages up to 20 volts in magnitude, for example, while low-voltage transistors 308 operate at a faster speed, but cannot operate at the same high voltages as high-voltage transistors 306. In an embodiment, low voltage transistors 308 are designed to have a shorter gate length than high voltage transistors 306. High-voltage transistors 306 are commonly characterized as having a thicker gate dielectric 310 than the gate dielectric of low-voltage transistors 308.
One advantage to keeping the isolation layer between the memory gate 418 and the select gate 406 as thin as possible is because then the memory gate 418 and the select gate 406 can better control the channel region at that interface area. In another embodiment, where higher voltages are to be used for programming or erase operations, it may be desirable to have the sidewall oxide physically and electrically thicker than the nitride layer 412, such that the thick sidewall oxide has a higher breakdown voltage than the nitride layer 412.
Further manufacturing steps can be performed following those shown in
One advantage of the semiconductor devices of
In
In contrast, the memory gate 808 of
The memory gate 808 of
While embodiments have been described herein with reference to charge trapping memory, the invention is not limited to these examples. Instead, embodiments of the invention are applicable to other types of computer memory. The invention is useful for both charge-trapping and floating-gate devices. This invention may be implemented with multi-level cells or other multi-bit memory technologies.
Embodiments of the present invention have been described above with the aid of functional building blocks illustrating the implementation of specified functions and relationships thereof. The boundaries of these functional building blocks have been arbitrarily defined herein for the convenience of the description. Alternate boundaries can be defined so long as the specified functions and relationships thereof are appropriately performed.
The foregoing description of the specific embodiments will so fully reveal the general nature of the invention that others can, by applying knowledge within the skill of the art, readily modify and/or adapt for various applications such specific embodiments, without undue experimentation, without departing from the general concept of the present invention. Therefore, such adaptations and modifications are intended to be within the meaning and range of equivalents of the disclosed embodiments, based on the teaching and guidance presented herein. It is to be understood that the phraseology or terminology herein is for the purpose of description and not of limitation, such that the terminology or phraseology of the present specification is to be interpreted by the skilled artisan in light of the teachings and guidance.
The breadth and scope of the present invention should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents.