Patent Application
20070045717
This invention relates generally to semiconductor devices and methods, and more particularly to a charge-trapping memory device and a method of production.
Semiconductor memory devices include an array of memory cells that are arranged at a main surface of a semiconductor substrate. Rows of memory cells are electrically insulated from one another by shallow trench isolations that are produced in the substrate material by etching parallel trenches, which are subsequently filled with dielectric material.
Charge-trapping memory cells include a layer sequence of dielectric materials suitable for charge-trapping. Examples of charge-trapping memory cells are the SONOS memory cells comprising oxide-nitride-oxide layer sequences as storage medium.
U.S. Pat. Nos. 5,768,192 and 6,011,725, both of which are incorporated herein by reference, disclose charge-trapping memory cells of a special type of so-called NROM cells, which can be used to store bits of information both at the source and at the drain below the respective gate edges. NROM cells are usually programmed by channel hot electron injection. The programmed cell is read in reverse mode to achieve a sufficient two-bit separation. Erasure is performed by hot hole injection.
The charge-trapping layer sequence is usually applied on the main surface of the substrate after the formation of the shallow trench isolations. The effective channel width of NROM cells is highly affected by the final top width of the shallow trench isolations, the thickness of the charge-trapping layer sequence and the step height between the dielectric material of the shallow trench isolations and the adjacent semiconductor material of the substrate surface. There are numerous further single process steps by which the structure of the memory cell array and thus the performance of the memory are affected. Doping atoms that are implanted to adjust the threshold voltage of the memory cell transistors may diffuse from the semiconductor material into the dielectric material of the shallow trench isolations. This is regarded as a possible source of cell instability. A further miniaturization of the memory cells is expected to aggravate these problems.
A shallow trench isolation structuring integration scheme is proposed, in which the effective channel width is mainly determined by the dimension of the active areas after the etching of the isolation trenches. This scheme is characterized by the application of the charge-trapping layer sequence after the structuring of the trenches that are provided for the shallow trench isolations and without a previous deposition of other dielectric material to fill the trenches. The application of a charge-trapping layer sequence also within the trenches has the additional advantage to prevent or at least inhibit an outdiffusion of implanted dopants from the cell channels into the dielectric material of the shallow trench isolations.
The charge-trapping memory device includes a semiconductor substrate, especially of silicon, having a main surface, in which a plurality of trenches provided for shallow trench isolations are etched. The etched trenches are arranged to separate rows or columns of memory cells of a memory cell array. The memory cells are provided with a charge-trapping layer sequence of dielectric materials that comprise at least one material that is suitable for charge-trapping. The charge-trapping layer sequence is arranged on the main surface of the semiconductor substrate, including the sidewalls and bottoms of the trenches, and fills the trenches, thus forming the shallow trench isolations.
The charge-trapping layer sequence comprises a bottom layer, which is conformal with the main surface of the substrate in the area of the memory cell array. This clearly defines the top width of the cell transistor bodies, i.e., the lateral dimension of the active areas, which are outlined by the shape of the bottom layer at the upper edges of the transistor bodies. Furthermore, the charge-trapping layer sequence, especially a memory layer that is applied on the bottom layer and is provided for charge-trapping, provides a diffusion barrier against a diffusion of semiconductor material into the shallow trench isolations. The charge-trapping layer sequence can for instance comprise a bottom layer of oxide, especially silicon oxide, a memory layer of nitride, especially silicon nitride, and a top layer of oxide, especially silicon oxide.
In a manufacturing method of embodiments of these charge-trapping memory devices, a plurality of trenches running parallel at a distance from one another is etched into a main surface of a semiconductor substrate, especially a silicon substrate. The location of the trenches can be defined by the openings of a hard mask, preferably a layer of silicon nitride that is structured in a usual way by means of a photolithography step. After the formation of the trenches, a charge-trapping layer sequence is applied, which can especially be an oxide-nitride-oxide-layer sequence. These layers can be grown or deposited. The layer sequence is applied in such a manner that the trenches are completely filled so that the shallow trench isolations are formed by the dielectric materials of the charge-trapping layer sequence. The dielectric materials can be selected to be suitable to prevent an outdiffusion of the implanted doping atoms. For this purpose, it is especially appropriate to apply a memory layer of nitride.
A variant of this method comprises an additional application of a further layer of the same material as the top layer of the charge-trapping layer sequence after the application of the memory layer and before the application of the top layer of the charge-trapping layer sequence. The further layer is provided to fill the trenches to an upper level of the memory layer. It is removed except for residual parts so that an essentially planar upper surface of the memory layer is achieved. Then the top layer of the charge-trapping layer sequence is deposited or grown.
These and other features and advantages of the invention will become apparent from the following brief description of the drawings, detailed description and appended claims and drawings.
For a more complete understanding of the present invention, and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which:
The following list of reference symbols can be used in conjunction with the figures:
The making and using of the presently preferred embodiments are discussed in detail below. It should be appreciated, however, that the present invention provides many applicable inventive concepts that can be embodied in a wide variety of specific contexts. The specific embodiments discussed are merely illustrative of specific ways to make and use the invention, and do not limit the scope of the invention.
Between the trenches 2, there are areas of the upper surface 3 that form portions of the main surface of the substrate. These areas are the active areas of the memory cell array. The trenches have sidewalls and bottom surfaces 4.
The upper surface 3 and the sidewalls and bottom surfaces 4 of the trenches form the main surface of the substrate and are covered by a bottom layer 5 as shown in
The charge-trapping layer sequence can then be completed by the application of the top layer 7 as shown in
The trenches shown in
The preferred embodiment of the invention uses the charge-trapping layer sequence as a diffusing barrier on the semiconductor material to prevent the outdiffusion of dopant atoms. The forming of the charge-trapping layer sequence within the trenches enables an especially precise width uniformity of the active areas. The process steps can be performed to produce a structure having an essentially planar upper surface without additional planarizing steps being necessary; and non-uniform structures like steps between the shallow trench isolations and the cell transistor bodies are avoided.
Although the present invention and its advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims.
