CHECK MATRIX CREATION DEVICE, CHECK MATRIX CREATION METHOD, CHECK MATRIX CREATION PROGRAM, TRANSMITTER, RECEIVER, AND COMMUNICATION SYSTEM

Abstract

A check matrix creation device includes a circulant permutation matrix setting unit 12 for preparing a plurality of circulant permutation matrices each having an inner diameter of six or larger, and a quasi-cyclic matrix creation unit 13 for arranging the plurality of circulant permutation matrices prepared by the circulant permutation matrix setting unit 12 both in a row direction and in a column direction to create a quasi-cyclic matrix.

Description

FIELD OF THE INVENTION

The present invention relates to an encoding technology for use in digital communications. More particularly, it relates to a check matrix creation device for, a check matrix creation method of and a check matrix creation program for creating a parity check matrix for an LDPC (Low-Density Parity Check) code, a transmitter that encodes predetermined information bits by using a parity check matrix for LDPC code and transmits the encoded predetermined information bits, a receiver that decodes predetermined information bits by using a parity check matrix for an LDPC code, and a communication system consisting of the above-mentioned transmitter and the above-mentioned receiver.

BACKGROUND OF THE INVENTION

Hereafter, a conventional communication system which uses an LDPC code as an encoding method will be explained.

A case in which a quasi-cyclic (QC: Quasi-Cyclic) code is used as an example of an LDPC code will be explained (for example, refer to nonpatent reference 1).

First, encoding and decoding processing in the conventional communication system which uses an LDPC code as an encoding method will be explained briefly.

An LDPC encoder is mounted in a transmitter which is a communication device on a transmit side of the communication system, and creates a parity check matrix H by using a conventional method which will be mentioned later.

The LDPC encoder also creates a generator matrix G of K rows and N columns (K: an information length, N: a codeword length), for example.

When the parity check matrix for LDPC is a matrix of M rows and N columns, the generator matrix G satisfies GH^T=0 (T shows that the matrix is a transposed matrix).

When receiving a message (m₁, m₂, . . . , m_K) having an information length of K as information bits after creating the parity check matrix H and the generator matrix G, the LDPC encoder uses the message (m₁, m₂, . . . , m_K) and the generator matrix G to create a codeword C, as shown in the following equation (1).

C=(m₁, m₂, . . . , m_K)G=(c₁, c₂, . . . , c_N)   (1)

where the following equation: H(c₁, c₂, . . . , c_N)^T=0 is satisfied.

When the LDPC encoder creates the codeword C, the modulator of the transmitter performs digital modulation according to a modulation method, such as BPSK (Binary Phase Shift Keying), QPSK (Quadrature Phase Shift Keying), or multiple-value QAM (Quadrature Amplitude Modulation), for example, and transmits a modulated signal x=(x₁, x₂, . . . , x_N) of the codeword C to a receiver.

When the transmitter transmits the modulated signal x=(x₁, x₂, . . . , x_N), the demodulator of the receiver which is a communication device on a receive side of the communication system receives a corresponding modulated signal y=(y₁, y₂, . . . , y_N) which has been propagated thereto via a communication channel.

When receiving the modulated signal y=(y₁, y₂, . . . , y_N), the demodulator of the receiver performs digital demodulation corresponding to the modulation method, such as BPSK, QPSK, or multiple-value QAM, on the modulated signal.

An LDPC decoder of the receiver performs iterative decoding according to a “sum-product algorithm” on the demodulated result obtained by the demodulator, and, as the decoded result, outputs a message corresponding to the original message m₁, m₂, . . . , and m_K.

Hereafter, a parity check matrix for an LDPC code in the conventional communication system will be explained. For example, nonpatent reference 1 shown below discloses, as a parity check matrix for an LDPC code, the parity check matrix of a QC code as shown in FIG. 14.

The parity check matrix of a QC code shown in FIG. 14 is formed of circulant permutation matrices (p=5) of five rows and five columns which are arranged both in a longitudinal direction (J=3) and in a lateral direction (L=5).

In general, the parity-check matrix H_QC of a (J,L) QC code of M (=pJ) rows and N (=pL) columns can be defined as shown in the following equation (2).

In this equation, p is a non-zero integer.

Furthermore, L shows the number of circulant permutation matrices arranged in the lateral direction (column direction) in the parity-check matrix H_QC, and J shows the number of circulant permutation matrices arranged in the longitudinal direction (row direction) in the parity-check matrix H_QC.

$\begin{array}{cc}I\left(0\right)=\left[\begin{array}{cccc}I\left(p_{0,0}\right)& I\left(p_{0,1}\right)& \dots & I\left(p_{0,L-1}\right)\\ I\left(p_{1,0}\right)& I\left(p_{1,1}\right)& \dots & I\left(p_{1,L-1}\right)\\ ⋮& ⋮& \ddots & ⋮\\ I\left(p_{J-1,0}\right)& I\left(p_{J-1,1}\right)& \dots & I\left(p_{J-1,L-1}\right)\end{array}\right]\mathrm{Example}\text{:}P=5,I\left(0\right)=\left[\begin{array}{ccccc}1& 0& 0& 0& 0\\ 0& 1& 0& 0& 0\\ 0& 0& 1& 0& 0\\ 0& 0& 0& 1& 0\\ 0& 0& 0& 0& 1\end{array}\right]& \left(2\right)\end{array}$

where for 0<=j<=J−1 and 0<=l<=L−1, I(p_j,l) is a circulant permutation matrix in which any component whose row number is “r” (0<=r<=p−1) and whose column number is “(r+p_j,l) mod p” is “1”, and any other components are all “0”.

Furthermore, when an LDPC code is designed, because there is a high possibility that existence of many loops having a short length generally causes degradation in the performance, it is necessary to increase the inner diameter to reduce the number of loops having a short length (e.g., length-4 loops, length-6 loops, and so on).

FIG. 15 is an explanatory drawing showing an example of a parity-check matrix in the form of a Tanner graph.

In FIG. 15, in a parity-check matrix H of M rows and N columns having two elements {0, 1}, a node corresponding to each column is represented by a bit node b_n (1<=n<=N) (in the figure, ◯ shows each bit node), and a node corresponding to each row is represented by a check node c_m (1<=m<=M) (in the figure, □ shows each check node).

A bipartite graph in which a bit node and a check node corresponding to each of all the intersections of rows and columns at which “l” exists is connected by a branch is called a Tanner graph.

Hereafter, the meaning of a loop mentioned above will be explained. As shown in FIG. 15, a “loop” shows a closed path starting from a specific node (corresponding to ◯ or □ in the figure), and ending at this node.

Furthermore, the “inner diameter” means the length of the shortest loop, and “the length of a loop” is represented by the number of branches which construct the closed path. Loops are simply expressed as length-4 loops, length-6 loops, length-8 loops, and so on according to their lengths.

Furthermore, in the following nonpatent reference 1, the range of inner diameters g in the parity-check matrix H_QC of a (J,L) QC-LDPC code is defined to be equal to “4<=g<=12 (g is an even number)”. However, it is easy to avoid g=4 and, in many cases, the inner diameter range is g>=6.

Related Art Document

Nonpatent Reference

Nonpatent reference 1: M. Fossorier, “Quai-Cyclic Low-Density Parity-Check Codes From Circulant Permutation Matrices”, IEEE Trans. Inform. Theory, Vol. 50, No. 8 (2004) pp. 1788-1793.

SUMMARY OF THE INVENTION

Because the conventional communication systems are constructed as above, a parity-check matrix H_QC whose range of inner diameters g is “4<=g<=12 (g is an even number) ” is used. However, a design method of designing an LDPC code under the conditions that g>=6, g>=8, g>=10, g>=12, or . . . is satisfied has not been shown concretely. A problem is therefore that it is necessary to design an LDPC code by mainly using a computer search and therefore it takes much time to design an LDPC code.

Another problem is that because such a method lacks in extendibility and also lacks in the regularity among circulant permutation matrices, the degree of complexity increases at the time of implementation.

It has not been proved that the results obtained through a computer search are optimal.

The present invention is made in order to solve the above-mentioned problems, and it is therefore an object of the present invention to provide a check matrix creation device, a check matrix creation method, and a check matrix creation program capable of creating a parity-check matrix for an irregular LDPC code which has a better performance than that created using a method of configuring a check matrix through a computer search, and which has a regular configuration and can support a wide range of coding rates.

It is another object of the present invention to provide a transmitter and a communication system which have a good performance and which can encode predetermined information bits by using a parity-check matrix having a regular configuration, and transmit them.

It is a further object of the present invention to provide a receiver and a communication system which have a good performance and which can decode predetermined information bits by using a parity-check matrix having a regular configuration.

In accordance with the present invention, there is provided a check matrix creation device including: a circulant permutation matrix setting means for preparing a plurality of circulant permutation matrices; and a quasi-cyclic matrix creation means for arranging the plurality of circulant permutation matrices prepared by the circulant permutation matrix setting means both in a row direction and in a column direction to create a quasi-cyclic matrix.

Because the check matrix creation device in accordance with the present invention is constructed in such a way as to include the circulant permutation matrix setting means for preparing a plurality of circulant permutation matrices, and the quasi-cyclic matrix creation means for arranging the plurality of circulant permutation matrices prepared by the circulant permutation matrix setting means both in the row direction and in the column direction to create a quasi-cyclic matrix, there is provided an advantage of being able to create a parity-check matrix for an irregular LDPC code which has a better performance than that created using a method of forming a check matrix through a computer search, and which has a regular configuration and can support a wide range of coding rates.

BRIEF DESCRIPTION OF THE FIGURES

FIG. 1 is a block diagram showing a communication system in accordance with Embodiment 1 of the present invention;

FIG. 2 is a flow chart showing processes respectively carried out by check matrix creation devices 11 and 21;

FIG. 3 is an explanatory drawing showing a graph G of the check matrix of an LDPC code in QC;

FIG. 4 is an explanatory drawing showing the graph G which is shown using V_l={v_l,0, v_l,1, . . . , v_l,p−1} for 0<=l<=L−1, and C_j={c_j,0, c_j,1, . . . , c_j,p−1} for 0<=j<=J−1;

FIG. 5 is an explanatory drawing showing a graph G₀^g which is a bipartite graph;

FIG. 6 is an explanatory drawing showing a subgraph of nodes connected to V₀;

FIG. 7 is an explanatory drawing showing a subgraph in which V₀ is divided into V_0—0, V_0—1, and V_0—2;

FIG. 8 is an explanatory drawing showing a state in which two graphs G₀^g and G₁^g are connected to each other via p branches;

FIG. 9 is an explanatory drawing showing a state in which two graphs G₀^g and G₁^g are connected to each other via 2*p branches;

FIG. 10 is an explanatory drawing showing conversion of a graph G₀¹⁰ into a graph G₀¹⁰;

FIG. 11 is an explanatory drawing showing a graph using a check matrix H_0,1;

FIG. 12 is a block diagram showing a communication system in accordance with Embodiment 2 of the present invention;

FIG. 13 is a block diagram showing a communication system in accordance with Embodiment 3 of the present invention;

FIG. 14 is an explanatory drawing showing a parity-check matrix for LDPC codes disclosed by nonpatent reference 1; and

FIG. 15 is an explanatory drawing showing an example of the parity-check matrix in the form of a Tanner graph.

EMBODIMENTS OF THE INVENTION

Hereafter, in order to explain this invention in greater detail, the preferred embodiments of the present invention will be described with reference to the accompanying drawings. Embodiment 1.

FIG. 1 is a block diagram showing a communication system in accordance with Embodiment 1 of the present invention. In the figure, a transmitter 1 is a communication device on a transmit side of the communication system, and carries out a process of creating a codeword (v₁, v₂, . . . , v_N) from both a message (u₁, u₂, . . . , u_K) having an information length of K which is predetermined information bits, and a parity-check matrix H_M for an LDPC code, modulating the codeword (v₁, v₂, . . . , v_N), and transmitting a modulated signal (x₁, x₂, . . . , x_N) of the codeword via a communication channel 2.

The receiver 3 is a communication device on a receive side of the communication system, and, when receiving a modulated signal (y₁, y₂, . . . , y_N) of a codeword transmitted from the transmitter 1, carries out a process of demodulating the modulated signal (y₁, y₂, . . . , y_N), and decodes this demodulated signal to generate a message (u₁, u₂, . . . , u_K) having an information length of K.

A check matrix creation device 11 of the transmitter 1 carries out a process of preparing a plurality of circulant permutation matrices each having an inner diameter g of six or larger, and arranging the plurality of circulant permutation matrices both in a row direction and in a column direction to create a quasi-cyclic matrix which is a parity-check matrix H_M for an LDPC code.

A circulant permutation matrix setting unit 12 of the check matrix creation device 11 carries out the process of preparing the plurality of circulant permutation matrices each having an inner diameter g of six or larger. The circulant permutation matrix setting unit 12 constructs a circulant permutation matrix setting means.

A quasi-cyclic matrix creation unit 13 of the check matrix creation device 11 carries out the process of arranging the plurality of circulant permutation matrices prepared by the circulant permutation matrix setting unit 12 both in the row direction and in the column direction to create a quasi-cyclic matrix which is a parity-check matrix H_M for an LDPC code. The quasi-cyclic matrix creation unit 13 constructs a quasi-cyclic matrix creation means.

An LDPC encoder 14 of the transmitter 1 carries out a process of creating a codeword (v₁, v₂, . . . , v_N) from both a message (u₁, u₂, . . . , u_K) having an information length of K, and the parity-check matrix H_M for an LDPC code created by the check matrix creation device 11. The LDPC encoder 14 constructs a codeword creation means.

A modulator 15 of the transmitter 1 carries out a process of modulating the codeword (v₁, v₂, . . . , v_N) created by the LDPC encoder 14, and transmitting a modulated signal (x₁, x₂, . . . , x_N) of the codeword to the receiver 3 via the communication channel 2. The modulator 15 constructs a transmitting means.

The check matrix creation device 11 of the transmitter 1 carries out the process of preparing a plurality of circulant permutation matrices each having an inner diameter g of six or larger, and arranging the plurality of circulant permutation matrices both in the row direction and in the column direction to create a quasi-cyclic matrix which is a parity-check matrix H_M for an LDPC code.

The circulant permutation matrix setting unit 12 of the check matrix creation device 11 carries out the process of preparing a plurality of circulant permutation matrices each having an inner diameter g of six or larger. The circulant permutation matrix setting unit 12 constructs the circulant permutation matrix setting means.

The quasi-cyclic matrix creation unit 13 of the check matrix creation device 11 carries out the process of arranging the plurality of circulant permutation matrices prepared by the circulant permutation matrix setting unit 12 both in the row direction and in the column direction to create a quasi-cyclic matrix which is a parity-check matrix H_M for an LDPC code. The quasi-cyclic matrix creation unit 13 constructs the quasi-cyclic matrix creation means.

In this Embodiment 1, the check matrix creation device 11 which is comprised of the circulant permutation matrix setting unit 12 and the quasi-cyclic matrix creation unit 13 is shown. As an alternative, the check matrix creation device 11 can be constructed of a computer, and, in this case, a check matrix creation program in which the processes of the circulant permutation matrix setting unit 12 and the quasi-cyclic matrix creation unit 13 are described can be stored in a memory of the computer and the CPU of the computer can be made to execute the check matrix creation program.

When the receiver 3 receives a modulated signal (y₁, y₂, . . . , y_N) of a codeword transmitted from the transmitter 1, a demodulator 24 of the receiver 3 carries out a process of demodulating the modulated signal (y₁, y₂, . . . , y_N). The demodulator 24 constructs a receiving means.

An LDPC decoder 25 of the receiver 3 carries out a process of performing iterative decoding according to a known decoding algorithm on the demodulated result obtained by the demodulator 24 by using a parity-check matrix H_M created by a check matrix creation device 21, and outputting a message corresponding to the original message (u₁, u₂, . . . , u_K) as the decoded result. The LDPC decoder 25 constructs a decoding means.

In FIG. 1, the example in which the check matrix creation device 11 is disposed separately from the LDPC encoder 14 is shown, although the LDPC encoder 14 can include the check matrix creation device 11.

As an alternative, the check matrix creation device 11 can be disposed outside the transmitter 1. In this case, the parity-check matrix H_M for an LDPC code created by the check matrix creation device 11 can be stored in an internal memory of the transmitter 1, or the transmitter can receive the parity-check matrix H_M from the check matrix creation device 11.

Furthermore, in FIG. 1, the example in which the check matrix creation device 21 is disposed separately from the LDPC decoder 25 is shown, although the LDPC decoder 25 can include the check matrix creation device 21.

As an alternative, the check matrix creation device 21 can be disposed outside the receiver 3. In this case, the parity-check matrix H_M for an LDPC code created by the check matrix creation device 21 can be stored in an internal memory of the receiver 3, and the receiver can receive the parity-check matrix H_M from the check matrix creation device 21.

Next, the operation of the communication system will be explained.

First, encoding and decoding processing carried out by the communication system of FIG. 1 which uses an LDPC code as an encoding method will be explained briefly.

The check matrix creation device 11 of the transmitter 1 prepares a plurality of circulant permutation matrices each having an inner diameter g of six or larger, and arranges the plurality of circulant permutation matrices both in the row direction and in the column direction to create a quasi-cyclic matrix which is a parity-check matrix H_M for an LDPC code.

More specifically, the circulant permutation matrix setting unit 12 of the check matrix creation device 11 prepares a plurality of circulant permutation matrices each having an inner diameter g of six or larger in advance, although will be mentioned below in detail.

After the circulant permutation matrix setting unit 12 prepares the plurality of circulant permutation matrices, the quasi-cyclic matrix creation unit 13 of the check matrix creation device 11 arranges the plurality of circulant permutation matrices both in the row direction and in the column direction to create a quasi-cyclic matrix which is a parity-check matrix H_M for an LDPC code, although will be mentioned below in detail.

After the check matrix creation device 11 creates the parity-check matrix H_M of M rows and N columns as the parity-check matrix H_M for an LDPC code, when receiving a message (u₁, u₂, . . . , u_K) having an information length of K, the LDPC encoder 14 of the transmitter 1 creates a codeword v=(v₁, v₂, . . . , v_N) having a length of N from the message (u₁, u₂, . . . , u_K) and the parity-check matrix H_M, as shown in the following equation (3).

v={(v₁, v₂, . . . , v_N) ∈GF(2)|(v₁, v₂, . . . , v_N)H_M^T=0}  (3)

In this Embodiment 1, the LDPC encoder carries out a process of encoding the information bits without using a generator matrix G (K: an information length, N: a codeword length), unlike in the case of the conventional example.

More specifically, when the parity-check matrix H_M has a part having a lower triangular matrix configuration, the LDPC encoder can implement the encoding easily without using a generator matrix G.

For example, when a systematic codeword v is expressed as will be shown below, and a message u=(u₁, u₂, . . . , u_K) having an information length of K is provided, the LDPC encoder creates a parity component p_m=(p₁, p₂, . . . , p_M) in such a way that “H*v^T=0” is satisfied. More specifically, the LDPC encoder creates the parity component p_m=(p₁, p₂, . . . , p_M) as shown in the following equation (4).

v=(v₁, v₂, . . . , v_K, v_K+1, v_K+2, . . . , v_N)=(u₁, u₂, . . . , u_K,p₁,p₂, . . . , p_M)

where N=K+M.

$\begin{array}{cc}{p}_m=\sum _{n=1}^{K+m-1}v_nh_{m,n},1\le m\le M,1\le n\le N& \left(4\right)\end{array}$

where h_m,n shows a component having a row number m and a column number n in the parity-check matrix H_M.

After the LDPC encoder 14 creates the codeword (v₁, v₂, . . . , v_N), the modulator 15 of the transmitter 1 performs digital modulation according to a modulation method, such as BPSK, QPSK, or multiple-value QAM, on the codeword (v₁, v₂, . . . , v_N), and transmits a modulated signal x=(x₁, x₂, . . . , x_N) of the codeword (v₁, v₂, . . . , v_N) to the receiver 3 via the communication channel 2.

The check matrix creation device 21 of the receiver 3 prepares a plurality of circulant permutation matrices each having an inner diameter g of six or larger, and arranges the plurality of circulant permutation matrices both in the row direction and in the column direction to create a quasi-cyclic matrix which is a parity-check matrix H_M for an LDPC code in the same way that the check matrix creation device 11 of the transmitter 1 does.

More specifically, the circulant permutation matrix setting unit 22 of the check matrix creation device 21 prepares a plurality of circulant permutation matrices each having an inner diameter g of six or larger in advance.

After the circulant permutation matrix setting unit 22 prepares the plurality of circulant permutation matrices, the quasi-cyclic matrix creation unit 23 of the check matrix creation device 21 arranges the plurality of circulant permutation matrices both in the row direction and in the column direction to create a parity-check matrix H_M for an LDPC code.

When the transmitter 1 transmits the modulated signal x=(x₁, x₂, . . . , x_N), the demodulator 24 of the receiver 3 receives the modulated signal y=(y₁, y₂, . . . , y_N) which has been propagated thereto via the communication channel 2.

When receiving the modulated signal y=(y₁, y₂, . . . , y_N) the demodulator 24 of the receiver 3 carries out digital demodulation corresponding to the modulation method, such as BPSK, QPSK, or multiple-value QAM, on the modulated signal y.

The LDPC decoder 25 of the receiver 3 performs iterative decoding according to a known decoding algorithm on the demodulated result obtained by the demodulator 24 by using the parity-check matrix H_M created by the check matrix creation device 21, and outputs a message corresponding to the original message (u₁, u₂, . . . , u_K) as the decoded result.

Hereafter, a method of creating a parity-check matrix H_M which each of the check matrix creation devices 11 and 21 uses will be explained concretely.

FIG. 2 is a flow chart showing a process carried out by the check matrix creation devices 11 and 21.

[Condition for Configuring a New Check Matrix from a Combination of Check Matrices Each Having an Inner Diameter of g]

Hereafter, a (J,L)-regular bipartite graph representing the check matrix of an LDPC code in (J,L)-regular QC is expressed as “G”.

The graph G consists of a set of n=L*p bit nodes having a degree of λ: λ={V₀, V₁, . . . , V_L−1} for V₁={v_l,0, v_l,1, . . . , v_l,p−1} and 0<=l<=L−1, and a set of m=J*p check nodes having a degree of ρ: Γ={C₀, C₁, . . . , C_J−1} for C_j={c_j,0, c_j,1, . . . , c_j,p−1} and 0<=j<=J−1.

A set of N_e=n*J=m*L branches: Ξ={e₀, e₁, . . . , e_N−1} is included in the graph G.

Furthermore, when the nodes connected to a branch e_i for 0<=i<=N_e are v_l,1 and c_j,0, for example, this connection is expressed as (v_l,1, c_j,0).

Each branch e_i also has a bit node as a left-hand side vertex, and a check node as a right-hand side vertex.

Bit Node as Left-Hand Side Vertex v_l,└i/p┘, l=└i/(J·p)┘.

Check Node as Right-Hand Side Vertex c_{J,((ιmod p)−pj,J)mod p}, l=└└i/p┘mod J┘

For example, in the case of the following check matrix,

$\left[\begin{array}{ccc}I\left(0\right)& I\left(0\right)& I\left(0\right)\\ I\left(0\right)& I\left(1\right)& I\left(2\right)\end{array}\right]=\left[\frac{\begin{array}{ccccc}1& & & & \\ & 1& & & \\ & & 1& & \\ & & & 1& \\ & & & & 1\end{array}|}{\begin{array}{ccccc}1& & & & \\ & 1& & & \\ & & 1& & \\ & & & 1& \\ & & & & 1\end{array}|}\frac{\begin{array}{ccccc}1& & & & \\ & 1& & & \\ & & 1& & \\ & & & 1& \\ & & & & 1\end{array}|}{\begin{array}{ccccc}& 1& & & \\ & & 1& & \\ & & & 1& \\ & & & & 1\\ 1& & & & \end{array}|}\frac{\begin{array}{ccccc}1& & & & \\ & 1& & & \\ & & 1& & \\ & & & 1& \\ & & & & 1\end{array}}{\begin{array}{ccccc}& & 1& & \\ & & & 1& \\ & & & & 1\\ 1& & & & \\ & 1& & & \end{array}}\right]$

the graph G of the check matrix of an LDPC code in QC is represented as shown in FIG. 3. However, in FIG. 3, only a part of the branches is shown. From this graph G, an example of the relationship between the branches and the nodes each of which is a vertex can be verified.

FIG. 4 shows the graph G by using V₁={v_l,0, v_l,1, . . . , v_l,p−1} for 0<=l<=L−1, and C_j={c_j,0, c_j,1, . . . , c_j,p−1} for 0<=j<=J−1.

As shown in FIG. 4, for example, a set V₁ of bit nodes is connected to a set C₀ of check nodes via I(0), and is also connected to a set C₁ of check nodes via I(1).

Hereafter, when the graph G has an inner diameter of g, it is expressed as G_x^g, and it is assumed that G_xg≠G_x′^g when x≠x′. Furthermore, it is assumed that a graph G₀^g is a bipartite graph as shown in FIG. 5.

At this time, focusing attention on a set V₀ of bit nodes of this graph G₀^g, all loops formed via V₀, and C₁, C₁ and C₂ have inner diameters of g or larger.

For example, as shown in FIG. 6, in the subgraph of nodes connected to V₀, all of a loop extending via (V₀, C₀) and (V₀, C₁), a loop extending via (V₀, C₀) and (V₀, C₂), and a loop extending via (V₀, C₁) and (V₀, C₂) have inner diameters of g or larger.

V₀ is divided into V_0—0, V_0—1, and V_0—2 in this subgraph, as shown in FIG. 7, and branches are newly formed under conditions that no loop is produced in the subgraph comprised of V_0—0, V_0—1 and V_0—2, and C₀, C₁ and C₂,

The whole of this graph obtained after the division is done is expressed as G₀^g.

For example, it is assumed that V₁ is connected to C₀ via I(0), is connected to C₁ via I(1), and is connected to C₂ via I(2).

Furthermore, it is assumed that after the division is done, V_0—0 is connected to C₀ via I(0) and is also connected to C₁ via I(1), V_0—1 is connected to C₁ via I(1) and is also connected to C₂ via I(2), and V_0—2 is connected to C₁ via I(2).

As a result of this division, because each loop extending via (V₀, C₀) and (V₀, C₁) in the graph G₀^g, and each loop extending via (V_0—0, C₀) and (V_0—0, C₁) in the graph G₀^g pass the same I(0) and I(1) respectively, their loop lengths do not change and are equal to or longer than g.

Similarly, each loop extending via (V_0—1, C₁), and (V_0—1, C₂) has also a loop length of g or longer.

In addition, each loop extending via (V_0—0, C₀) and (V_0—1, C₂) has a loop length of g+2 or longer.

Furthermore, because the branches are added in such a way that no loop is produced newly, no loop having a loop length of shorter than g exists.

• (I) As mentioned above, when the graph G₀^g representing the check matrix of an LDPC code in QC satisfies the following conditions (1) and (2), the graph G₀^g which is produced after the division is done also has an inner diameter of g or larger.
• (1) V_x or C_y is divided without changing the value of I(p_j,1) extending via V_x and C_y.
• (2) No loop exists in the subgraph which is produced after the division and is comprised of V_x and C_y.
• (II) Next, consider a connection between different graphs.

When different graphs are connected to each other via p branches (for example, as illustrated in FIG. 8, different graphs are connected to each other via a single thick branch, although this single thick branch is a set of p branches), each of loops including the branches has a loop length of ten or larger.

For example, as shown in FIG. 8, when two graphs G₀^g and G₁^g are connected to each other via p branches (which is one set of p branches), it is necessary for each of the loops including the branches to go via the 2*p branches (the two sets of p branches) in order to connect the two graphs G₀^g and G₁^g because the shortest loop of each graph is a 4-length loop.

Accordingly, there is a possibility that each of the loops including the branches has a loop length=4+4+2=10, and their shortest loop length is ten or longer.

Furthermore, as shown in FIG. 9, in a case in which two or more graphs are subjected to a division based on the conditions shown in (I), two graphs on which the division is performed are connected by using 2*p branches (the two sets of p branches) or more in such a way that subgraphs each of which consist of nodes on which a division which does not produce any loop has been performed are connected to each other, and each of the subgraphs to which those branches are added does not include any loop, the shortest loop including those branches has a loop length of eight or longer.

When the above-mentioned conditions are satisfied, a connection between two graphs using 2*p branches (two sets of p branches) requires 2*p branches (two sets of p branches) for each of outward and return paths.

Because 2*p branches (two sets of p branches) in each of the graphs are adequate to form a loop, there is a possibility that each loop including the branches has a loop length=2+2+2+2=8, and the shortest loop including the branches has a loop length of eight or longer.

[Example of Configuration of an LDPC Code]

Hereafter, a code which is configured according to the above-mentioned configuration conditions will be shown as an example.

For example, check matrices corresponding to graphs G₀¹⁰ and G₁¹⁰ are expressed as H₀¹⁰ and H₁¹⁰ respectively, and it is assumed that the check matrices H₀¹⁰ and H₁¹⁰ have the following configurations respectively. In the matrices, each numeral shows p_j,l, and each null shows a p×p zero matrix.

$H_0^{10}=\left[\begin{array}{cccc}0& 11& 0& 0\\ 1& 7& 8& 0\\ 3& 20& 31& 0\end{array}\right]H_1^{10}=\left[\begin{array}{cccc}0& 14& 4& 0\\ 10& 1& 8& 0\\ 17& 41& 7& 0\end{array}\right],p=49$

Furthermore, each of these two check matrices H₀¹⁰ and H₁¹⁰ is divided in such a way that check matrices H₀¹⁰ and H₁¹⁰ corresponding to graphs G₀¹⁰ and G₁¹⁰ are configured.

${\underset{\_}{H}}_0^{10}=\left[\begin{array}{cccccc}0& 11& 0& 0& & \\ 1& 7& 8& 0& 0& \\ 3& 20& 31& & 0& 0\end{array}\right],{\underset{\_}{H}}_1^{10}=\left[\begin{array}{cccccc}0& 14& 4& 0& & \\ 10& 1& 8& 0& 0& \\ 17& 41& 7& & 0& 0\end{array}\right],p=49$

The above-mentioned conversion of the graph G₀¹⁰ into the graph G₀¹⁰ is represented by a graph, as shown in FIG. 10.

The conversion of the graph G₁¹⁰ into the graph G₁¹⁰ is similarly represented by a graph.

Next, the following check matrix H_0,1 is created by using the check matrices H₀¹⁰ and H₁¹⁰.

${\underset{\_}{H}}_{0,1}\left[\begin{array}{cccccccccccc}0& 11& 0& & & & 0& & & & & \\ & & & 0& 14& 4& 0& 0& & & & \\ 1& 7& 8& & & & & 0& 0& & & \\ & & & 10& 1& 8& & & 0& 0& & \\ 3& 20& 31& & & & & & & 0& 0& \\ & & & 17& 41& 7& & & & & 0& 0\end{array}\right]$

This graph is represented as shown in FIG. 11.

In FIG. 11, each node denoted by reference characters not including “′” is a node for the graph G₀¹⁰, and each node denoted by reference characters including “′” is a node for the graph G₁¹⁰.

In the graph of FIG. 11, only connections with each divided node are represented by branches to avoid the complexity of the graph.

This H_0,1 is an example represented, as the check matrix, by connecting different graphs of g=10 to form a new graph.

In this case, H_0,1¹⁰ has an inner diameter of eight or larger according to the condition (2) of (II). Because designing a check matrix having an inner diameter of eight or larger is a difficult issue, it is desired that an advantage of adequately guaranteeing the performance characteristics of the check matrix creation device is provided.

[Combination with a Submatrix Having a Large Column Weight and a Small Inner Diameter]

In general, an inner diameter exerts a large influence upon a portion having a small column weight.

In the above-mentioned example, a combination with a submatrix having g=10 is shown. However, it has turned out that, if the submatrix has a large column weight, the performance characteristics of the check matrix creation device do not degrade greatly even though the subgraph corresponding to the submatrix having the large column weight has an inner diameter of g=6 or g=8.

Therefore, only the inner diameter of a submatrix corresponding to a portion having a large column weight can be reduced relatively as follows.

[Process of Reducing Columns Having a Column Weight of “1”]

In the above-mentioned check matrix H′_0,1, because a portion of p_5,13=0 has a column weight of “1”, the weights of p columns are all “1”.

In general, because an error floor can occur when there are a large number of columns having a weight of “1”, it is desirable that the number of columns having a weight of “1” is small.

On the other hand, because a stair-like arrangement of “0s” forms a lower triangular matrix and has a configuration required for the code creation, it is preferable to maintain the configuration of the lower triangular matrix.

As a method of reducing the number of columns having a weight of “1” in the state in which this configuration is maintained, a circulant permutation matrix having a column weight of “1” is converted as follows. As a result, the number of columns having a column weight of “1” can be reduced from p to 1.

$I\left(0\right)=\left[\begin{array}{ccccc}1& & & & \\ & 1& & & \\ & & \ddots & & \\ & & & 1& \\ & & & & 1\end{array}\right]I\left(0^{″}\right)=\left[\begin{array}{ccccc}1& & & & \\ 1& 1& & & \\ & \ddots & \ddots & & \\ & & 1& 1& \\ & & & 1& 1\end{array}\right]$

The whole of the check matrix is converted as follows.

In this case, the check matrix is simply represented only by using p_j,l of I(p_j,l) in the following expression. Furthermore, the above-mentioned conversion is expressed as p_j,l=0″.

${\underset{\_}{H^{″}}}_{0,1}=\left[\begin{array}{cccccccccccccc}0& 0& 0& 11& 0& & & & 0& & & & & \\ 1& 2& & & & 0& 14& 4& 0& 0& & & & \\ 3& 6& 1& 7& 8& & & & & 0& 0& & & \\ 4& 8& & & & 10& 1& 8& & & 0& 0& & \\ 9& 18& 3& 20& 31& & & & & & & 0& 0& \\ 10& 20& & & & 17& 41& 7& & & & & 0& 0^{″}\end{array}\right],p=49$

As can be seen from the above description, because the check matrix creation device in accordance with this Embodiment 1 is constructed in such a way as to include the circulant permutation matrix setting unit 12 for preparing a plurality of circulant permutation matrices each having an inner diameter of six or larger, and the quasi-cyclic matrix creation unit 13 for arranging the plurality of circulant permutation matrices prepared by the circulant permutation matrix setting unit 12 both in the row direction and in the column direction to create a quasi-cyclic matrix, there is provided an advantage of being able to create a parity-check matrix for an irregular LDPC code which has a better performance than that created using a method of forming a check matrix through a computer search, and which has a regular configuration and can support a wide range of coding rates.

Embodiment 2

FIG. 12 is a block diagram showing a communication system in accordance with Embodiment 2 of the present invention.

In above-mentioned Embodiment 1, the example in which the communication device on the transmit side is the transmitter 1 and the communication device on the receive side is the receiver 3 is shown (refer to FIG. 1). In contrast, in this Embodiment 2, an example in which a mobile terminal 100 and a base station 200 transmit and receive data to and from each other is shown.

In the figure, a physical layer LDPC encoder 101 of the mobile terminal 100 is applied to a fading communication channel or the like in a physical layer, and constructs the LDPC encoder 14 of FIG. 1. Furthermore, the physical layer LDPC encoder 101 can include the check matrix creation device 11 of FIG. 1, or the check matrix creation device 11 of FIG. 1 can be disposed separately from the physical layer LDPC encoder 101.

A modulator 102 of the mobile terminal 100 carries out a process of modulating a codeword created by the physical layer LDPC encoder 101, and sending out a modulated signal of the codeword onto a radio channel by using an antenna 105.

A demodulator 103 of the mobile terminal 100 carries out a process of, when the antenna 105 receives a modulated signal of a codeword transmitted from the base station 200 (a received signal including an error occurring in the radio channel), demodulating the modulated signal.

A physical layer LDPC decoder 104 of the mobile terminal 100 is applied to the fading communication channel or the like in the physical layer, and constructs the LDPC decoder 25 of FIG. 1. Furthermore, the physical layer LDPC decoder 104 can include the check matrix creation device 21 of FIG. 1, or the check matrix creation device 21 of FIG. 1 can be disposed separately from the physical layer LDPC decoder 104.

A physical layer LDPC encoder 201 of the base station 200 is applied to a fading communication channel or the like in the physical layer, and constructs the LDPC encoder 14 of FIG. 1. Furthermore, the physical layer LDPC encoder 201 can include the check matrix creation device 11 of FIG. 1, or the check matrix creation device 11 of FIG. 1 can be disposed separately from the physical layer LDPC encoder 201.

A modulator 202 of the base station 200 carries out a process of modulating a codeword created by the physical layer LDPC encoder 201, and sending out a modulated signal of the codeword onto a radio channel by using an antenna 205.

A demodulator 203 of the base station 200 carries out a process of, when the antenna 205 receives a modulated signal of a codeword transmitted from the mobile terminal 100 (a received signal including an error occurring in the radio channel) demodulating the modulated signal.

A physical layer LDPC decoder 204 of the base station 200 is applied to the fading communication channel or the like in the physical layer, and constructs the LDPC decoder 25 of FIG. 1. Furthermore, the physical layer LDPC decoder 204 can include the check matrix creation device 21 of FIG. 1, or the check matrix creation device 21 of FIG. 1 can be disposed separately from the physical layer LDPC decoder 204.

Next, the operation of the communication system will be explained.

When the mobile terminal 100 transmits data to the base station 200, the physical layer LDPC encoder 101 for the fading communication channel encodes the data on a per-packet-data basis in the physical layer. The encoding process is the same as that carried out by the LDPC encoder 14 of FIG. 1.

When the physical layer LDPC encoder 101 creates coded data, the modulator 102 of the mobile terminal 100 modulates the coded data, and sends out a modulated signal of the coded data onto the radio channel by using the antenna 105.

When the antenna 205 receives the modulated signal of the codeword transmitted from the mobile terminal 100 (the received signal including an error occurring in the radio channel), the demodulator 203 of the base station 200 demodulates the modulated signal.

The physical layer LDPC decoder 204 of the base station 200 corrects the error of the data by performing the same decoding process as that carried out by the LDPC decoder 25 of FIG. 1 on the demodulated result obtained by the demodulator 203 to generate the data.

In the physical layer, the physical layer LDPC decoder 204 informs information showing whether the physical layer LDPC decoder has succeeded in the error correction on a per-packet basis to an upper hierarchical layer, and transmits the error-corrected data to the communication partner via the network.

In a case in which the base station 200 transmits data to the mobile terminal 100, when the physical layer LDPC encoder 201 for the fading communication channel receives the data, via the network, from the communication partner in the physical layer, the physical layer LDPC encoder 201 encodes the data on a per-packet-data basis. The encoding process is the same as that carried out by the LDPC encoder 14 of FIG. 1.

When the physical layer LDPC encoder 201 creates coded data, the modulator 202 of the base station 200 modulates the coded data, and sends out a modulated signal of the coded data onto the radio channel by using the antenna 205.

When the antenna 105 receives the modulated signal of the codeword transmitted from the base station 200 (the received signal including an error occurring in the radio channel), the demodulator 103 of the mobile terminal 100 demodulates the modulated signal.

The physical layer LDPC decoder 104 of the mobile station 100 corrects the error of the data by performing the same decoding process as that carried out by the LDPC decoder 25 of FIG. 1 on the demodulated result obtained by the demodulator 103 to reproduce the data.

In the physical layer, the physical layer LDPC decoder 104 informs information showing whether the physical layer LDPC decoder has succeeded in the error correction on a per-packet basis to an upper hierarchical layer

In this Embodiment 2, the example in which the communication channel is a radio channel is shown, although the communication channel is not limited to a radio channel. For example, the communication channel can be a radio LAN, an optical communication channel, or a satellite communication channel.

Furthermore, in this Embodiment 2, the example in which the communication devices are the mobile terminal 100 and the base station 200 is shown, although the communication devices are not limited to the mobile terminal 100 and the base station 200. For example, the communication devices can be quantum encryption devices or the like, and this embodiment can be widely applied to whole fields of communication equipment.

Embodiment 3

FIG. 13 is a block diagram showing a communication system in accordance with Embodiment 3 of the present invention.

In above-mentioned Embodiment 1, the example in which the communication device on the transmit side is the transmitter 1 and the communication device on the receive side is the receiver 3 is shown (refer to FIG. 1). In contrast, in this Embodiment 3, an example in which a mobile terminal 300 and a base station 400 transmit and receive data to and from each other is shown.

In the figure, an upper hierarchical layer LDPC encoder 301 of the mobile terminal 300 is applied to a correction or the like in an upper hierarchical layer of a packet error occurring in a fading communication channel or the like, and constructs the LDPC encoder 14 of FIG. 1. Furthermore, the upper hierarchical layer LDPC encoder 301 can include the check matrix creation device 11 of FIG. 1, or the check matrix creation device 11 of FIG. 1 can be disposed separately from the upper hierarchical layer LDPC encoder 301.

A physical layer transmitter 302 of the mobile terminal 300 carries out a process of modulating a codeword created by the upper hierarchical layer LDPC encoder 301, and sending out a modulated signal of the codeword onto a radio channel by using an antenna 305.

When the antenna 305 receives a modulated signal of a codeword transmitted from the base station 400 (a received signal including an error occurring in the radio channel), a physical layer receiver 303 of the mobile terminal 300 carries out a process of demodulating the modulated signal.

An upper hierarchical layer LDPC decoder 304 of the mobile terminal 300 is applied to a correction or the like in the upper hierarchical layer of a packet error occurring in the fading communication channel or the like, and constructs the LDPC decoder 25 of FIG. 1. Furthermore, the upper hierarchical layer LDPC decoder 304 can include the check matrix creation device 21 of FIG. 1, or the check matrix creation device 21 of FIG. 1 can be disposed separately from the upper hierarchical layer LDPC decoder 304.

An upper hierarchical layer LDPC encoder 401 of the base station 400 is applied to a correction or the like in an upper hierarchical layer of a packet error occurring in a fading communication channel or the like, and constructs the LDPC encoder 14 of FIG. 1. Furthermore, the upper hierarchical layer LDPC encoder 401 can include the check matrix creation device 11 of FIG. 1, or the check matrix creation device 11 of FIG. 1 can be disposed separately from the upper hierarchical layer LDPC encoder 401.

A physical layer transmitter 402 of the base station 400 carries out a process of modulating a codeword created by the upper hierarchical layer LDPC encoder 401, and sending out a modulated signal of the codeword onto a radio channel by using an antenna 405.

When the antenna 405 receives a modulated signal of a codeword transmitted from the mobile terminal 300 (a received signal including an error occurring in the radio channel), a physical layer receiver 403 of the base station 400 carries out a process of demodulating the modulated signal.

An upper hierarchical layer LDPC decoder 404 of the base station 400 is applied to a correction or the like in the upper hierarchical layer of a packet error occurring in the fading communication channel or the like, and constructs the LDPC decoder 25 of FIG. 1. Furthermore, the upper hierarchical layer LDPC decoder 404 can include the check matrix creation device 21 of FIG. 1, or the check matrix creation device 21 of FIG. 1 can be disposed separately from the upper hierarchical layer LDPC decoder 404.

Next, the operation of the communication system will be explained.

When the mobile terminal 300 transmits data to the base station 400, in the upper hierarchical layer, the upper hierarchical layer LDPC encoder 301 for the fading communication channel encodes the data on a per-packet-data basis. The encoding process is the same as that carried out by the LDPC encoder 14 of FIG. 1.

When the upper hierarchical layer LDPC encoder 301 creates coded data, the physical layer transmitter 302 of the mobile terminal 300 modulates the coded data in the physical layer, and sends out a modulated signal of the coded data onto the radio channel by using the antenna 305.

When the antenna 405 receives the modulated signal of the codeword transmitted from the mobile terminal 300 (the received signal including an error occurring in the radio channel), the physical layer receiver 403 of the base station 400 demodulates the modulated signal in the physical layer.

The upper hierarchical layer LDPC decoder 404 of the base station 400 performs the same decoding process as that performed by the LDPC decoder 25 of FIG. 1 on the demodulated result obtained by the physical layer receiver 403, and then corrects the error of the data by generating the data in the upper hierarchical layer.

When an error correction has been made on a per-packet basis, the upper hierarchical layer LDPC decoder 404 transmits the error-corrected data to the communication partner via the network.

In a case in which the base station 400 transmits data to the mobile terminal 300, when the upper hierarchical layer LDPC encoder 401 for the fading communication channel receives the data via the network from the communication partner, the upper hierarchical layer LDPC encoder encodes the data on a per-packet-data basis in the upper hierarchical layer. The encoding process is the same as that carried out by the LDPC encoder 14 of FIG. 1.

When the upper hierarchical layer LDPC encoder 401 creates coded data, the physical layer transmitter 402 of the base station 400 modulates the coded data in the physical layer, and sends out a modulated signal of the coded data onto the radio channel by using the antenna 405.

When the antenna 305 receives the modulated signal of the codeword transmitted from the base station 400 (the received signal including an error occurring in the radio channel), the physical layer receiver 303 of the mobile terminal 300 demodulates the modulated signal.

The upper hierarchical physical layer LDPC decoder 304 of the mobile station 300 corrects the error of the data by performing the same decoding process as that carried out by the LDPC decoder 25 of FIG. 1 on the demodulated result obtained by the physical layer receiver 303 in the upper hierarchical layer to reproduce the data.

In this Embodiment 3, the example in which the communication channel is a radio channel is shown, although the communication channel is not limited to a radio channel. For example, the communication channel can be a radio LAN, an optical communication channel, or a satellite communication channel.

Furthermore, in this Embodiment 3, the example in which the communication devices are the mobile terminal 300 and the base station 400 is shown, although the communication devices are not limited to the mobile terminal 300 and the base station 400. For example, the communication devices can be quantum encryption devices or the like, and this embodiment can be widely applied to whole fields of communication equipment.

Embodiment 4

In this Embodiment 4, a concrete example of the parity-check matrix is shown explicitly.

For example, the following check matrix H_CH is the one of a code having a coding rate of ½ which is used by the International Standards IEEE802.16e. In the check matrix, each numeral shows p_j,l, and “−1” shows a p×p zero matrix.

$H_{\mathrm{CH}}=\begin{array}{cccccccccccccccccccccccc}-1& 94& 73& -1& -1& -1& -1& -1& 55& 83& -1& -1& 7& 0& -1& -1& -1& -1& -1& -1& -1& -1& -1& -1\\ -1& 27& -1& -1& -1& 22& 79& 9& -1& -1& -1& 12& -1& 0& 0& -1& -1& -1& -1& -1& -1& -1& -1& -1\\ -1& -1& -1& 24& 22& 81& -1& 33& -1& -1& -1& 0& -1& -1& 0& 0& -1& -1& -1& -1& -1& -1& -1& -1\\ 61& -1& 47& -1& -1& -1& -1& -1& 65& 25& -1& -1& -1& -1& -1& 0& 0& -1& -1& -1& -1& -1& -1& -1\\ -1& -1& 39& -1& -1& -1& 84& -1& -1& 41& 72& -1& -1& -1& -1& -1& 0& 0& -1& -1& -1& -1& -1& -1\\ -1& -1& -1& -1& 46& 40& -1& 82& -1& -1& -1& 79& 0& -1& -1& -1& -1& 0& 0& -1& -1& -1& -1& -1\\ -1& -1& 95& 53& -1& -1& -1& -1& -1& 14& 18& -1& -1& -1& -1& -1& -1& -1& 0& 0& -1& -1& -1& -1\\ -1& 11& 73& -1& -1& -1& 2& -1& -1& 47& -1& -1& -1& -1& -1& -1& -1& -1& -1& 0& 0& -1& -1& -1\\ 12& -1& -1& -1& 83& 24& -1& 43& -1& -1& -1& 51& -1& -1& -1& -1& -1& -1& -1& -1& 0& 0& -1& -1\\ -1& -1& -1& -1& -1& 94& -1& 59& -1& -1& 70& 72& -1& -1& -1& -1& -1& -1& -1& -1& -1& 0& 0& -1\\ -1& -1& 7& 65& -1& -1& -1& -1& 39& 49& -1& -1& -1& -1& -1& -1& -1& -1& -1& -1& -1& -1& 0& 0\\ 43& -1& -1& -1& -1& 66& -1& 41& -1& -1& -1& 26& 7& -1& -1& -1& -1& -1& -1& -1& -1& -1& -1& 0\end{array}$

Next, an example of an extension of this check matrix H_CH to create a check matrix having a coding rate of ⅓ is shown. In this example, a portion designated by A and two portions designated by I are designed by using the method in accordance with the present invention.

Each of the portion designate by A and the two portions designated by I in the above-mentioned example is divided by using the following two check matrices of g=8.

$\left[\begin{array}{cccc}0& 0& 0& 0\\ 0& 2& 4& 10\\ 0& 6& 12& 36\\ 0& 14& 28& 62\\ 0& 16& 32& 86\\ 0& 20& 40& 78\end{array}\right],\left[\begin{array}{ccc}0& 0& 0\\ 0& 4& 8\\ 0& 10& 2\\ 0& 28& 56\\ 0& 32& 64\\ 0& 38& 58\end{array}\right].$

Embodiment 5

In this Embodiment 5, an example of the check matrix H having a coding rate of ¾ is shown explicitly. In this check matrix H, p=1,620.

The above-mentioned example is configured by a combination of a matrix based on three graphs of g=10, and a matrix based on one graph of g=6.

It is also possible to delete some columns to create a check matrix having a lower coding rate as follows. In this example, the check matrix has a coding rate of 5/7. Furthermore, in this check matrix, p=1,852.

$H=\left[\begin{array}{ccccccccccccccccccccccccccccccccccc}4& 14& 15& 45& -1& -1& -1& -1& -1& -1& -1& 0& 76& 2& 76& 20& 4& -1& 306& 35& -1& -1& -1& -1& -1& 0& -1& -1& -1& -1& -1& -1& -1& -1& -1\\ 1& 5& 19& 5& 24& 95& 36& 38& 3& 12& 28& -1& -1& -1& -1& -1& -1& -1& -1& -1& -1& -1& -1& -1& -1& 0& 0& -1& -1& -1& -1& -1& -1& -1& -1\\ 0& 2& 39& 81& -1& -1& -1& -1& -1& -1& -1& -1& -1& -1& -1& -1& -1& -1& -1& -1& 0& 0& 58& 12& 1& -1& 0& 0& -1& -1& -1& -1& -1& -1& -1\\ 8& 1& 67& 7& -1& -1& -1& -1& -1& -1& -1& 10& 152& 160& 34& 190& -1& 200& 226& -1& -1& -1& -1& -1& -1& -1& -1& 0& 0& -1& -1& -1& -1& -1& -1\\ 5& 9& 1& 120& 123& 13& 209& 180& 4& 114& 11& -1& -1& -1& -1& -1& -1& -1& -1& -1& -1& -1& -1& -1& -1& -1& -1& -1& 0& 0& -1& -1& -1& -1& -1\\ 2& 50& 91& 8& -1& -1& -1& -1& -1& -1& -1& -1& -1& -1& -1& -1& -1& -1& -1& -1& 8& 38& 40& 142& 152& -1& -1& -1& -1& 0& 0& -1& -1& -1& -1\\ 7& 41& 105& 16& -1& -1& -1& -1& -1& -1& -1& 17& 133& 30& 2& 323& 77& 9& -1& 259& -1& -1& -1& -1& -1& -1& -1& -1& -1& -1& 0& 0& -1& -1& -1\\ 3& 18& 57& 60& 18& 342& 345& 60& 31& 100& 34& -1& -1& -1& -1& -1& -1& -1& -1& -1& -1& -1& -1& -1& -1& -1& -1& -1& -1& -1& -1& 0& 0& -1& -1\\ 5& 19& 38& 77& -1& -1& -1& -1& -1& -1& -1& -1& -1& -1& -1& -1& -1& -1& -1& -1& 1& 95& 16& 96& 35& -1& -1& -1& -1& -1& -1& -1& 0& 0& -1\\ 19& 30& 141& 6& -1& -1& -1& -1& -1& -1& -1& -1& -1& -1& -1& -1& 6& 73& 30& 167& -1& -1& -1& -1& -1& -1& -1& -1& -1& -1& -1& -1& -1& 0& 0^{″}\end{array}\right]$

Embodiment 6

In this Embodiment 6, a concrete example of the parity-check matrix is shown explicitly.

For example, the following check matrix H_CH is a slight modification of the check matrix (the check matrix described in above-mentioned Embodiment 4) of a code having a coding rate of ½ which is used by the International Standards IEEE802.16e. In the check matrix, each numeral shows p_j,l, −1 shows a p×p zero matrix, and 0″ shows a p×p matrix as shown in the following equation (5).

$\begin{array}{cc}{H}_{\mathrm{CH}}=\begin{array}{cccccccccccccccccccccccc}-1& 94& 73& -1& -1& -1& -1& -1& 55& 83& -1& -1& 7& 0& -1& -1& -1& -1& -1& -1& -1& -1& -1& -1\\ -1& 27& -1& -1& -1& 22& 79& 9& -1& -1& -1& 12& -1& 0& 0& -1& -1& -1& -1& -1& -1& -1& -1& -1\\ -1& -1& -1& 24& 22& 81& -1& 33& -1& -1& -1& 0& -1& -1& 0& 0& -1& -1& -1& -1& -1& -1& -1& -1\\ 61& -1& 47& -1& -1& -1& -1& -1& 65& 25& -1& -1& -1& -1& -1& 0& 0& -1& -1& -1& -1& -1& -1& -1\\ -1& -1& 39& -1& -1& -1& 84& -1& -1& 41& 72& -1& -1& -1& -1& -1& 0& 0& -1& -1& -1& -1& -1& -1\\ -1& -1& -1& -1& 46& 40& -1& 82& -1& -1& -1& 79& 0& -1& -1& -1& -1& 0& 0& -1& -1& -1& -1& -1\\ -1& -1& 95& 53& -1& -1& -1& -1& -1& 14& 18& -1& -1& -1& -1& -1& -1& -1& 0& 0& -1& -1& -1& -1\\ -1& 11& 73& -1& -1& -1& 2& -1& -1& 47& -1& -1& -1& -1& -1& -1& -1& -1& -1& 0& 0& -1& -1& -1\\ 12& -1& -1& -1& 83& 24& -1& 43& -1& -1& -1& 51& -1& -1& -1& -1& -1& -1& -1& -1& 0& 0& -1& -1\\ -1& -1& -1& -1& -1& 94& -1& 59& -1& -1& 70& 72& -1& -1& -1& -1& -1& -1& -1& -1& -1& 0& 0& -1\\ -1& -1& 7& 65& -1& -1& -1& -1& 39& 49& -1& -1& -1& -1& -1& -1& -1& -1& -1& -1& -1& -1& 0& 0\\ 43& -1& -1& -1& -1& 66& -1& 41& -1& -1& -1& 26& 7& -1& -1& -1& -1& -1& -1& -1& -1& -1& -1& 0\end{array}I\left(0^{″}\right)=\left[\begin{array}{ccccc}1& & & & \\ 1& 1& & & \\ & \ddots & \ddots & & \\ & & 1& 1& \\ & & & 1& 1\end{array}\right]& \left(5\right)\end{array}$

Next, an example of an extension of this check matrix H_CH to create a check matrix having a coding rate of 1/3 is shown. In this example, a portion designated by A and two portions designated by I are designed by using the method in accordance with the present invention.

INDUSTRIAL APPLICABILITY

As mentioned above, according to the check matrix generation method in accordance with the present invention, a parity-check matrix having a good performance and having a regular configuration can be created. Therefore, the check matrix generation method in accordance with the present invention is suitable for use in a transmitter that encodes information bits using this parity-check matrix and transmits them, a receiver that decodes information bits by using this parity-check matrix, a communication system consisting of the transmitter and the receiver, and so on.

Claims

1. A check matrix creation device for creating a quasi-cyclic matrix which is a parity check matrix for an LDPC code, said check matrix creation device comprising: a circulant permutation matrix setting means for preparing a plurality of circulant permutation matrices; anda quasi-cyclic matrix creation means for arranging the plurality of circulant permutation matrices prepared by said circulant permutation matrix setting means both in a row direction and in a column direction to create a quasi-cyclic matrix.

2. The check matrix creation device according to claim 1, wherein the circulant permutation matrix setting means prepares the plurality of circulant permutation matrices each having an inner diameter of six or larger.

3. The check matrix creation device according to claim 1, wherein when arranging the plurality of circulant permutation matrices both in the row direction and in the column direction to create a quasi-cyclic matrix, the quasi-cyclic matrix creation means divides said circulant permutation matrices into parts in the column direction without changing components of the quasi-cyclic matrix connected to a specific row, and satisfies a constraint of non-occurrence of a loop in a relationship between nodes in the column direction and nodes in the row direction of the quasi-cyclic matrix after the division is done.

4. The check matrix creation device according to claim 1, wherein when arranging the plurality of circulant permutation matrices both in the row direction and in the column direction to create the quasi-cyclic matrix, the quasi-cyclic matrix creation means divides said circulant permutation matrices into parts in the row direction without changing components of the quasi-cyclic matrix connected to a specific row, and satisfies a constraint of non-occurrence of a loop in a relationship between nodes in the row direction and nodes in the column direction of the quasi-cyclic matrix after the division is done.

5. The check matrix creation device according to claim 3, wherein when the quasi-cyclic matrix is represented by a bipartite graph and each of the plurality of circulant permutation matrices is a matrix of p rows and p columns, the quasi-cyclic matrix creation means connects between nodes of two subgraphs by using p branches.

6. The check matrix creation device according to claim 3, wherein when the quasi-cyclic matrix is represented by a bipartite graph and each of the plurality of circulant permutation matrices is a matrix of p rows and p columns, the quasi-cyclic matrix creation means connects between nodes of two subgraphs by using 2*p or more branches and satisfies a constraint of non-occurrence of a loop between nodes connected using 2*p or more branches.

7. The check matrix creation device according to claim 1, wherein when preparing the plurality of circulant permutation matrices, the circulant permutation matrix setting means prepares, as apart of the circulant permutation matrices, a circulant permutation matrix I(0″) as shown below.

8. The check matrix creation device according to claim 1, wherein when preparing the plurality of circulant permutation matrices, the circulant permutation matrix setting means prepares, as a part of the circulant permutation matrices, a stair-like submatrix, as shown below, which is a combination of circulant permutation matrices I(0) and I(0″).

9. The check matrix creation device according to claim 1, wherein when preparing the plurality of circulant permutation matrices, the circulant permutation matrix setting means prepares circulant permutation matrices having different column weights and different inner diameters.

10. A check matrix creation method of creating a quasi-cyclic matrix which is a parity-check matrix for an LDPC code, said check matrix creation method comprising: a circulant permutation matrix setting step of a circulant permutation matrix setting means preparing a plurality of circulant permutation matrices each having an inner diameter of six or larger; anda quasi-cyclic matrix creating step of a quasi-cyclic matrix creation means arranging the plurality of circulant permutation matrices prepared by said circulant permutation matrix setting means both in a row direction and in a column direction to create a quasi-cyclic matrix.

11. A check matrix creation program for creating a quasi-cyclic matrix which is a parity-check matrix for an LDPC code, said check matrix creation program causing a computer to carry out: a circulant permutation matrix setting process of a circulant permutation matrix setting means preparing a plurality of circulant permutation matrices each having an inner diameter of six or larger; anda quasi-cyclic matrix creating process of a quasi-cyclic matrix creation means arranging the plurality of circulant permutation matrices prepared by said circulant permutation matrix setting means both in a row direction and in a column direction to create a quasi-cyclic matrix.

12. A transmitter comprising: a circulant permutation matrix setting means for preparing a plurality of circulant permutation matrices each having an inner diameter of six or larger;a quasi-cyclic matrix creation means for arranging the plurality of circulant permutation matrices prepared by said circulant permutation matrix setting means both in a row direction and in a column direction to create a quasi-cyclic matrix which is a parity-check matrix for an LDPC code;a codeword creation means for creating a codeword from predetermined information bits and the quasi-cyclic matrix created by said quasi-cyclic matrix creation means; anda transmitting means for modulating the codeword created by said codeword creation means and transmitting a modulated signal of said codeword.

13. A receiver comprising: a circulant permutation matrix setting means for preparing a plurality of circulant permutation matrices each having an inner diameter of six or larger;a quasi-cyclic matrix creation means for arranging the plurality of circulant permutation matrices prepared by said circulant permutation matrix setting means both in a row direction and in a column direction to create a quasi-cyclic matrix which is a parity-check matrix for an LDPC code;a receiving means for receiving the modulated signal to demodulate this modulated signal; anda decoding means for decoding a demodulated result obtained by said receiving means to generate information bits by using the quasi-cyclic matrix created by said quasi-cyclic matrix creation means.

14. A communication system provided with a transmitter that creates a codeword from predetermined information bits and a parity-check matrix for an LDPC code, modulates said codeword, and transmits a modulated signal of said codeword, and a receiver that receives and demodulates the modulated signal of the codeword transmitted from said transmitter, and decodes a demodulated result of said modulated signal to generate said information bits by using said quasi-cyclic matrix, wherein each of said transmitter and said receiver comprises a check matrix creation device for creating a quasi-cyclic matrix which is a parity-check matrix for an LDPC code, and said check matrix creation device is comprised of:a circulant permutation matrix setting means for preparing a plurality of circulant permutation matrices each having an inner diameter of six or larger; anda quasi-cyclic matrix creation means for arranging the plurality of circulant permutation matrices prepared by said circulant permutation matrix setting means both in a row direction and in a column direction to create a quasi-cyclic matrix which is a parity-check matrix for an LDPC code.