Patent Application
20200027644
This application claims the benefit of priority to Korean Patent Application No. 10-2018-0083974 filed on Jul. 19, 2018 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety.
The present disclosure relates to a chip inductor and a method of manufacturing the same, and more particularly, to a thin-film chip inductor and a method of manufacturing the same.
As the miniaturization and thinning of various electronic devices have accelerated with the development of information technology (IT), thin-film inductors have also been required to be miniaturized and thinned. In the case of a power inductor, a chip size has decreased, but an increase in the number of turns of a coil pattern (fine patterning), a development of high-permeability materials, and a technique to increase a pattern height are required to achieve miniaturization of products without the loss of chip characteristics such as inductance, Rdc, and the like.
An aspect of the present disclosure is to provide a chip inductor which prevents damage to an insulating member included in the chip inductor.
According to an aspect of the present disclosure, a chip inductor includes a body having a coil and an insulating member on which the coil is disposed, and external electrodes disposed on external surfaces of the body. The insulating layers are disposed on one surface of the insulating member in the body and another surface opposing the one surface, respectively, and are made of a material different from a material of the insulating member. The insulating member and the insulating layers constitute a multilayer structure. The coil includes a top coil and a bottom coil disposed on a top surface and a bottom surface of the multilayer structure, respectively. The top and bottom coils are connected by a via penetrating through the top and bottom surfaces of the multilayer structure.
The insulating layers may be made of an epoxy-novolac-based resin having a hydroxyl group.
Entire surfaces of the insulating member maybe covered with the insulating layers.
The coil may include a plurality of conductive layers, which includes a first conductive layer disposed on the insulating layers.
Among the plurality of conductive layers, the first conductive layer brought into contact with the insulating layers may include at least one of nickel (Ni), niobium (Nb), molybdenum (Mo), and palladium (Pd).
Among the plurality of conductive layers, the first conductive layer brought into contact with the insulating layers may be a copper (Cu) plating layer.
The plurality of conductive layers may further include a second conductive layer, disposed on the first conductive layer, having a thickness greater than a thickness of the first conductive layer.
A filler may be impregnated in the insulating member.
A glass fabric may be included in the insulating member.
The insulating member may have a thickness ranging from 15 micrometers to 40 micrometers.
The insulating member may include a polyimide material.
Each of the insulating layers may have a thickness ranging from 1 μm to 25 μm.
A through-hole may be disposed on the multilayer structure, spaced apart from the via, and filled with the encapsulant.
According to an aspect of the present disclosure, a method of manufacturing a chip inductor includes preparing a multilayer structure including an insulating member and insulating layers attached to one surface and another surface of the insulating member, respectively, providing metal layers, each having a predetermined thickness, on top and bottom surfaces of the multilayer structure, respectively, exposing the multilayer structure by patterning the metal layers in such a manner that the metal layer has a plurality of openings, processing a via hole penetrating through the multilayer structure, forming top and bottom coils on exposed surfaces of the multilayer structure, dicing the multilayer structure to be divided in the form of individual chips, insulating surfaces of the top and bottom coils, and forming a body encapsulating the top and bottom coils and forming external electrodes on external surfaces of the body. The exposing the multilayer structure includes an etching process.
The method may include performing a desmearing process after processing the via hole.
The desmearing process may use a CO2 laser.
The insulating member and the insulating layers in the multilayer structure may include different materials from each other.
The insulating layer may be made of an epoxy-novolac-based resin having a hydroxyl group.
The above and other aspects, features, and advantages of the present disclosure will be more clearly understood from the following detailed description, taken in conjunction with the accompanying drawings, in which:
Hereinafter, examples of the present disclosure will be described as follows with reference to the attached drawings.
The present disclosure may, however, be embodied in many different forms and should not be construed as being limited to the examples set forth herein. Rather, these examples are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the present disclosure to those skilled in the art.
The same reference numerals are used to designate the same elements throughout the drawings. In the drawings, the sizes and relative sizes of layers and regions may be exaggerated for clarity.
It will be understood that the terms “comprises,” “comprising,” “includes” and/or “including,” when used herein, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
Hereinafter, a chip inductor according to an example and a method of manufacturing the same will be described, but is not limited thereto.
Chip Inductor
Referring to
The external electrode 2 includes a first external electrode 21 and a second external electrode 22 disposed on the external surfaces of the body 1 to oppose each other in a length direction L. Although the external electrode 2 has a shape extending from one surface of the body 1 to four adjacent surfaces thereof, the shape of the external electrode 2 is not limited thereto and may be modified into various shapes as needed by those skilled in the art. For example, the external electrode 2 may have an ‘L’ shape or an ‘I’ shape. Since the external electrode 2 is connected to a lead portion of an internal coil, the external electrode 2 should include a material having improved electrical conductivity.
The body 1 has a first end surface and a second end surface disposed to oppose each other in the length direction L, a first side surface and a second side surface disposed to oppose each other in a width direction W, and has a substantially hexahedral shape having a top surface and a bottom surface disposed to oppose each other in a thickness direction T.
An insulating member 11, having a through-hole Hh and a via hole Hv, is included in the body 1. The insulating member 11 serves to mechanically support the coil 12 disposed thereon and to facilitate the formation of a coil.
Insulating layers 111 and 112 are respectively disposed on one surface and the other surface of the insulating member 11 opposing the one surface.
The insulating member 11 and the insulating layers 111 and 112 constitute a multilayer structure C laminated in the thickness direction T of the body 1.
The multilayer structure C has a via hole Hv, passing through top and bottom surfaces of the multilayer structure C, and a through-hole Hh spaced apart from the via hole Hv.
The via hole Hv is filled with a conductive material in such a manner that a via V is formed to connect a top coil and a bottom coil to each other.
The insulating member 11 and the insulating layers 111 and 112 in the multilayer structure C are formed of different materials from each other to have different physical properties.
The insulating member 11 includes a material, having an insulating property, and may be, for example, a resin layer of a thin film made of a polyimide material. The insulating member 11 may be a magnetic insulator having a magnetic property as well as the insulating property. For example, the insulating member 11 may have a structure in which a filler is impregnated in a resin. The filler refers to particles added to reinforce a bending property or mechanical rigidity of the insulating member 11, and a type or a content of the filler may be appropriately selected depending on characteristics of the insulating member 11. The insulating member 11 may include a resin and a glass fabric impregnated with the resin, and may be an Ajinomoto build-up film (ABF), a PID resin, or the like. A thickness of the insulating member 11 is more advantageous as the insulating member 11 becomes thinner. For example, the insulating member 11 has a thickness, in detail, ranging from 10 micrometers (μm) to 60 μm and, in further detail, ranging from 15 μm to 40 μm, to support a coil and stably maintain a coil shape when a coil is formed. When the insulating member has a thickness less than 10 μm, a coil may not be supported properly or a rolling phenomenon may occur during a process of forming the coil. When the insulating member 11 has a thickness greater than 60 μm, it is difficult to sufficiently increase a thickness of a coil, on the basis of a limited chip thickness of a coil component. In further detail, the insulating member 11 may have a thickness ranging from 10 μm to 35 μm. In this case, the coil may be stably supported, while implementing a desired thickness of the coil. Thus, the rolling phenomenon may be significantly reduced during formation of the coil.
The insulating layers 111 and 112, disposed on one surface and the other surface of the insulating member 11, respectively, have a structure covering the entirety of the one surface and the other surface. In this case, the one surface and the other surface of the insulating member 11 are not exposed outwardly and are protected by an insulating layer.
The insulating layer 111 or 112 has a thickness, in detail, ranging from 1 μm to 25 μm. When the insulating layer 111 or 112 has a thickness less than 1 μm, possibility of damaging the insulating layer 111 or 112 during a desmearing process, described later, is significantly increased. When the insulating layer 111 or 112 has a thickness greater than 25 μm, it may be difficult to apply the configuration, in which insulating layers 111 and 112 are disposed on the one surface and the other surface of the insulating member 11, to an existing facility equipment.
The insulating layers 111 and 112 are made of a material different from a material of the insulating member 11. In detail, the insulating layers 111 and 112 include an epoxy-novolac-based resin having a hydroxyl group. The insulating layers 111 and 112 serve to protect the insulating member 11. Specifically, the insulating member 11 is thinned with a low profile tendency to decrease a thickness of a chip inductor. As the insulating member 11 is thinned, when a via hole is formed to penetrate through the insulating member 11, a portion of an insulating material remains around the via hole and is injected into the processed via hole or the insulating member 11 is severely eroded by an etchant during an etching step in a desmearing process, after processing the via hole, to frequently damage the insulating member 11. The insulating layers 111 and 112 may be protective layers covering the one surface and the other surface of the insulating member 11 to prevent the above issue. The insulating layers 111 and 112 are protective layers preventing exposure of a filler, erosion of a remaining resin, or exposure of a glass fabric in the insulating member 11 during an etching step in the desmearing process after processing the via hole. In addition, since the insulating layers 111 and 112 are appropriate to directly perform chemical copper plating on the insulating layers 111 and 112, it is unnecessary to introduce an expensive sputtering process on the insulating layers 111 and 112. Thus, mass productivity of the chip inductor may be improved.
Since the insulating layers 111 and 112 are made of a material pyrolyzed at about 370 degrees Celsius, heat resistant characteristics maybe improved in a press process, a stacking process, a lamination process, or the like, compared with a case in which a coil is directly formed on an insulating member.
In addition, since the insulation layers 111 and 112 are made of a material having improved adhesion to copper (Cu) constituting a coil, delamination of the coil may be prevented to improve reliability of the chip inductor. In this regard, the insulating layers 111 and 112 include an epoxy-novolac-based resin having a hydroxyl group. When a desmearing process is performed to fabricate a chip inductor, a polar group generated through a desmear reaction mechanism are increased to improve adsorption to palladium (Pd). Thus, affinity with the chemical copper plating may be enhanced. A known copper clad laminate (CCL), used as a support member of a chip inductor, means that adhesion is improved when a chemical copper plating is performed thereon.
Apart from the via hole Hv passing through top and bottom surfaces of the multilayer structure C, a through-hole Hh is formed at a position spaced apart from the via hole Hv. The through-hole Hh is filled with an encapsulant 13 described later. A permeability of a coil component is increased by the encapsulant filling the through-hole Hh.
A coil 12 includes a coil body 121 wound a plurality of times and a lead portion 122 connected to both ends of the coil body 121. The lead portion 122 includes a first lead portion 122a connected to a first external electrode 21 and a second lead portion 122b connected to a second external electrode 22.
The coil 12 includes a plurality of conductive layers. The plurality of conductive layers include a first conductive layer 12a disposed at a lowermost portion to be in contact with the insulating layers 111 and 112. The first conductive layer 12a may be a copper (Cu) plating layer or a layer containing at least one of nickel (Ni), niobium (Nb), molybdenum (Mo), and palladium (Pd).
In the case in which the first conductive layer 12a is a copper (Cu) plating layer, the top and bottom surfaces of the multilayer structure C include insulating layers, as described above. Therefore, although a Cu plating layer is directly formed on the insulating layer using a semi-additive process (SAP), delamination of the Cu plating layer may be prevented. In the case in which the first conductive layer 12a includes a Cu plating layer, manufacturing yield and reliability for manufacturing the chip inductor may be improved.
A case in which the first conductive layer 12a includes at least one of Ni, Nb, Mo, and Pd is a case in which a seed layer is formed on the insulating layer using a sputtering method. Since the first conductive layer 12a is disposed at a lowermost portion of the coil, the first conductive layer 12a substantially serves as a seed layer for a second conductive layer 12b disposed thereon and having a thickness greater than a thickness of the first conductive layer 12a. When the first conductive layer 12a is formed by applying a sputtering process, a thinner and more uniform seed layer may be implemented.
Method of Manufacturing Chip Inductor
Referring to
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The top and bottom coils may be formed by any method, and, among the plurality of conductive layers, a first conductive layer 12a brought into direct contact with the multilayer structure may be formed using a sputtering method or a chemical copper plating method. Although the first conductive layer 12a is formed using the chemical copper plating method, adhesion between the insulating layer and a chemical copper plating layer is greater than adhesion between the insulating member and the chemical copper plating layer. Therefore, delamination of the first conductive layer 12a may be prevented. A second conductive layer 12b is formed on the first conductive layer 12a to substantially determine a thickness of the coil, and a manner of forming the second conductive layer 12b is not limited. The second conductive layer 12b may be formed by anisotropic plating using the first conductive layer 12a as a seed layer. Alternatively, the second conductive layer 12b maybe formed by laminating an insulating material to fill the first conductive layer 12a, patterning the insulating material, and filling an opening of the pattern insulating material with the first conductive layer 12a.
Referring to
According to an example, one of various effects of the present disclosure is prevent an open defect or the like of a chip inductor. As a result, reliability of the chip inductor is improved.
While examples have been shown and described above, it will be apparent to those skilled in the art that modifications and variations could be made without departing from the scope of the present invention as defined by the appended claims.
| Number | Date | Country | Kind |
|---|---|---|---|
| 10-2018-0083974 | Jul 2018 | KR | national |
