Claims
- 1. A method for generating a gray box model from a circuit for static circuit analysis, said circuit having one or more inputs, said method comprising the steps of:
- a. ordering said one or more input and selecting the first in order input as the input under analysis;
- b. initiating a path search from said input under analysis;
- c. characterizing said input under analysis;
- d. determining whether a state follows said input under analysis and continuing from said step of initiating with the next in order input, if any, as the input under analysis or continuing at the step of terminating said method if there is no next in order input;
- e. calculating delay for said stage;
- f. characterizing said stage, if said stage is an output; and continuing from said step of determining, if said stage is not a latch; and
- g. incorporating said input characterization, said delay if said stage is an input and said output characterization, if any, into said gray box model.
- 2. The method of claim 1 wherein said step of characterizing said input under analysis comprises
- performing a simulation for each possible slope for said input under analysis; and
- then calculating an input slope factor for said input under analysis.
- 3. The method of claim 1 wherein said step of characterizing said output stage comprises
- performing a simulation for each possible load for said output; and
- then calculating a drive resistance and an intrinsic delay for said output stage.
CROSS REFERENCE TO RELATED APPLICATIONS
This application is a division of and claims the benefit of U.S. patent application Ser. No. 08/429,430, filed May 1, 1995, U.S. Pat. No. 5,740,347 the disclosure of which, including Appendices A and B, is hereby incorporated by reference in its entirety for all purposes.
US Referenced Citations (6)
Non-Patent Literature Citations (1)
Entry |
Epic Design Technology, Inc., PathMill User Manual, Release 3.00LCS (Jan. 1994). |
Divisions (1)
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Number |
Date |
Country |
Parent |
429430 |
May 1995 |
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