Claims
- 1. A circuit for detecting if an arithmetic/logic combination of a first multibit number A of N bits and a second multibit B of N bits equals a third multibit number C of N bits prior to availability of the arithmetic/logic combination of A and B, said circuit comprising:
- a plurality of N PGK generating circuits, each PGK generating circuit receiving a corresponding nth bit of said first multibit number A.sub.n, a corresponding nth bit of said second multibit number B.sub.n, each PGK generating circuit generating a corresponding propagate signal P.sub.n at a propagate output, generating a corresponding generate signal G.sub.n at a generate output and generating a corresponding kill signal K.sub.n at a kill output;
- a plurality of N zero circuits, one zero circuit corresponding to one of said PGK generating circuits, each of said zero circuits including
- an exclusive OR circuit having a first input receiving said corresponding propagate signal P.sub.n and a second input receiving said kill signal K.sub.n-1 of a prior PGK generating circuit if a corresponding nth bit of said third multibit number C.sub.n is "0" and a corresponding prior bit of said third multibit number C.sub.n-1 is "0", said zero circuit generating a corresponding zero signal Z.sub.n at an output,
- an exclusive NOR circuit having a first input receiving said corresponding propagate signal P.sub.n and a second input receiving said generate signal G.sub.n-1 of a prior PGK generating circuit if a corresponding nth bit of said third multibit number C.sub.n is "0" and a corresponding prior bit of said third multibit number C.sub.n-1 is "1", said zero circuit generating a corresponding zero signal Z.sub.n at an output,
- an exclusive NOR circuit having a first input receiving said corresponding propagate signal P.sub.n and a second input receiving said kill signal K.sub.n-1 of a prior PGK generating circuit if a corresponding nth bit of said third multibit number C.sub.n is "1" and a corresponding prior bit of said third multibit number C.sub.n-1 is "0", said zero circuit generating a corresponding zero signal Z.sub.n at an output,
- an exclusive OR circuit having a first input receiving said corresponding propagate signal P.sub.n and a second input receiving said generate signal G.sub.n-1 of a prior PGK generating circuit if a corresponding nth bit of said third multibit number C.sub.n is "1" and a corresponding prior bit of said third multibit number C.sub.n-1 is "1", said zero circuit generating a corresponding zero signal Z.sub.n at an output; and
- an N input AND circuit receiving said corresponding zero signals Z.sub.n from each of said zero circuits for generating an equality signal indicating the arithmetic/logic combination of said first multibit number A and said second multibit number B equals said third multibit number C if all of said zero signals Z.sub.n are "1".
- 2. The circuit of claim 1, wherein:
- N equals 32; and
- said N input AND circuit includes
- a first four input AND gate having a output forming the output of said N input AND circuit and four inputs,
- 4 eight input AND gates, each having an output connected to a corresponding input of said first 4 input AND gate, each including a two input NOR gate having an output forming the output of said eight input AND gate and two inputs, and 2 four input NAND gates having an output connected to a corresponding input of said two input NOR gate and four inputs receiving corresponding zero signals.
- 3. The circuit of claim 1, further comprising:
- an arithmetic/logic circuit connected to receive said propagate signal P.sub.n, said generate signal G.sub.n and said kill signal K.sub.n from each of said PGK generating circuits for generating corresponding bit resultants of said arithmetic/logic combination of said first multibit number A and said second multibit number B.
- 4. The circuit of claim 1, wherein:
- each of said plurality of N PGK generating circuits includes
- an exclusive NOR circuit having a first input receiving said corresponding nth bit of said first multibit number A.sub.n and a second input receiving said corresponding nth bit of said second multibit number B.sub.n, said exclusive NOR circuit generating a corresponding propagate signal P.sub.n at an output,
- a first inverter circuit having an input receiving said corresponding nth bit of said first multibit number A.sub.n and an output,
- a NOR circuit having a first input receiving said output of said first inverter circuit and a second input receiving said corresponding nth bit of said second multibit number B.sub.n, said AND circuit generating a corresponding generate signal G.sub.n at an output,
- a second inverter circuit having an input receiving said corresponding nth bit of said second multibit number B.sub.n and an output,
- a NOR circuit having a first input receiving said corresponding nth bit of said first multibit number A.sub.n and a second input receiving said output of said second inverter circuit, said NOR circuit generating a corresponding kill signal K.sub.n at an output.
- 5. The circuit of claim 1, wherein:
- each of said plurality of N PGK generating circuits includes
- a first AND circuit having a first input receiving said corresponding nth bit of said second multibit number B.sub.n, a second input receiving a first arithmetic logic unit control signal and an output,
- a first inverter circuit having an input receiving said corresponding nth bit of said second multibit number B.sub.n and an output,
- a second AND circuit having a first input receiving said output of said first inverter circuit, a second input receiving a second arithmetic logic unit control signal and an output,
- a first NOR circuit having a first input receiving said output of said first AND circuit, a second input receiving said output of said second AND circuit and an output,
- a third AND circuit having a first input receiving said corresponding nth bit of said second multibit number B.sub.n, a second input receiving a third arithmetic logic unit control signal and an output,
- a fourth AND circuit having a first input receiving said output of said first inverter circuit, a second input receiving a fourth arithmetic logic unit control signal and an output,
- a second NOR circuit having a first input receiving said output of said third AND circuit, a second input receiving said output of said fourth AND circuit and an output,
- a fifth AND circuit having a first input receiving an ARITH signal having a first digital state indicating an arithmetic function and a second digital state opposite to said first digital state indicating a logical function, a second input receiving said corresponding nth bit of said first multibit number A.sub.n, a third input receiving said output of said first NOR circuit, said fifth AND circuit generating a corresponding generate signal G.sub.n at an output,
- an OR circuit having a first input receiving said corresponding nth bit of said first multibit number A.sub.n, a second input receiving said output of said first NOR circuit and an output,
- a NAND circuit having a first input receiving said ARITH signal, a second input receiving said output of said OR circuit, said NAND circuit generating a corresponding kill signal K.sub.n at an output,
- a fifth AND circuit having a first input receiving said corresponding nth bit of said first multibit number A.sub.n, a second input receiving said output of said first NOR circuit and an output,
- a second inverter circuit having an input receiving said corresponding nth bit of said first multibit number A.sub.n and an output,
- a sixth AND circuit having a first input receiving said output of said second inverter circuit, a second input receiving said output of said second NOR circuit and an output, and
- a third NOR circuit having a first input receiving said output of said fifth AND circuit, a second input receiving said output of said sixth AND circuit, said third NOR circuit generating a corresponding propagate signal P.sub.n at an output.
- 6. A method for detecting if an arithmetic/logic combination of a first multibit number A of N bits and a second multibit B of N bits equals a third multibit number C of N bits prior to availability of the arithmetic/logic combination of A and B, said method comprising the steps of:
- forming a propagate signal P.sub.n for each of said N bits from a corresponding nth bit of said first multibit number A.sub.n and a corresponding nth bit of said second multibit number B.sub.n ;
- forming a generate signal G.sub.n for each of said N bits from said corresponding nth bit of said first multibit number A.sub.n and said corresponding nth bit of said second multibit number B.sub.n ;
- forming a kill signal K.sub.n for each of said N bits from said corresponding nth bit of said first multibit number A.sub.n and said corresponding nth bit of said second multibit number B.sub.n ;
- forming a zero signal Z.sub.n for each of said N bits, said zero signal Z.sub.n formed
- by an exclusive OR of said corresponding propagate signal P.sub.n and said kill signal K.sub.n-1 of a prior bit if a corresponding nth bit of said third multibit number C.sub.n is "0" and a corresponding prior bit of said third multibit number C.sub.n-1 is "0",
- by an exclusive NOR of said corresponding propagate signal P.sub.n and said generate signal G.sub.n-1 of a prior bit if a corresponding nth bit of said third multibit number C.sub.n is "0" and a corresponding prior bit of said third multibit number C.sub.n-1 is "1",
- by an exclusive NOR of said corresponding propagate signal P.sub.n and kill signal K.sub.n-1 of a prior bit if a corresponding nth bit of said third multibit number C.sub.n is "1" and a corresponding prior bit of said third multibit number C.sub.n-1 is "0",
- by an exclusive OR of said corresponding propagate signal P.sub.n and a second input receiving said generate signal G.sub.n-1 of a prior bit if a corresponding nth bit of said third multibit number C.sub.n is "1" and a corresponding prior bit of said third multibit number C.sub.n-1 is "1"; and
- indicating equality of the arithmetic/logic combination of said first multibit number A and said second multibit number B and said third multibit number C if all of said zero signals Z.sub.n are "1".
- 7. The method of claim 6, further comprising:
- forming the arithmetic/logic combination of said first multibit number A and said second multibit number B from said propagate signal P.sub.n, said generate signal G.sub.n and said kill signal K.sub.n from each bit.
- 8. The method of claim 6, wherein:
- said step of forming a propagate signal P.sub.n for each of said N bits consists of forming an exclusive NOR of said corresponding nth bit of said first multibit number A.sub.n and said corresponding nth bit of said second multibit number B.sub.n ;
- said step of forming a generate signal G.sub.n for each of said N bits consists of inverting said corresponding nth bit of said first multibit number A.sub.n and forming a NOR of said inverted corresponding nth bit of said first multibit number A.sub.n and said corresponding nth bit of said second multibit number B.sub.n ;
- said step of forming a kill signal K.sub.n for each of said N bits consists of inverting said corresponding nth bit of said second multibit number B.sub.n and forming a NOR circuit of said corresponding nth bit of said first multibit number A.sub.n and said inverted corresponding nth bit of said second multibit number B.sub.n.
- 9. The method of claim 6, further comprising:
- forming a first intermediate signal X.sub.n for each nth bit according the function
- X.sub.n =not((B.sub.n AND CO) OR (B.sub.n AND C2));
- forming a second intermediate signal Y.sub.n for each nth bit according to the function
- Y.sub.n =not((B.sub.n AND C1) OR (B.sub.n AND C3));
- said step of forming said propagate signal P.sub.n for each of said N bits consists of forming the following function
- P.sub.n =not ((X.sub.n AND A.sub.n) OR (Y.sub.n AND A.sub.n ));
- said step of forming said generate signal G.sub.n for each of said N bits consists of forming the following function
- G.sub.n =ARITH AND A.sub.n AND X.sub.n ;
- said step of forming said Kill signal K.sub.n for each of said N bits consists of forming the following function
- K.sub.n =not (ARITH AND (A.sub.n OR X.sub.n));
- where: A.sub.n is the corresponding nth bit of the first multibit number; A.sub.n is the inverse of A.sub.n ; B.sub.n is the corresponding nth bit of the second multibit number; B.sub.n is the inverse of B.sub.n ; C0, C1, C2 and C3 are arithmetic logic unit control signals; and ARITH is a signal having a first digital state indicating an arithmetic function and a second digital state opposite to said first digital state indicating a logical function.
Parent Case Info
This application is a continuation of U.S. patent application Ser. No. 08/166,370 filed Dec. 13, 1993, now U.S. Pat. No. 5,508,950, which is a divisional of U.S. patent application Ser. No. 07/922,926 filed Jul. 31, 1992, now U.S. Pat. No. 5,270,955.
US Referenced Citations (6)
Divisions (1)
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922926 |
Jul 1992 |
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Continuations (1)
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166370 |
Dec 1993 |
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