Claims
- 1. A computer processor, said computer processor comprising:
- an execution unit, said execution unit executing a first instruction, said execution unable to receive an additional instruction for execution until execution of said first instruction completes, said execution unit indicating a number of clock cycles required to complete execution of said first instruction;
- a reservation station, said reservation station comprising a plurality of entries containing instructions to be executed, each entry comprising a field indicating a number of clock cycles until an instruction associated with that entry is ready to execute; and
- an instruction scheduler, said instruction scheduler locating a first entry in said reservation station wherein said field indicating a number of clock cycles until said associated instruction is ready to execute matches said number of clock cycles required to complete execution of said first instruction, said scheduler dispatching said associated instruction from said first entry to said execution unit.
- 2. The computer processor of claim 1 wherein said scheduler determines whether said associated instruction from said first entry requires said execution unit for execution before dispatching said associated instruction from said first entry.
- 3. The computer processor of claim 2 wherein said execution resource indicates a number of clock cycles until a result will be available and said scheduler marks said number of clock cycles in an entry of the reservation station that needs said result as an operand.
- 4. The computer processor of claim 3 wherein said execution unit indicates said number of clock cycles until availability to receive said additional instruction by sending a signal over a control bus.
- 5. The processor of claim 1 wherein said number of clock cycles is equal to two.
- 6. The processor of claim 1 wherein said execution unit indicates said number of clock cycles required to complete execution of said first instruction a number of clock cycles prior to actual completion of execution of said first instruction.
- 7. The processor of claim 1 wherein said execution unit comprises a plurality of pipeline stages, said execution resource specifying said number of clock cycles based on one of said pipeline stages in which said first instruction is executing.
- 8. The processor of claim 1 further comprising a result buffer, said first execution unit transferring said first execution result to said result buffer.
Parent Case Info
This is a divisional of application Ser. No 08/634,692, filed Apr. 18, 1996, which is a divisional of application Ser. No. 08/293,388, filed Aug. 19, 1994, now U.S. Pat. No. 5,555,432 Now issued.
US Referenced Citations (2)
Number |
Name |
Date |
Kind |
5428811 |
Hinton et al. |
Jun 1995 |
|
5555432 |
Hinton et al. |
Sep 1996 |
|
Foreign Referenced Citations (1)
Number |
Date |
Country |
9301546 |
Jan 1993 |
WOX |
Non-Patent Literature Citations (1)
Entry |
Hinton; "80960 --Next Generation" pp. 13-17; IEEE; 1989. |
Divisions (2)
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Number |
Date |
Country |
Parent |
634692 |
Apr 1996 |
|
Parent |
293388 |
Aug 1994 |
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