Patent Application
20060214709
This application claims priority under 35 USC §119 to German Application No. DE 10 2005 011 894.1 filed on Mar. 15, 2005, and titled “Circuit Arrangement for Generating a Synchronization Signal,” the entire contents of which are hereby incorporated by reference.
The present invention relates to a circuit arrangement for generating a synchronization signal.
Complex electrical circuits or parts of them (for example integrated circuits) having a large number of circuit blocks are frequently electrically connected to other complex electrical circuits when used together. In this case, the different complex electrical circuits are often situated on different semiconductor chips or other substrates (for example printed circuit boards). Integrated semiconductor memory circuits in integrated semiconductor memory chips or on appropriate modules may be used as one example of these. On the one hand, these different complex circuits as well as their circuit blocks operate relatively independently of one another, for example, at a different speed (owing to temperature fluctuations and unavoidable tolerance fluctuations in specific electrical parameters during production processes) and asynchronously. On the other hand, the different complex circuits and circuit blocks must communicate electrically with one another, to which the desired (overall) success of an arrangement of such complex circuits and circuit blocks is also geared. This is generally achieved using external clock signals which are supplied to the individual complex circuits and circuit blocks. For example, the task of these external clock signals is to synchronize those electrical signals which are produced in an individual complex circuit (such as a semiconductor circuit) or in an individual circuit block (such as a memory cell array together with read/write amplifiers) with the external clock signal, so that comparable electrical signals from different complex circuits and circuit blocks have a fixed time relationship to one another.
Electrical signals from different complex circuits and circuit blocks are frequently matched to one another, in terms of time, using synchronization signals which are derived from clock signals. In the past, a signal edge change (for example positive=rising edge change of an electrical signal) of the clock signal within a signal period was usually referred to in this case, which edge change then triggers the intended circuit functions when it occurs. In the meantime, however, particularly under the constant pressure to increase the operating speed of electrical circuits, technical progress has advanced to such an extent that the above-described synchronization operations are frequently no longer carried out upon just one of the two edge changes experienced by a synchronization signal within a signal period but rather upon both edge changes, i.e. both on a rising edge of the relevant electrical signal and on a falling edge. Dynamic semiconductor memories (=DRAM) of the DDR type (DDR-DRAM, DDR=Double Data Rate) may be used as one example of this. Both edge changes of the clock signal are used to generate such synchronization signals.
If, then, in the case of synchronization signals, i.e. in the case of signals which are intended to synchronize other electrical signals from a complex circuit or a circuit block with a system clock for a system comprising a plurality of complex circuits or circuit blocks, the rising and falling edges of the two edge changes which occur within a signal period are relatively close to one another (i.e. the so-called duty ratio differs considerably from 50%, with the duty ratio specifying the [for example percentage] proportion of time taken up by one of the two signal levels of the [digital] signal within the signal period) within a signal period (for example on account of changes which the signal has made on its way through a complex circuit), it is difficult to carry out the abovementioned synchronization operation; and it is all the more difficult, the shorter the signal period. The reason for this difficulty is that the interval of time between the two edge changes (which rapidly follow one another) in a signal period is so short that it is scarcely possible to carry out synchronization anymore.
Furthermore, it has also proved to be disadvantageous to use both edge changes of the clock signal to generate a synchronization signal. This is because, if the two edge changes of the clock signal have interference, for example jitter or superimposed interference signal spikes, the interference of both edge changes has an effect on the synchronization signal.
The present invention provides a circuit arrangement which converts a given signal to a synchronization signal having a phase shift that is as exact as possible with respect to the given signal.
In accordance with the present invention, a circuit arrangement is provided for generating at least one synchronization signal having defined signal edge changes. The circuit arrangement comprises a plurality of at least two controllable signal delay arrangements, with each controllable signal delay arrangement including a circuit part with variable signal delay and a circuit part with constant signal delay, and with an input signal being supplied to the first controllable signal delay arrangement. The circuit arrangement further comprises a phase detection device including two inputs and one output, a control circuit to control the circuit parts with variable signal delay, with the input of the control circuit being connected to the output of the phase detection device and the output of the control circuit being connected to control inputs of the circuit parts with variable signal delay. The input signal is also supplied to the first input of the phase detection device, one output of one of the controllable signal delay arrangements is connected to the second input of the phase detection device, and the output signal from one of the circuit parts with variable signal delay is used as a first synchronization signal.
The above and still further features and advantages of the present invention will become apparent upon consideration of the following detailed description of specific embodiments thereof, particularly when taken in conjunction with the accompanying drawings wherein like reference designations in the various figures are utilized to designate like components.
The variable signal delay in the circuit parts DLYv with variable signal delay is controlled by the phase detection device Φdetect and the control circuit CTRL as follows: When the input signal CLK is applied to the entire circuit arrangement, this input signal CLK is applied to the first input B of the phase detection device Φdetect and to the input of the first controllable signal delay arrangement DLY1. If the input signal CLK then undergoes an edge change of a predetermined type as it progresses further (it is assumed, for the explanation below, that this edge change is a positive edge change), the occurrence of this edge change is also supplied, in the form of a signal, to the first input B of the phase detection device Φdetect and is applied to the latter. Irrespective of this, the input signal CLK is simultaneously delayed using the chain of controllable signal delay arrangements DLY1, DLYn and is then supplied, in a manner such that it is delayed relative to the input signal CLK, to the second input A of the phase detection device Φdetect.
This delay gives rise to a phase shift between the signals which are supplied to the two inputs A and B of the phase detection device Φdetect (for example a phase shift between the rising edges of these two signals; the same respectively applies, by analogy, to falling edges in this case and in the text below, with, however, those skilled in the art having to decide, when designing the respective circuit, between those circuits which are designed to evaluate rising edges and those circuits which are designed to evaluate falling edges). This phase shift results from a comparison of the signal which has been delayed and is applied to the second input A with the next edge change of the same type (in this case: a rising edge change) that occurs in the input signal CLK at the first input B of the phase detection device Φdetect. The phase detection device Φdetect detects this phase shift and signals the detection result to the control circuit CTRL which uses the latter to generate the control signal ΦCTRL. The control signal ΦCTRL is supplied, via the output of the control circuit CTRL, to the control inputs CTRL-In of the circuit parts DLYv with variable signal delay in the controllable signal delay arrangements DLY1, DLYn.
The value of the control signal ΦCTRL determines the value of the signal delay times used in the circuit parts DLYv with variable signal delay in the controllable signal delay arrangements DLY1, DLYn. In this case, the signal delay times used in the circuit parts DLYv with variable signal delay in the controllable signal delay arrangements DLY1, DLYn are changed using the control signal ΦCTRL until the abovementioned phase shift is equal to zero.
As long as the phase shift between the two signals which are applied to the inputs A and B of the phase detection device Φdetect is such that a (an assumedly) rising edge of the signal that is applied to the second input A occurs at a time after the rising edge of the signal that is applied to the first input B, the value of the control signal ΦCTRL is changed in such a manner that the delay times which occur in the circuit parts DLYv with variable signal delay in the controllable signal delay arrangements DLY1, DLYn are reduced. If, however, the rising edge of the signal that is applied to the second input A occurs once again at a time before the rising edge of the signal that is applied to the first input B, the delay times which occur in the circuit parts DLYv with variable signal delay in the controllable signal delay arrangements DLY1, DLYn are increased.
And when (at some time) the phase shift between the signals which are applied to the two inputs A and B is equal to zero, the control signal ΦCTRL has a value that causes the effective signal delay times (which have been set up to that point) of the circuit parts DLYv with variable signal delay in the controllable signal delay arrangements DLY1, DLYn to remain constant.
The entire arrangement is thus stabilized like a DLL circuit (DLL=Delay Lock Loop) in such a manner that the chain of controllable signal delay arrangements DLY1, DLYn is used to delay the input signal CLK until there is no longer any phase shift between the signals which are applied to the inputs A and B of the phase detection device Φdetect. As soon as this situation has occurred, the control circuit is stable; the desired stable delay relationships and thus also the phase relationships for the input signal CLK are present.
In this case, the (assumedly rising) signal edge of the synchronization signal Φ1 which is applied to, and can be tapped off from, the connecting line between the circuit part DLYv with variable signal delay and the circuit part DLYc with constant signal delay in the first controllable signal delay arrangement DLY1 is delayed, with respect to the input signal CLK, by a period of time that is determined by the control signal ΦCTRL.
On the one hand, the synchronization signal is not tapped off, as the synchronization signal Φ1, from the connecting line between the circuit part DLYv with variable signal delay and the circuit part DLYc with constant signal delay in the first controllable signal delay arrangement DLY1 but rather is tapped off, as the synchronization signal Φn, from the connecting line between the circuit part DLYv with variable signal delay and the circuit part DLYc with constant signal delay in the last (in this case synonymous with: the second) controllable signal delay arrangement DLYn. Compared to the synchronization signal Φ1, this results in the signal edge (which is likewise assumed to be rising again) of the synchronization signal Φn being additionally offset, in time, by half the amount of time by which the signal that is applied to the second input A of the phase detection device Φdetect has been delayed with respect to the input signal CLK.
On the other hand, the inventive circuit arrangement shown in
In the present embodiment according to
On account of the chain (which operates as a DLL circuit) of two controllable signal delay arrangements DLY1, DLYn together with the associated phase detection device Φdetect and control circuit CTRL, the two synchronization signals Φ1, Φn which are supplied to the phase matching device Φadapt have different time offsets from one another with respect to the original input signal CLK. Every time one of the two supplied synchronization signals Φ1, Φn has one of the assumedly positive (the negative edge changes could also be used, as noted above) edge changes, which corresponds to the (assumedly) positive edge change of the input signal CLK, the output signal (which is the common synchronization signal Φ) from the phase matching device Φadapt has a positive or negative edge change. Each of these positive and negative edge changes is synchronized with the original input signal CLK and has a resultant constant phase shift with respect to these edge changes. Furthermore, in this embodiment, the interval between two successive edge changes of the common synchronization signal Φ is equal to half the period duration of the common synchronization signal Φ. The common synchronization signal Φ thus has edge changes (at equal time intervals) with a duty ratio of 50% in this exemplary embodiment. This common synchronization signal Φ makes it possible to synchronize other circuits, which need to be synchronized with the common synchronization signal Φ, at a time interval of half the period duration of the input signal CLK despite evaluating only one of the two edge changes of the input signal CLK (for example the rising edge), which is advantageous, in particular, when the inventive circuit arrangement is intended to interact with complex electrical circuits, or parts of the latter, which operate at very high speed.
The embodiment shown in
The inventive circuit arrangements shown in
A similar situation applies to the advantageous embodiment shown in
The embodiments shown in
It has been assumed, in each of the above-described embodiments, that the individual circuit parts DLYv with variable signal delay each have the same delay response as one another and that the individual circuit parts DLYc with constant signal delay likewise each have the same delay response as one another. When generating a plurality of synchronization signals Φ1, Φ2, . . . , Φn, this results in the various controllable signal delay arrangements DLY1, DLY2, . . . , DLYn respectively reacting in the same manner in terms of time and in the synchronization signals Φ1, Φ2, . . . , Φn having equidistant edge changes. However, it is also conceivable for individual circuit parts DLYv with variable signal delay (and/or individual circuit parts DLYc with constant signal delay) to have delay responses which are at least partially different from one another. The different controllable signal delay arrangements DLY1, DLY2, . . . , DLYn and, consequently, the plurality of generated synchronization signals Φ1, Φ2, . . . , Φn then no longer have equal time intervals between their edge changes but rather those which result from the differences in the delay responses of the individual circuit parts DLYv with variable signal delay (and/or the individual circuit parts DLYc with constant signal delay).
While the invention has been described in detail and with reference to specific embodiments thereof, it will be apparent to one skilled in the art that various changes and modifications can be made therein without departing from the spirit and scope thereof. Accordingly, it is intended that the present invention covers the modifications and variations of this invention provided they come within the scope of the appended claims and their equivalents.
List of Reference Symbols
Φ1, . . . , Φn Synchronization signals
Φ Common synchronization signal
CLK Input signal
DLY1, . . . , DLYn Signal delay arrangements
DLYv, DLYc Circuit part with variable time delay and circuit part with constant time delay
B, A Inputs
O Output
Φdetect Phase detection device
Φadapt Phase matching device
CTRL Control circuit
CTRL-In Control input
DRV-In, DRV-Out Input driver circuit, output driver circuit
Dly Delay block
| Number | Date | Country | Kind |
|---|---|---|---|
| 10 2005 011 894.1 | Mar 2005 | DE | national |
