Circuit element with elimination of kink effect

Abstract

A circuit element which includes a source region of a first conductance type provided with a source terminal, an intermediate region of the first conductance type separated from the source region by a first volume, a first channel region portion of a second conductance type provided with a first gate terminal and occupying the first volume, a drain region of the first conductance type provided with a drain terminal and separated from the intermediate region by a second volume, a second channel region portion of the second conductance type provided with a second gate terminal conductively connected to the first gate terminal and occupying said second volume, and an oxide layer. The first channel region portion, the intermediate region, and the second channel region portion are deposited on one face of the oxide layer. The design of the circuit element reduces adverse consequences of the so-called Kink effect, to which other circuit elements have been subject.

Description

The so-called Kink effect occurs in MOSFETs at the temperature of liquid helium (4.2 K) and also at higher temperatures in the case of SOI (Silicon on Insulator) nMOSFETs. The Kink effect is thought to occur at the saturation current I.sub.Dsat when charge carriers with a polarity opposite that of the channel are generated in the channel by ionization in the pinch-off region at the drain. When the thus generated charge carriers (holes at a nMOS channel) cannot escape due to the low temperature in the substrate or the back oxide, the effective channel resistance R.sub.L is reduced.

Thin-film SOI-MOS elements display no Kink effect but are not suitable for applications where radiation occurs, such as in space travel.

A circuit element as according to claim 1 suffers no adverse consequences from the Kink effect.

Further advantages, features and details of the present invention will become apparent in the light of the following description of a preferred embodiment with reference to a drawing, wherein:

FIG. 1 shows a schematic, sectional view of a preferred embodiment of a SOI-nMOS circuit element according to the present invention; and

FIG. 2, 3 and 4 show graphs of measurements on a structure as depicted in FIG. 1.

A structure 1 (FIG. 1) comprises a schematically designated control electrode 16 for applying a voltage V.sub.G2 behind a back oxide 2. This back oxide is preferably arranged using the SIMOX (Separation by Implantation of Oxygen) technique. SIMOX substrates or wafers are commercially available in standard form nowadays. Arranged on the back oxide 2 is an n.sup.+ -source region 3 provided with a source terminal 4 for applying the source voltage V.sub.s (for example earth potential). Further arranged on the back oxide 2 are a first p-channel region 4, an n.sup.+ -intermediate region 5 and a second p-channel region 6, wherein above the first channel region portion 4 and the second channel region portion 6 are arranged the respective oxide layers 7 and 8, wherein the respective electrodes 9 and 11 arranged above the oxide layer are commonly connected to a gate voltage V.sub.GS. Using the voltage V.sub.GS n-channels are formed in the first and second channel region portions as indicated schematically with dashed lines 12 and 13 respectively. Further arranged on the back oxide 2 is a drain region 14 provided with a terminal 15 for applying a drain voltage V.sub.DS.

The shown preferred embodiment is arranged in a SIMOX wafer with a silicon film thickness of 230 nm. First of all a 20 nm thick gate oxide is grown. Boron ions are subsequently implanted and a 400 nm thick polysilicon layer is then deposited to form the (doped) gate electrodes. Arsenic ions are implanted to form source and drain regions and the intermediate region 5. Source and drain are annealed and an oxide layer arranged to form contact holes wherein titanium tungsten (TiW) and aluminium silicon (AlSi) alloys are used to form the conductor paths.

In the graph of FIG. 2 (drain current (I.sub.DS) as a function of the voltage between drain and source (V.sub.DS)) the curves a, b, c, d, e are measured at room temperature (300 K) and at the value for the voltage V.sub.VS of 1.0 V (volt), 1.5 V; 2.0 V; 2.5 V; and 3.0 V respectively and a V.sub.G2 of -10 V on a "normal" SOI-MOS transistor with a width-length ratio (W/L) of 50/2. It can clearly be seen that the Kink effect occurs in the curves in the region of V.sub.DS between 2.0 and 3.0 V. The curves a', b', c', d' represent curves measured with a structure of FIG. 2 at the same value for V.sub.GS wherein the width-length ratio of the first channel region portion 4 amounts to W/L=50/2 and that of the second channel region portion 50/1. It can be seen clearly that the Kink effect has been eliminated.

FIG. 3 is measured at the temperature of liquid helium (4.2 K). The broken lines f, g, h, i and j indicate the measured curves in the case of a SOI-MOS FET (W/L=50/2) at a gate source voltage V.sub.GS of respectively 1.5 V; 2.0 V; 2.5 V; 3.0 V and 3.5 V and a V.sub.G2 of -10 V. The Kink effect is once again clearly observable. The full lines f', g', h', i', j' display no Kink effect and are measured on a structure as depicted in FIG. 1 wherein once again the width-length ratio of the first channel region portion amounts to 50/2 and that of the second channel region portion 50/1.

The curves shown in FIG. 4 were measured at room temperature (300 K), V.sub.GS 3.0 V, V.sub.GT -10 V. The full line e is likewise from FIG. 2, while the broken line k relates to a MOS-SOI transistor with W/L=50/1.

Line e' is already shown in FIG. 2, while line 1 is measured on the structure of FIG. 2, wherein source and drain are exchanged, that is, first a channel region portion with W/L=50/1 and behind this a channel region portion with W/L=50/2.

It is thought that the good results are obtained because the Kink effect at pinch-off is limited to the second channel region portion (indicated in FIG. 1 with an arrow and positive charge carriers) while the output characteristic is determined by the first channel region portion 4.

In order to verify the above a simulation was performed using ELDQ as described in B. Hennion, P. Senn: "ELDO: A New Third Generation Circuit Simulator using the On Step Relaxation Method", Proc. ISCAS, pp.1065-1068.

The results (not shown) of this simulation represent a sufficient verification of above stated theory of the operation of the circuit element according to the shown and described preferred embodiment of the present invention.

In order to elucidate the present invention a voltage V.sub.G2 of -10 V was applied to the back gate; the present invention is however equally applicable at other values for V.sub.G2, for instance V.sub.G2 =0.

Claims

1. A circuit element comprising:

a source region of a first conductance type, provided with a source terminal;

an intermediate region of the first conductance type, separated from the source region by a first volume;

a first channel region portion of a second conductance type opposed to the first conductance type, provided with a first gate terminal, and occupying the first volume;

a drain region of the first conductance type provided with a drain terminal, and separated from the intermediate region by a second volume;

a second channel region portion of the second conductance type provided with a second gate terminal conductively connected to the first gate terminal, and occupying said second volume; and

an oxide layer having a first face, wherein the first channel region portion, the intermediate region, and the second channel region portion, are deposited on the first face of the oxide layer.

2. A circuit element as claimed in claim 1, wherein the second channel region portion has a channel length greater than that of the first channel region portion.

3. A circuit element as claimed in claim 1, wherein the width-to-length ration, W/L, of the first channel region portion is substantially equal to 50/2 and that of the second channel region portion is substantially equal to 50/1.

4. The circuit element of claim 1, wherein the oxide layer has a second face opposite the first face, and also including a control terminal connected to the second face of the oxide layer.

5. A circuit element as claimed in claim 1, wherein each of the first channel region portion and the second channel region portion comprises an n-channel.

6. The circuit element of claim 5, wherein the second channel region portion has a channel length greater than that of the first channel region portion.