This invention relates to (nonvolatile) memory devices, and, more particularly, to a circuit that generates an internal enabling signal of an output buffer of a memory device when external commands for enabling the memory and outputting data are provided.
(Nonvolatile) Memory devices include output buffers of the type exemplified in
When the memory is enabled, an output buffer transfers data from a line of the bus DBUS to the line of the bus DQ_PAD when a respective external enabling command OEN_PAD switches to the null logic value. Other circuits of the memory, not shown, send through the bus DBUS data read from the memory. This data is made available on the lines DQ_PAD after a time tELQV, for instance of 60 ns, from the instant in which the memory has been enabled.
An output buffer transfers on the line DQ_PAD a signal present on the internal bus DBUS after a time tELQX shorter than the time tELQV. In a buffer of
It is evident that a line DQ_PAD is needlessly occupied for a relatively long time with data that does not correspond to the data read from the memory because this is not yet available on the internal bus DBUS. It would be desirable to increase the time tELQX to make it close to the time tELQV such that the line DQ_PAD is occupied only when a stable signal, corresponding to the read data, is present on the internal bus DBUS. This would reduce power consumption and noise on the line DQ_PAD and would free it for other uses.
For instance, a device for writing in the memory and a device for reading from the memory could use the same line DQ_PAD in a time-sharing mode. It would be possible to exploit the waiting time for a reading operation as a “hold-time” of a writing operation, with evident advantages in terms of reduced hardware complexity and optimization of the read/write phases.
The invention relates to a circuit for generating an internal enabling signal of an output buffer of a memory that meets the above mentioned objective. It includes a logic circuit that generates the internal enabling signal when the memory is turned on and enabled for generating output data through appropriate external commands, and when the read operation of the data from the memory ends. To attain this objective, the logic circuit processes the internal flags that signal when a read operation is in progress and when it ends, generally available in any such memory device for switching on the internal enabling signal such that the output buffer is enabled as soon as the read operation ends.
The invention will be described referring to the attached drawings, wherein:
a and 1b show an output buffer of a memory and a circuit for generating an internal enabling signal, respectively, as in the prior art;
A first embodiment of the circuit of the invention is shown in
When the external commands CEN_PAD and OEN_PAD switch low, the signal OE_N is low but the internal enabling signal OEN does not yet switch low. As a consequence, the output buffer remains disabled even if the external commands enable the memory and the generation of output data as long as an intermediate signal Q assumes a logic low value.
This intermediate signal Q is generated by the latch LD1 as a replica of its input D when a high logic signal is fed to the input G. This takes place either when: a read operation of data from the memory is terminated, that is when the signal END_READ is high, or the internal registers of the memory are being read, that is when the signal READ_N is high.
The latter operation is much faster than a normal reading of data from the memory array (it lasts only a few ns, while reading a memory array cell takes normally about 50 ns). Thus, even if the signal OEN switches low before a reading operation of these registers ends, the output buffer does not hold the line DQ_PAD because of switching delays of the MOS transistors that compose it, before the signal on the bus DBUS becomes stable. With these expedients, the internal signal OEN enables the output buffer when the read operation from the memory is terminated, thus the line DQ_PAD is occupied only when the signal present on the bus DBUS is stable and corresponds to read data.
As an option, the state of the signal OEN may be conditioned even by a TEST flag, that signals when the memory device is in test mode, such as to enable the output buffer when a memory test is in progress.
A detailed circuit scheme of the latch LD1 is shown in
An alternative embodiment of the circuit of this invention is shown in
The diagram of
Number | Date | Country | Kind |
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VA2005A0002 | Jan 2005 | IT | national |
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4882507 | Tatsumi et al. | Nov 1989 | A |
5303191 | Eagan et al. | Apr 1994 | A |
7079445 | Choi et al. | Jul 2006 | B2 |
Number | Date | Country | |
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20060181311 A1 | Aug 2006 | US |