Patent Grant
8339195
The present disclosure relates to circuits and methods for offset calibration in amplifier circuits.
Unless otherwise indicated herein, the approaches described in this section are not prior art to the claims in this application and are not admitted to be prior art by inclusion in this section.
Amplifier circuits are basic building blocks of many electronic systems. Amplifier circuits (or “amplifiers”) are used to increase a particular characteristic of a signal, such as voltage, current, or power, for example. Amplifiers typically have offset. For example, when an amplifier input is zero, ideally the output should also be zero. However, due to the internal construction limitations of most amplifiers, when the input of an amplifier is zero, the amplifier will typically generate a non-zero output. This non-ideality is referred to as the offset of the amplifier.
Particular embodiments described below reduce offset in amplifiers.
Embodiments of the present disclosure include amplifier circuits with reduced offsets. In one embodiment, the present invention includes a circuit comprising an amplifier having an input and an output, an offset detection circuit configured to detect an offset of the amplifier at the output of the amplifier, and an offset generation circuit having an input coupled to the offset detection circuit and an output coupled to the input of the amplifier configured to generate an offset at the input of the amplifier during an operational phase of the amplifier based on the detected offset. The generated offset is configured to cancel a least a portion of the offset of the amplifier.
In one embodiment, the offset detection circuit is configured to detect offset at the output of the amplifier during a calibration phase to generate the offset at the input of the amplifier and the offset at the input of the amplifier is maintained during the operational phase.
In one embodiment, the offset generation circuit produces a current into the input of the amplifier to cancel at least a portion of the offset of the amplifier.
In one embodiment, the amplifier comprises a second input, and the offset generation circuit generates the first offset into the first amplifier input when the detected offset at the output of the amplifier has a first polarity and the offset generation circuit generates a second offset into the second amplifier input when the detected offset at the output of the amplifier has a second polarity.
In one embodiment, the offset generation circuit receives a digital signal to generate a particular offset value at the input of the amplifier, and the digital signal is changed to produce a plurality of offset values to reduce the offset of the amplifier.
In one embodiment, the amplifier is a sense amplifier in a memory. The sense amplifier comprises a first input coupled to a first output of a memory cell and a second input coupled to a second output of the memory cell. The offset generation circuit comprises a first current generator coupled to the first input of the sense amplifier and a second current generator coupled to the second input of the sense amplifier.
In one embodiment, a plurality of the sense amplifiers are calibrated simultaneously in response to a single control signal.
In one embodiment, the present invention includes a method comprising detecting a first offset of an amplifier at an output of the amplifier and generating, during an operational phase of the amplifier, a second offset at an input of the amplifier based on the first offset, where the second offset cancels a least a portion of the first offset of the amplifier.
In one embodiment, detecting the first offset is performed during a calibration phase to generate the second offset at the input of the amplifier, and the second offset at the input of the amplifier is maintained during the operational phase.
In one embodiment, the amplifier comprises a second input, and generating the second offset comprises generating the second offset into the first amplifier input when the first offset at the output of the amplifier has a first polarity and generating the second offset into the second amplifier input when the first offset at the output of the amplifier has a second polarity.
In one embodiment, the method further includes receiving, by an offset generation circuit, a digital signal to generate a particular second offset value at the input of the amplifier, where the digital signal is changed to produce a plurality of second offset values to reduce the first offset of the amplifier.
In one embodiment, the amplifier is a sense amplifier in a memory. The input of the amplifier is a first input coupled to a first output of a memory cell and the sense amplifier comprises a second input coupled to a second output of the memory cell, where generating the second offset comprises generating a first current to the first input of the sense amplifier when the first offset at the output of the amplifier has a first polarity and generating a second current to the second input of the sense amplifier when the first offset at the output of the amplifier has a second polarity.
The following detailed description and accompanying drawings provide a better understanding of the nature and advantages of the present invention.
Described herein are techniques for reducing offset in amplifiers. In the following description, for purposes of explanation, numerous examples and specific details are set forth in order to provide a thorough understanding of particular embodiments. The circuits and methods disclosed herein may be used in a variety of electronic systems. Further, the circuits and methods describe herein may be implemented on an integrated circuit (IC). Particular embodiments as defined by the claims may include some or all of the features in these examples alone or in combination with other features described below, and may further include modifications and equivalents of the features and concepts described herein.
In one embodiment, amplifier 101 operates in a calibration phase and an operational phase. During the calibration phase, the input of amplifier 101 may be set to a particular value (e.g., ground) and offset detection circuit 102 detects the offset at the output of amplifier 101. In response to the detected offset, offset generation circuit 103 generates an offset at the input of amplifier 101 to cancel the offset of amplifier 101. During the operational phase, offset generation circuit 103 maintains the offset at the input of amplifier 101 to cancel the detected offset of amplifier 101. Accordingly, previous stage 104 may generate input signals to amplifier 101 during the operational phase, and the input signals will be amplified with reduced offset.
In a particular embodiment, offset generation circuit 103 produces a current into the input of amplifier 101 to cancel at least a portion of the offset of the amplifier. For example, the input of amplifier 101 may have an associated capacitance, C. Offset generation circuit 103 may produce a current into capacitance, C, over a particular time period to produce a change in voltage that cancels out an offset voltage of amplifier 101 according to the following equation: Ios*t/C=ΔV, where Ios is the current generated at the input of amplifier 101 by offset generation circuit 103, t is the time period, and ΔV is the generated offset at the input that cancels the amplifier offset.
In another particular embodiment, offset generation circuit 103 receives a digital signal to generate a particular offset value at the input of amplifier 101 and the digital signal is changed to produce a plurality of offset values to reduce offset of amplifier 101. For example, offset detection circuit 102 may generate digital signals in response to detecting offset at the output of amplifier 102. The digital signals may be a single digital bit indicating that a voltage on the output of amplifier 101 is above or below a particular value, or the digital signals may be multiple digital bits specifying the value of the voltage on the output of amplifier 101, for example. Offset generation circuit 103 may receive the digital signals and generate an offset voltage to cancel the offset of the amplifier. For example, if offset detection circuit 102 detects that the voltage on the output of amplifier 101 is above zero volts, then offset generation circuit 103 may generate −100 mV of offset. Offset detection circuit 102 may detect offset at the output of amplifier 101 again. If the voltage on the output of amplifier 101 is still above zero volts, then the offset of the amplifier is greater than 100 mV and more canceling offset may be generated. However, if the voltage on the output of amplifier 101 is now below zero volts, then the offset of the amplifier is less than 100 mV and less cancelling offset may be generated. A more detailed algorithm for detecting and reducing amplifier offset according to one embodiment is provided below.
In this example, offset detection circuit 210 has an input coupled to the first output of amplifier 201 to detect offset of amplifier 201. An output of offset detection circuit 210 is coupled to control circuit 211, and control circuit 211 generates digital signals in response to the detected offset. An output of control circuit 211 is coupled to offset generation circuit 213 to configure offset generation circuit 213 to generate an offset at the first input of amplifier 201. Similarly, offset detection circuit 220 has an input coupled to the second output of amplifier 201 to detect offset of amplifier 201. An output of offset detection circuit 220 is coupled to control circuit 221, and control circuit 221 generates digital signals in response to the detected offset. An output of control circuit 221 is coupled to offset generation circuit 223 to configure offset generation circuit 223 to generate an offset at the second input of amplifier 201. Offset may be detected and an input offset that cancels the offset of the amplifier (e.g., a cancelling offset) may be determined during the calibration phase mentioned above. At the end of the calibration phase, digital values may be stored in either or both of offset value storage blocks 212 or 222. Accordingly, during an operational phase, values stored in one or both of the offset value storage blocks 212 or 222 may be accessed to generate a cancelling offset at the input of amplifier 201.
While a variety of algorithms may be used to determine an optimum offset to generate to reduce the offset of amplifier 201, in one embodiment a successive approximation may be used. For instance, control signals received by control circuit 211 and control circuit 221 may cause the circuit to perform successive approximation to determine an offset to reduce the offset of amplifier 201. The successive approximation may be performed during a calibration phase that occurs before or between operational phases of amplifier 201, for example.
If the positive output of the amplifier is high when a negative offset is injected into the positive input, then such a condition indicates that the offset of the amplifier is greater than the injected offset. Accordingly, to further cancel the amplifier offset, the injected offset is increased to the next increment at 307 (e.g., −100 mV). For example, if the injected offset is represented by the variable X and the increment is represented by the variable Dn, then Xn=Xo+Dn, where Xn is the “nth” increment and Xo is the previous value. At 308, the new offset is injected into the positive input. If the positive output is still high (Vout+=H) at 309, then the process returns to 307 for further increments. If the positive output goes low (Vout+=L) at 309, then the final offset is stored at 310 (e.g., in offset value storage 212 of
If the positive output is low (Vout+=L) at 305, then such a condition indicates the amplifier may have a negative offset. Accordingly, the processes repeated for the negative input of the amplifier as illustrated by the steps shown at 312. In this case, a negative offset is injected into the negative input at 313, and the condition on the detected output at 315 is high (Vout−=H?). For example, if a negative offset is injected by offset generation circuit 223 in
After calibration, an offset corresponding to the value stored during the calibration phase may be injected into the input signal path during an operational phase. For example, during an operational phase, switches 215 and 225 are closed and an input signal may be received on the inputs of amplifier 201. If the “offset injection needed” flag is set during calibration phase, then offset will be generated. For example, if the positive “offset injection needed” flag was set, then offset is generated by offset generation circuit 213 into the positive input of amplifier 201 based on the value stored in offset value storage 212. Similarly, if the negative “offset injection needed” flag was set, then offset is generated by offset generation circuit 223 into the positive input of amplifier 201 based on the value stored in offset value storage 222. Accordingly, either no offset will be injected (neither flag set) or offset will be injected to the positive or negative inputs of amplifier 201 depending on the values of the positive and negative flags. The flags may be stored in flip flops or registers in control circuits 211 or 221, for example
In this example, offset generation circuits 422 and 423 generate currents i1 and i2, respectively. Current i1 from offset generation circuit 422 may be selectively coupled through transistor 424 to the positive input of amplifier 405 during a read operation to reduce the offset of amplifier 405. Similarly, current i2 from offset generation circuit 423 may be selectively coupled through transistor 425 to the negative input of amplifier 405 during a read operation to reduce the offset of amplifier 405. Offset in amplifier 405 may be canceled by iteratively generating offsets into the positive or negative inputs of amplifier 405, or both, as described above during a calibration phase or using another offset calibration algorithm. The generated offset is opposite in polarity to the offset of the amplifier so that the effects of the amplifier offset are reduced or canceled completely. A final offset may be stored in a register for use during an operational phase, for example.
During the operational phase, such as a read operation, word line 404 is activated to turn on transistors 412 and 413. A data bit stored on inverters 410 and 411 as a voltage is coupled to the inputs of amplifier 405. Inverter 410 sources or sinks current into the positive input of amplifier 405. If offset generation circuit 422 is configured to generate an offset into the positive input of amplifier 405, based on the result of the calibration phase, then current i1 is combined with current from inverter 410, where current i1 reduces the offset of amplifier 405. Similarly, inverter 411 sources or sinks current into the negative input of amplifier 405. If offset generation circuit 423 is configured to generate an offset into the negative input of amplifier 405, based on the result of the calibration phase, then current i2 is combined with current from inverter 411, where current i2 reduces the offset of amplifier 405. In some memory applications, a plurality of the sense amplifiers are calibrated simultaneously in response to a single control signal. For instance, offset in multiple sense amplifiers 405 may be calibrated and/or corrected during an operational phaset using one control signal. The control signal may be coupled to multiple sense amplifiers to activate the sense amplifiers in banks, for example.
One advantage of the example implementation in
Particular embodiments of the present invention may be used to implement offset adjustment in sense amplifiers using a small number of transistors (e.g., 100's or 1000's per chip). This may be advantageous in high density memory applications having a large number of sense amplifiers, for example. In one embodiment, the output of sense amplifier 405 is coupled to two latches: one for storing a condition where the offset is greater than a first value (e.g., 100 mV) and another for storing a condition where the offset is less than a first value (e.g., −100 mV). In one particular embodiment, offset generations circuits 422 and 423 are configured to generate predetermined offset voltages (e.g., +/−200 mV) for amplifier 405. Opposite polarity offset is applied during the operational phase at the input of amplifier 405 if one of the latches is set during calibration, indicating that the output of the amplifier 405 was either above or below a predefined threshold value. Accordingly, offset detection circuit 420 may comprise two latches, for example, for capturing the above two conditions.
For example, in one embodiment, during calibration WL 404 may be low to disconnect memory cell 401, transistors 450 and 451 may be turned on, and the inputs of sense amplifier 405 may be precharged to Vdd using transistors 460-461 (i.e., PRECHG=0V). Next, transistors 460 and 461 are turned off and the positive input of sense amplifier 405 may be driven by a current pulse from offset generation circuit 422 by turning on transistor 424 for a time period corresponding to the amount of offset to be injected. For example, a current pulse may be configured to last a time period sufficient to produce a 100 mV offset. After the offset has been injected, the output of amplifier 405 may be monitored. For example, if 100 mV of negative offset is applied to the positive input, it would be expected that the output is negative. However, if the output remains positive, then the offset is greater than 100 mV. As mentioned above, offset detection circuit 420 may include a latch that is triggered if the output of amplifier 450 is positive. Thus, the latch may store a flag that indicates that a negative offset is to be generated during an operational phase. Accordingly, during an operational phase, when memory cell 401 is activated by word line 404, a negative offset (e.g., 200 mV) may be injected simultaneously into the positive input of amplifier 405 to cancel the offset voltage of amplifier 405. The negative (or canceling) offset injected during operational phase may be up to two times (2×) the offset used during the calibration phase for detecting offset, for example. Increasing the injected offset up to 2× the offset used during calibration phase may further improve the overall distribution of the sense amplifier offsets in memory circuit such that speed, yield, or power is improved. In this embodiment, storage of final offset voltage of sense amplifiers is not required and the amount of circuitry and calibration time is minimized. Accordingly, in some embodiments, steps 307-310 and 317-320 may be omitted.
One advantage of the above example is that the mechanism for detecting offset is the same as the mechanism for canceling offset, which reduces the number of transistors required to implement the circuit and reduces mismatch errors, for example. It is to be understood that a similar technique may be employed for detecting negative offsets. For example, if the output of amplifier 405 goes negative in response to negative offset injection by offset generation circuit 422 as mentioned above, then another offset may be injected by offset generation circuit 423 during calibration phase. In this case, a second latch in offset detection circuit 420 may be triggered if the output of amplifier 405 is negative. Accordingly, the calibration phase may include both positive and negative offset injection testing described above, and cancelling offset may be injected into either the positive or negative inputs of amplifier 405 as required during the operational phase (e.g., during a read operation).
The above description illustrates various embodiments of the present invention along with examples of how aspects of the present invention may be implemented. The above examples and embodiments should not be deemed to be the only embodiments, and are presented to illustrate the flexibility and advantages of the present invention as defined by the following claims. For example, while the some of the above embodiments have been disclosed using PMOS and NMOS, other embodiments may use other types of transistors. As a further example, one or more steps of methods or processes discussed above may be performed in a different order (or concurrently) and still achieve desirable results. Based on the above disclosure and the following claims, other arrangements, embodiments, implementations and equivalents may be employed without departing from the scope of the invention as defined by the claims.
The present disclosure claims the benefit of priority from U.S. Provisional Application No. 61/285,484, filed Dec. 10, 2009, the disclosure of which is incorporated herein by reference in its entirety.
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