Clock and data recovery circuit

Abstract

Disclosed is a clock and data recovery circuit which includes a four-phase generation circuit that generates four-phase clock signals with phases thereof being equally spaced by 90 degrees, a first interpolator and a second interpolator, each of which receives two of the clocks with phases thereof separated to each other by 180 degrees, performs phase interpolation, and outputs a signal obtained by the interpolation and a signal with a phase reverse to a phase of the interpolated signal, and a four-phase to eight-phase conversion circuit that receives the four-phase clocks from the first and second interpolators, buffers the four-phase clock signals output from the first interpolator and the second interpolator and outputs the buffered four-phase clock signals without alteration, and generates four-phase clocks each obtained by interpolation of two of the clock signals with the mutually adjacent phases among the four-phase clock signals output from the first interpolator and the second interpolator. A set of the four-phase clocks among the eight-phase clocks output from the four-phase to eight-phase conversion circuit are used for data detection of received serial data with even and odd data multiplexed therein, for transfer. A remaining set of the four-phase clocks are used for edge detection.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a diagram showing a configuration of an example of the present invention;

FIG. 2 is a timing waveform diagram showing an example of an operation of the example of the present invention;

FIG. 3 is a diagram showing an example of a configuration of a four-phase to eight-phase conversion circuit in FIG. 1;

FIG. 4 is a diagram showing an example of a configuration of a timing difference division circuit in FIG. 3;

FIG. 5 is a diagram showing an example of a typical configuration of a conventional clock and data recovery circuit;

FIG. 6 is a timing waveform diagram showing an example of an operation in FIG. 5; and

FIG. 7 is a diagram showing an example of an interpolator.

Claims

1. A clock and data recovery circuit comprising: a plurality of interpolators, each of which receives two input clock signals and generates a clock signal with a phase obtained by interpolating a phase difference between the two input clock signals; a plurality of clock signals from said interpolators constituting a first set of clock signals; anda conversion circuit which receives the first set of clock signals from said interpolators and generates a second set of clock signals obtained by dividing mutually adjacent phases of the first set of clock signals;said first set of clock signals being used for one of input data detection and edge detection, and said second set of clock signals being used for the other of the input data detection and the edge detection.

2. A clock and data recovery circuit comprising: a circuit which generates 2N-phase clock signals with phases thereof being equally spaced by 180/N degrees;N interpolators, each of which receives from among the 2N-phase clock signals two of the clock signals with phases thereof separated by 360/N degrees, performs phase interpolation, and generates a signal obtained by the interpolation and a signal having a phase reverse to a phase of the signal obtained by the interpolation;said N interpolators providing 2N-phase clock signals with phases thereof interpolated; anda 2N-phase to 4N-phase conversion circuit which buffers the 2N-phase clock signals from said N interpolators and delivers the buffered 2N-phase clock signals without alteration, and generates 2N-phase clock signals each having a phase intermediate between the mutually adjacent phases of two of the 2N-phase clock signals from said N interpolators, thereby providing a total of 4N-phase clock signals;a set of the 2N-phase clock signals among the 4N-phase signals from said 2N-phase 4N-phase conversion circuit being used for input data detection and the remaining 2N-phase clock signals being used for edge detection.

3. The clock and data recovery circuit according to claim 2, wherein the set of the 2N-phase clock signals is used for the data detection of serial data in which even and odd data have been multiplexed, and the other 2N-phase clock signals are used for the edge detection.

4. A clock and data recovery circuit comprising: a four-phase clock generation circuit which generates clock signals of four phases equally spaced by 90 degrees;a first interpolator which receives the clock signals with first and third phases of the four phases, performs phase interpolation, and generates a signal obtained by the interpolation and a signal with a phase reverse to a phase of the signal obtained by the interpolation;a second interpolator which receives the clock signals with second and fourth phases of the four phases, performs phase interpolation, and generates a signal obtained by the interpolation and a signal with a phase reverse to a phase of the signal obtained by the interpolation; anda four phase-to eight-phase conversion circuit which receives the four-phase clock signals from said first and second interpolators, buffers the four-phase clock signals from said first and second interpolators and delivers the buffered four-phase clock signals without alteration, and generates four-phase clock signals obtained by interpolating two of the clock signals having the mutually adjacent phases among the four-phase clock signals output from said first and second interpolators, thereby providing eight-phase clock signals;a set of the four-phase clock signals among the eight-phase clock signals from said four-phase to eight-phase conversion circuit being used for data detection of serial data and the remaining four-phase clock signals being used for edge detection of the serial data, the serial data having even data and odd data multiplexed therein, for transfer.

5. The clock and data recovery circuit according to claim 4, comprising: a control circuit which controls each of phase interpolating amounts of said first and second interpolators separately;duty ratio correction being separately carried out in response to respective changes in duty ratios of the even data and the odd data.

6. The clock and data recovery circuit according to claim 4, wherein said four-phase to eight-phase conversion circuit comprises: first through fourth buffer circuits which buffer the four-phase clock signals from said first and second interpolators and output the buffered four-phase clock signals without alteration, respectively; andfirst through fourth timing division circuits which generate the clock signals each obtained by equally dividing a timing difference between the two clock signals having the mutually adjacent phases among the four-phase clock signals from said first and second interpolators.

7. The clock and data recovery circuit according to claim 6, wherein said first through fourth buffer circuits which buffer and output the four-phase clock signals from said first and second interpolators without alteration, respectively, comprise fifth through eighth timing division circuits, respectively, said fifth through eighth timing division circuits receiving the four-phase clock signals from said first and second interpolator, respectively, at respective two input terminals thereof in common.

8. The clock and data recovery circuit according to claim 4, further comprising: a first selector which receives from among the four-phase clock signals from said four-phase clock generation circuit the clock signals with the first phase and the third phase, and selects one of the clock signals with the first phase and the third phase based on a first selection signal, for supply to a first input of said first interpolator;a second selector which receives from among the four-phase clock signals the clock signals with the second phase and the fourth phase, and selects one of the clock signals with the second phase and the four phase based on a second selection signal, for supply to a second input of said first interpolator;a third selector which receives from among the four-phase clock signals from said four-phase clock generation circuit the clock signals with the first phase and the third phase, and selects one of the clock signals with the first phase and the third phase based on the first selection signal, for supply to a first input of said second interpolator; anda fourth selector which receives from among the four-phase clock signals from said four-phase clock generation circuit the clock signals with the second phase and the fourth phase, and selects one of the clock signals with the second phase and the fourth phase based on the second selection signal, for supply to a second input of said second interpolator.

9. The clock and data recovery circuit according to claim 8, further comprising: first through eighth latches which latch the serial data responsive to the eight-phase clock signals from said four phase-to eight-phase conversion circuit, respectively;a digital filter which receives latched results of the first through eighth latches and outputs an up or down signal based on a result of filter processing of the latched results;a control circuit which receives the up or down signal from the digital filter and generates said first and second selection signals and generates first and second control signals for controlling respective phase interpolating amounts of said first and second interpolators separately.