Patent Application
20250226829
This application claims the priorities of Republic of Korea Patent Application Nos. 10-2024-0003189 filed on Jan. 8, 2024 and 10-2024-0120650 filed on Sep. 5, 2024, which are hereby incorporated by reference in their entirety.
The present disclosure relates to a clock recovery device and a display driving device including the same, and more specifically, to a clock recovery device that changes the delay time of a clock signal to the same, and a display driving device including the same.
The display device includes a panel that displays an image through a pixel matrix, a gate driver that drives gate lines of the panel, a data driver that supplies data signals to data lines of the panel, a timing controller that controls the gate driver and the data driver, etc. The data driver includes a plurality of data driving ICs (Integrated Circuits) that divide and drive the data lines.
The timing controller serializes parallel data and transmits it to a plurality of data driving ICs, and each of the plurality of data driving ICs may recover clock and data information from the transmission signal and use it.
A clock recovery unit applied to a receiving unit of a conventional display device generates a clock having a delay time equal to an embedded clock frequency.
The delay times inside the voltage-controlled delay line in the clock recovery section have constant values because the input/output capacitances are the same, but since the capacitor capacity or length of the line providing the master clock signal is different from the capacitor capacity or length inside the voltage-controlled delay line, the first delay time has an error with the second delay time.
Due to the error that occurs as described above, a certain section of the setup or hold margin is damaged during data recovery, which reduces the range of application.
Accordingly, the present disclosure is directed to a clock recovery device and a display driving device including the same that substantially obviate one or more of problems due to limitations and disadvantages described above.
More specifically, the present disclosure is to provide a clock recovery device and a display driving device including the same for preventing an error in delay time from occurring according to input/output capacitance.
Additional features and advantages of the disclosure will be set forth in the description which follows and in part will be apparent from the description, or may be learned by practice of the disclosure. Other advantages of the present disclosure will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
To achieve these and other advantages and in accordance with the present disclosure, as embodied and broadly described, a clock recovery device may include a clock generator configured to generate a master clock signal from embedded transmission data, a delay line for generating multi-level clock signals by delaying the master clock signal by a preset reference delay time unit based on an input frequency, a delay controller configured to receive two clock signals delayed by a reference delay time unit among the multi-level clock signals and detect delay time, output a selection signal based on the delay time and the reference delay time, correct the delay time of the master clock signal to the reference delay time based on the selection signal, and output the master clock signal corrected to the reference delay time to the delay line, and a data recovery module configured to recover the multi-level clock signal corrected to the reference delay time through the delay line.
The delay controller may increase the delay time by reducing a rising time of the clock signal through an inverter of a determined size when an input frequency is a low frequency.
The delay controller may include a first inverter of a large size and a second inverter of a small size, and the inverter of the determined size may be the first inverter.
The delay controller may reduce a delay time by increasing a rising time of the clock signal through an inverter of a determined size when an input frequency is a high frequency.
The delay controller may include a first inverter of a large size and a second inverter of a small size, and the inverter of the determined size may be the second inverter.
The delay line is composed of a plurality of inverters, and may generate the multi-level clock signal by passing through the plurality of inverters.
In addition, to solve the above problem, a display driving device recovering a clock signal and data from an input signal and driving a display panel using the recovered clock signal and data may include a clock recovery device including: a clock generator configured to generate a master clock signal from embedded transmission data; a delay line for generating multi-level clock signals by delaying the master clock signal by a preset reference delay time unit based on an input frequency; a delay controller configured to receive two clock signals delayed by a reference delay time unit among the multi-level clock signals and detect delay time, output a selection signal based on the delay time and the reference delay time, correct the delay time of the master clock signal to the reference delay time based on the selection signal, and output the master clock signal corrected to the reference delay time to the delay line; and a data recovery module configured to recover the multi-level clock signal corrected to the reference delay time through the delay line.
The delay control unit may compare the delay time with the reference delay time, and output the selection signal including ‘1’or ‘0’ based on the comparison result.
The delay control unit may determine a size of an inverter to output the master clock signal based on the selection signal.
In another aspect of the present disclosure, a clock recovery method may include generating a master clock signal from embedded transmission data, generating multi-level clock signals by delaying the master clock signal by a preset reference delay time unit based on an input frequency, receiving two clock signals delayed by a reference delay time unit among the multi-level clock signals, detecting the delay time, comparing the delay time with the reference delay time, outputting a selection signal based on the comparison result, and determining a size of an inverter outputting the master clock signal based on the selection signal, and recovering the multi-level clock signals whose delay time is corrected to the reference delay time by passing through an inverter of the determined size.
In the step of determining the size of the inverter, when the input frequency is a low frequency, the delay time may be increased by reduced a rising time of the clock signal through the inverter of the determined size.
In the step of determining the size of the inverter, the inverter may include a first inverter of a big size and a second inverter of a small size, and the inverter of the determined size may be the first inverter.
In the step of determining the size of the inverter, when the input frequency is a high frequency, the delay time may be reduced by increasing a rising time of the clock signal through the inverter of the determined size.
In the step of determining the size of the inverter, the inverter may include a first inverter of a big size and a second inverter of a small size, and the inverter of the determined size may be the second inverter.
The step of generating the multi-level clock signals may generate the multi-level clock signals by passing through a plurality of inverters.
The aspect may increase the frequency range in which the clock recovery device may operate by securing a setup or hold margin during data recovery.
In addition, the aspect may increase the operating range of the clock recovery device, thereby expanding the application range.
In addition, the aspect may improve the yield loss of the device.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the disclosure as claimed.
The accompanying drawings, which are included to provide a further understanding of the disclosure and are incorporated in and constitute a part of the disclosure, illustrate aspects of the disclosure and together with the description serve to explain the principle of the disclosure.
In the drawings:
Hereinafter, aspects will be described in detail with reference to the attached drawings. The aspects may have various modifications and may take various forms, and thus specific aspects will be illustrated in the drawings and described in detail in the text. However, this is not intended to limit the aspects to a specific disclosed form, and it should be understood that it includes all modifications, equivalents, or substitutes included in the spirit and technical scope of the aspects.
Terms such as “first” and “second” may be used to describe various components, but the components should not be limited by the terms. The terms are used for the purpose of distinguishing one component from another. In addition, terms specifically defined in consideration of the configuration and operation of the aspects are only for describing the aspects, and do not limit the scope of the aspects.
In the description of the aspect, when it is described as being formed “on or under” each element, “on or under” includes both the two elements being directly in contact with each other or one or more other elements being positioned indirectly between the two elements. In addition, when expressed as “on or under,” it may include the meaning of not only the upward direction but also the downward direction based on one element.
In addition, relational terms such as “upper/upper/top” and “lower/lower/below” used below may be used to distinguish one entity or element from another entity or element, without necessarily requiring or implying any physical or logical relationship or order between such entities or elements.
The receiving unit device according to the aspect may be configured to include a serial-to-parallel converter that receives transmission data (clock embedded data: CED) (hereinafter, collectively referred to as “transmission data (CED) ”) in the form of a clock signal transmitted from a timing control unit through a serial signal line, converts it into parallel data, and then transmits a recovered data signal (recovered data) to a display panel, and a clock recovery device according to the aspect that extracts an embedded clock signal from the transmission data (CED) in which the clock signal is embedded between data signals and transmits a sampling clock signal used for recovering the data signal to the serial-to-parallel converter and outputs a recovered clock signal (recovered clock) for data output.
Referring to
The timing controller 10 receives image data and timing signals from a host system (not shown), performs image processing such as image quality compensation on the image data, and provides a differential input signal (CEDA, CEDB) with a clock embedded in the data (image and control data) to the display driving device.
The display driving device 20 may recover the clock signal and data from the input signal (CEDA, CEDB) and drive the display panel 40 using the recovered clock signal and data. In addition, the display driving device 20 may detect a touch of the display panel 40 using the recovered clock signal.
The display driving device 20 may be equipped with a clock recovery device 1000 for recovering the clock.
Referring to
The clock generator 100 may receive transmission data (Clock Embedded Data: CED) in which a clock signal transmitted from a transmitter is embedded between data signals. The clock generator 100 may receive multi-level clock signals (CK1, CK2 . . . CK2N+1), which are delay clock signals output from a voltage controlled delay line 300, as inputs.
The clock generator 100 may generate a master clock signal (MCLK_PRE) by transmission data (CED) configured in the form of a clock signal input during a clock training period before the multi-level clock signals are generated. At this time, the number of multi-level clock signals must be at least greater than or equal to 2N+1, where N is a natural number representing the number of data bits existing between clock bits.
The delay control unit 200 according to the aspect may receive the master clock signal (MCLK_PRE). The delay control unit 200 may correct the delay time by using the multi-level clock signals output from the voltage-controlled delay line 300 and output the master clock signal (MCLK) whose delay time is corrected to the voltage-controlled delay line 300. The delay control unit 200 according to the aspect will be described in detail later.
The voltage-controlled delay line 300 may generate a multi-level clock signal by delaying the master clock signal (MCLK_PRE) by a preset reference delay time unit based on the input frequency. In addition, the voltage-controlled delay line 300 may generate a multi-level clock signal based on the master clock signal (MCLK) whose delay time is corrected.
As shown in
A plurality of inverters 310 may be used as the delay means. A plurality of inverters 310 uses two inverter pairs as one delay unit, and generate and output a delayed clock signal (CK1, CK2, CK3, . . . CK2N+1) while passing through the inverter pairs composed of two inverters.
In the above, the voltage-controlled delay line was described as a delay line, but it may also be configured as a current-controlled delay line (CCDL).
Returning to
The phase difference comparison unit 500 has as inputs any two signals among the multi-level clock signals delayed in the voltage-controlled delay line 300 based on the delay- locked loop along with the input clock signal of the delay-locked loop equipped with the delay means, and may generate an up/down signal (UP/DN) as a delay amount control signal by the time difference between the two signals.
When the lock signal becomes a logic high state and the delay-locked loop is locked, the phase difference comparison unit 500 has as inputs the master clock signal (MCLK) output from the clock generator 100 and any two clock signals among the delay clock signals (CK1, CK2, CK3, . . . , CK2N+1) output from the voltage-controlled delay line 300 whose time difference is the same as the cycle in which the clock bit is inserted. It may be configured to generate an up/down signal according to the time difference between these two input clock signals.
The low-pass filter 600 may remove or reduce the high-frequency component of the up/down signal (UP/DN) generated by the time difference of the two clock signals in the phase difference comparison unit 500 to output a voltage signal (VCOUNT). The low-pass filter 600 may be configured by a combination of a charge pump unit 610 and a loop filter unit 620.
Meanwhile, since the capacitor capacity or the length of the line providing the master clock signal in
In the aspect, the first delay time may be changed using a clock recovery device.
Referring to
The delay detector 210 may receive two clock signals (CK2, CK3) delayed by a reference delay time unit among multi-level clock signals and detect a delay time (CK2_delay) for the clock signal of CK2.
The delay detector 210 may compare the delay time (CK2_delay) with the reference delay time and output a selection signal based on the comparison result. Here, the reference delay time may be a predetermined time. For example, the reference delay time may be 0.5 UI, but the reference delay time may vary.
The clock extractor 220 may determine or change the inverter size that outputs the master clock signal based on the selection signal. Here, the selection signal may be ‘1’ or ‘0’. The clock extractor 220 may include a first inverter 221 of a big size and a second inverter 222 of a small size, but the number is not limited.
For example, when the input frequency is a low frequency, the first delay time may be increased by using the first inverter 221 of a big size. On the other hand, when the input frequency is a high frequency, the first delay time may be decreased by using the second inverter 222 of a small size.
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Referring to
The clock recovery method according to the aspect may be performed in a clock recovery device according to the aspect.
The clock generation unit may generate a master clock signal from embedded transmission data (S100). In more detail, the clock generation unit may receive transmission data (CED) in which a clock signal transmitted from the transmission unit is embedded between data signals. The clock generation unit may receive multi-level clock signals (CK1, CK2 . . . CK2N+1) output from the voltage-controlled delay line as input. The clock generation unit may generate a master clock signal (MCLK) by transmission data (CED) configured in the form of a clock signal input during the clock training period before the multi-level clock signals are generated.
The voltage-controlled delay line may generate a multi-level clock signal by delaying the master clock signal by a preset standard delay time unit based on the input frequency (S200).
In more detail, the voltage-controlled delay line may be configured based only on a delay-locked loop (DLL) equipped with a plurality of delay means capable of receiving, delaying, and outputting a master clock signal. A plurality of inverters may be used as the delay means. Multiple inverters use two inverter pairs as one delay unit, and generate and output a delayed clock signal (CK1, CK2, CK3, . . . CK2N+1) while passing through the inverter pairs composed of two inverters.
The delay control unit may determine the inverter size for correcting the first delay time (S300). The delay control unit may output a master clock signal whose delay time has been corrected by passing through the inverter.
As shown in
The delay control unit may compare the delay time with a preset reference delay time (S320).
The delay detector may compare the delay time with the reference delay time and output a selection signal based on the comparison result (S330). Here, the selection signal may include ‘1’ or ‘0’.
The delay detector may determine or change the inverter size that outputs the master clock signal based on the selection signal (S340).
For example, when the input frequency is low frequency, the first delay time may be increased by using a first inverter of a large size. On the other hand, when the input frequency is high frequency, the first delay time may be decreased by using a second inverter of a small size.
Returning to
Although the above has been described with reference to the drawings and aspects, it will be understood by those skilled in the art that the aspects of the present disclosure may be variously modified and changed within a scope that does not depart from the technical idea of the present disclosure described in the patent claims. Thus, it is intended that the present disclosure covers the modifications and variations of the aspects provided they come within the scope of the appended claims and their equivalents.
| Number | Date | Country | Kind |
|---|---|---|---|
| 10-2024-0003189 | Jan 2024 | KR | national |
| 10-2024-0120650 | Sep 2024 | KR | national |
