Patent Application
20060223261
The present invention relates to complimentary metal oxide semiconductor devices, and more particularly relates to devices and methods for fabricating a capacitive element operable at high frequencies using CMOS fabrication techniques. The invention also relates to ESD protection devices and methods using CMOS techniques.
Electronic circuits frequently make use of capacitors for numerous purposes, including filters as just one example of in a long list of uses. It is desirable to fabricate such capacitors integrally with the remaining devices that form the electronic circuit. This is particularly true for circuits comprised of solid state devices, which make up the vast majority of modern electronic circuits. In addition, the majority of modern circuits using solid state devices include devices fabricated using CMOS techniques. However, various limitations have made it difficult to fabricate capacitors integrally with CMOS transistors and similar devices, and particularly capacitors intended to operate at high frequency. Among these has been the existence of a resistor which is effectively connected in series with a capacitor formed in accordance with prior art techniques and significantly limits the application of such capacitive devices.
Such a prior art arrangement is shown in
As a result, there has been a need for a capacitor suitable for high frequency operation and capable of being fabricated through conventional CMOS techniques.
In addition, CMOS devices are susceptible to damage from electrostatic discharge, or ESD. While numerous techniques have been developed to protect CMOS devices, there has been a need for an ESD-protection device and method which could be fabricated through simple CMOS techniques.
The present invention provides a capacitive element or device capable of operation at high frequency, for example on the order of three Gigahertz or less, and capable of being fabricated using CMOS techniques. The invention includes providing a P doped substrate onto which a P− epitaxial layer (“epi”) has been deposited. Then, a P doped sinker deposition is formed which penetrates through the epi to electrically connect to the substrate. Standard P+ depositions are then formed within the sinker deposition, characteristic of the source and drain depositions typical of many types of CMOS transistors.
In a first embodiment, a thin silicon oxide layer is formed above the sinker, and typically between the two P+ depositions. A metal layer is then formed atop at least a portion of the oxide layer. Electrical contacts may then be made in any suitable manner to the substrate and to the metal layer. A capacitor is formed by the sandwich of the metal layer, silicon oxide and the sinker deposition connected to the substrate. The value of the capacitor may be varied by the area (a design criteria) and the oxide thickness (a process criteria). While the design criteria may be readily changed, the process criteria frequently would not be changed to avoid impacting the remaining processing.
In an alternative arrangement, the metal layer and oxide layers are not required. Instead, an N+ deposition is formed within the sinker area, and the boundary between the N+ region and the sinker forms a capacitive element. It will also be noted that the combination of the N+ region within the P doped sinker region forms a diode, which may be configured to provide protection against electrostatic discharge. In at least some implementations of the present invention the diode will have a breakdown voltage on the order of six to nine volts, and a series resistance which is typically less that five ohms.
These and other features of the invention will be better understood from the following detailed description of the invention, taken together with the attached Figures.
Referring first to
An oxide layer 240 is formed over the sinker region in a conventional manner, and a metal layer 250 is formed atop the oxide layer, also in a conventional manner. A contact is formed in electrical connection with the metal layer 250, and another on the back of the substrate 200, such that the metal layer, oxide and substrate form a capacitor 300 as represented electrically in
An alternative arrangement to the structure of
Then, again using CMOS techniques, an N+ deposition 430 is formed within the sinker region 420. By reverse biasing the junction of the N+ deposition 430 and the P sinker region, a charge layer 440 is formed therebetween, which is represented electrically as a capacitor 510 in
One example of a process flow for the fabrication of the invention can be appreciated from
Next, at step 620, a high temperature drive is applied, typically on the order of 1125-1200 C for several hours. The objective is to diffuse the P+ dopant applied in step 610 through the P− epi to the P+ substrate, with a reasonably uniform surface concentration. It will be appreciated that these relatively high temperatures and relatively long drive times can be adjusted significantly, as long as appropriately low impedance electrical connection is made between the P+ sinker region and the substrate.
Then, at step 630, the zener is formed through conventional masking and implanting steps. In particular, an N-type implant is implanted into the P sinker, using a dose generally in the range of low E15 to low E16; this forms the N+ region of the Zener diode. The N+ region is typically formed in a conventional manner using CMOS or NMOS process flow.
Then, at step 640, conventional connections are made to N+ region and the P+ sinker. Connections to the P+ sinker can be made, for example, by a P+ deposition or by backside contacts.
It will be appreciated from the foregoing that the low dynamic resistance capacitor/Zener diode structure of
The breakdown voltage of the Zener diode, typically in the range of 5-8 volts, can be modified by adjusting the concentration of the P type sinker. By providing low series resistance, the device can sink high currents during an ESD event, thus ensuring that the voltage does not increase to dangerous levels that can damage gate oxides, metal lines, semiconductor devices, and so on. The device can also be scaled in area size to optimize the use of space on the die, as well as meeting ESD requirements.
Set forth in Table 1, below, are a series of examples of the variation of the Zener breakdown voltage at various doses and intensities, and drive times and temperatures.
Having fully described a preferred embodiment of the invention and various alternatives, those skilled in the art will recognize, given the teachings herein, that numerous alternatives and equivalents exist which do not depart from the invention. It is therefore intended that the invention not be limited by the foregoing description, but only by the appended claims.
