CMOS IMAGE SENSOR AND METHOD FOR MANUFACTURING THE SAME

Abstract

Embodiments relate to a CMOS image sensor. In embodiments, the CMOS image sensor may include a semiconductor substrate, a photodiode, a first conduction type impurity region, a first insulating layer, a conduction layer, and a second insulating layer. The semiconductor substrate may have a trench in which a device isolation layer is to be formed. The photodiode may be formed in an active region of the semiconductor substrate, and the first conduction type impurity region may be formed in sidewalls of the trench. The first insulating layer may be formed inside the trench, and a conduction layer may be formed inside the trench and doped with second conduction type impurities. A second insulating layer may be formed inside the trench.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is an example circuit diagram of a 3T type CMOS image sensor;

FIG. 2 is an example layout diagram illustrating a unit pixel of a 3T type CMOS image sensor;

FIG. 3 is an example cross-sectional diagram illustrating a photodiode region of a related art CMOS image sensor;

FIG. 4 is an example cross-sectional diagram of a related art photodiode region;

FIGS. 5A and 5B are example cross-sectional diagrams illustrating a process for forming p-type impurity region according to the related art;

FIG. 6 is an example graph illustrating a concentration of boron measured along line I-I′ of FIG. 5B;

FIG. 7 is an example potential profile illustrating a problem of the related art CMOS image sensor;

FIGS. 8A to 8E are example cross-sectional diagrams illustrating a process of forming an impurity region in a device isolation layer of a CMOS image sensor according to embodiments;

FIG. 9 is an example cross-sectional diagram of a p-type impurity region, a thermal oxide layer, and a polysilicon patterns doped with n-type impurities of FIG. 8E, according to embodiments; and

FIG. 10 is an example diagram illustrating a potential profile taken along line II-II′ of FIG. 9, according to embodiments.

Claims

1. A device comprising: a semiconductor substrate having a trench;an impurity region doped with first conduction type impurities and formed in sidewalls of the trench;a first insulating layer formed in the trench;a conduction layer doped with second conduction type impurities and formed in the trench; anda second insulating layer formed in the trench.

2. The device of claim 1, further comprising a photodiode formed in an active region of the semiconductor substrate.

3. The device of claim 1, wherein the conduction layer is formed between the impurity region and the second insulating layer.

4. The device of claim 1, wherein the first insulating layer is formed between the impurity region and the conduction layer.

5. The device of claim 1, wherein the first insulating layer is formed on a lower portion of the trench and sidewalls of the impurity region.

6. The device of claim 5, wherein the conduction layer is formed over a surface of the first insulating layer.

7. The device of claim 1, wherein the conduction layer comprises a polysilicon layer doped with As.

8. The device of claim 7, wherein the conduction layer is patterned by removing a portion of the polysilicon layer.

9. The device of claim 1, wherein the impurity region comprises implanted boron-based impurity ions.

10. The device of claim 1, wherein the first conduction type impurities comprise P-type impurities and the second conduction type impurities comprise n-type impurities.

11. The device of claim 1, wherein the first insulating layer comprises a thermal oxide layer and the second insulating layer comprises an oxide layer formed by chemical vapor deposition.

12. A method comprising: forming a trench in a semiconductor substrate;forming an impurity region doped with first conduction type impurities in sidewalls of the trench;forming a first insulating layer in the trench;forming a conduction layer doped with second conduction type impurities in the trench; anddepositing a second insulating in the trench.

13. The method of claim 12, further comprising forming a photodiode in an active region of the semiconductor substrate.

14. The method of claim 12, wherein the impurity region is formed by implanting boron-based impurity ions in the sidewalls of the trench.

15. The method of claim 12, wherein forming the conduction layer comprises: forming a polysilicon layer on the semiconductor substrate and the impurity region; andetching a portion of the polysilicon layer formed inside the trench to form polysilicon patterns.

16. The method of claim 15, wherein the polysilicon layer is doped with As.

17. The method of claim 16, wherein a doping concentration of As is in a range of 1018-1019 atoms/cm3.

18. The method of claim 15, wherein etching the polysilicon layer comprises removing a portion of the polysilicon layer that is formed on a lower portion of the trench.

19. The method of claim 12, wherein the first insulating layer is formed on a lower portion of the trench and sidewalls of the impurity region.

20. The method of claim 12, wherein the first conduction type impurities comprise p-type impurities and the second conduction type impurities comprise n-type impurities.