Patent Application
20060134862
The present disclosure relates generally to integrated circuits and semiconductor devices, and more particularly, to a CMOS Non-Volatile Memory (NVM) bitcell.
In applications that use CMOS, including CMOS logic integrated circuits (ICs), some NVM capability is usually desirable. Because many of these applications are cost-sensitive, the NVM functionality is usually expected to be provided at very little or no additional cost. In these systems, NVM is often used to store personalization data, trim coefficients, serial numbers and other manufacturing data. As a result, the required bitcounts are usually small. However, the presence of even these small amounts of NVM adds significantly to the capability and desirability of the IC in customer systems.
In order to satisfy such requirements for the presence of NVM in an IC, there exist several single-poly CMOS NVM structures. As CMOS feature sizes shrink to deep sub-micron levels, some of these structures fail to operate as expected, often for reasons related to the lower junction breakdown voltages in scaled processes.
In addition to the problems of decreasing transistor and junction breakdown voltages, deep sub-micron CMOS logic, RF and Analog processes introduce other factors that must be considered in the design and operation of single-poly NVM cells. These include scaled gate oxides and MIM capacitors. Scaled gate oxides help to ameliorate the issue of decreasing transistor and junction breakdowns by requiring lower voltages for Fowler-Nordheim (FN) tunneling.
However, thin gate oxides also force the process designer and manufacturing fab to ensure that the transistor gate oxide quality is extremely high in order to maintain any data retention capability as the oxide thickness is decreased. Therefore, as gate dielectrics are scaled, it becomes increasingly difficult to satisfy the reliability specifications of numerous NVM applications.
Accordingly, it would be desirable to provide an improved CMOS NVM bitcell structure for overcoming the problems in the art.
The embodiments of the present disclosure are illustrated by way of example and not limited by the accompanying figures, in which like references indicate similar elements, and in which:
The use of the same reference symbols in different drawings indicates similar or identical items. Skilled artisans will also appreciate that elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale. For example, the dimensions of some of the elements in the figures may be exaggerated relative to other elements to help improve the understanding of the embodiments of the present invention.
According to one embodiment of the present disclosure, a bitcell structure makes use of a MIM capacitor structure available via deep sub-micron CMOS processes. The bitcell structure incorporating the MIM capacitor structure solves problems in the art posed by decreased junction/oxide breakdowns and oxide thicknesses in such scaled processes. In one embodiment, the bitcells eliminate any transistors, commonly CMOS, from the storage node in order that their gate oxide does not affect data retention of the device. In addition, the bitcell embodiments of the present disclosure do not add to the wafer process cost because they require no additional processing steps. Furthermore, in one embodiment, the bitcell structure allows for achieving a denser single-poly NVM array than that achievable with conventional single-poly NVM bitcells.
According to one embodiment of the present disclosure, the NVM bitcell structure eliminates a transistor gate and its thin gate oxide from the storage node of the device. Instead, the stored charge resides on a separate capacitor, for example, a MIM capacitor. Accordingly, the bitcell structure can be used independently of technology node. In addition, although a MIM capacitor has been disclosed, the bitcell structure storage node is not limited to only MIM capacitors. Furthermore, with the embodiments of the present disclosure, in the presence of a good enough capacitor, it is unnecessary to have a gate oxide robust enough for Non-Volatile Memory applications. This allows use of the bitcell structure on other technology platforms such as compound semiconductors.
The embodiments of the present disclosure overcome problems in the art, in part, because the transistor gate oxide is no longer in the storage node. Accordingly, the data retention problems caused by CMOS scaling of the gate oxide are eliminated.
Bitcell structure 10 further includes a first conductive line 28 (ML1) and a second conductive line 30 (ML2). Vias 32 electrically couple first conductive line 28 to the top plate 20 of MIM capacitor 14. Similarly, vias 34 electrically couple second conductive line 30 to the top plate 26 of MIM capacitor 22. Bitcell structure 10 still further includes a dielectric, generally indicated by reference numeral 36.
In other words, programming of bitcell structure 10 can be accomplished by raising ML1 to a high potential while grounding ML2. Since C2<C1, the field is largely confined to C2 and allows electrons to move unto the bottom plate 16 of the dual MIM capacitor (14, 22) through the dielectric 24 in C2. Removing the bias from ML1 decreases the fields across both C1 and C2 and leaves the electrons trapped on the bottom plate of the dual MIM capacitor. The same operation could also be accomplished by grounding ML1 and placing a large negative bias on ML2. Generally, the programming biases can be split between ML1 and ML2, as long as the potential of ML1 is higher than that of ML2 and the potential difference between ML1 and ML2 is large enough to create sufficient field across C2.
In other words, the bitcell structure 10 can be erased by grounding ML1 and raising ML2 to a high positive bias. The field across C2 now points in the opposite direction, allowing the electrons trapped on the bottom plate 16 of the dual MIM capacitor (14, 22) to move through the dielectric 24 in C2, erasing the bitcell. In general, the erase operation can be accomplished with any combination of biases on ML1 and ML2, such that the potential of ML2 is higher than that of ML1 and the difference is large enough to create a sufficiently large field across C2.
In other words, one method of reading the bitcell 10 involves temporarily connecting it to a MOS transistor (or MOSFET). During a Read operation, either ML1 or ML2 is connected to the gate of the MOSFET. For this example, assume ML2 is connected to the gate of a “READ” MOSFET. The MOSFET source and drain are biased with the same consideration for speed of operation limitations as for a conventional bitcell. The other metal line ML1 is then biased to a potential VcgR, such that VtE<VcgR<VtP, where VtE and VtP are the apparent program and erase thresholds of the MOSFET as seen from ML1. Again, erased bitcells will conduct current and programmed bitcells will not, allowing the states to be distinguished.
In a first programming scheme, the programming operation is performed as follows and includes the use of a split-bias scheme. To program the selected bitcell 62 using the split-bias scheme, program biases Vpp2 and Vpp1 are applied to row line 66 and column line 74, respectively. All other row lines (64, 68, 70) and column lines (72, 76) are grounded. The total voltage across the capacitors (i.e., C1 and C2) of the selected bitcell 62 is now Vpp1-Vpp2 (i.e., the voltage difference between Vpp1 and Vpp2). Bitcells sharing the same column line 74 have a potential Vpp1 across their capacitors while those bitcells on row line 66 are subjected to a potential drop of Vpp2. If the magnitude of (Vpp1-Vpp2) is greater than the magnitudes of Vpp1 and Vpp2 separately, then bitcell 62 can be programmed without programming other bitcells sharing the same row line or column line. This can be done, for example, by making Vpp1 positive and Vpp2 negative. Bitcells which do not share either a row line or column line with bitcell 62 do not experience any potential drop and, therefore, will not be programmed or erased. Accordingly, per this first programming scheme, selected bitcell 62 is the only bitcell programmed.
In a second programming scheme, the programming operation is performed as follows to avoid the generation of a negative bias. The programming operation includes an alternative split-bias scheme for programming bitcell 62 in array 60. The alternative split-bias scheme is to ground all column lines, except column line 74 and apply a positive inhibitory bias, Vinhp, to all row lines except row line 66. Row line 66 is then grounded to program bitcell 62. The potential across bitcell 62 is now Vpp1. Bitcells on the same row line as selected bitcell 62 have no voltage drop across them and, therefore, are not programmed. Bitcells on the same column line as selected bitcell 62 experience a potential drop of (Vpp1-Vinhp). Since Vinhp is positive, the quantity (Vpp1-Vinhp) is of smaller magnitude. Accordingly, the bitcells on the same column line as selected bitcell 62 that experience the potential drop of (Vpp1-Vinhp) are not programmed. The magnitude of the potential across all other bitcells is Vinhp, which can be chosen to be small enough so as not to program the corresponding bitcells. Accordingly, per this second programming scheme, selected bitcell 62 is the only bitcell programmed.
In a third programming scheme, the programming operation is performed as follows. In this third programming scheme, the roles of the rows and columns are interchanged from that of the second programming scheme. That is, in the third programming scheme, the inhibitory biases are applied to the unselected columns and the unselected rows are grounded. The inhibitory biases are negative biases in this third programming scheme. Accordingly, column line 74 is grounded while row line 66 is biased with a negative polarity Vpp2. Accordingly, per this third programming scheme, selected bitcell 62 is the only bitcell programmed.
In addition to the program schemes, the embodiments of the present disclosure include erase schemes. That is, the erase schemes can include split-bias schemes for erasing selected bitcell 62 of array 60 and are very similar to those schemes used for programming the same. For example, the programming methods described above can be used to erase the selected bitcell by changing the polarity of the applied biases. However, merely changing the polarity of the applied biases would lead to the use of predominantly negative voltages for erasing the selected bitcell. Since negative voltages are usually more difficult to generate on-chip, alternative methods of erasure using primarily positive voltages are desired, as discussed further herein below.
In a first erase scheme, the erase operation is substantially similar of the first programming scheme, however the roles of Vpp1 and Vpp2 are reversed. So, for example, instead of a positive Vpp1 and a negative Vpp2, the equivalent erase scheme would use a negative Vpp1 on column line 74 and a positive Vpp2 on row line 66 with all other row and column lines grounded. Similar to the situation in the first programming scheme, bitcells which share neither a row line nor a column line with the selected cell 62 of the array 60 do not see any applied bias and are not erased. Bitcells sharing a column line experience a bias of Vpp1 while bitcells sharing a row line experience a bias of Vpp2. With negative Vpp1 and positive Vpp2, the respective biases are smaller in magnitude than (Vpp2-Vpp1). With appropriately selected values for Vpp1 and Vpp2, the biases are too small to erase the other bitcells, while (Vpp2-Vpp1) is large enough to erase selected bitcell 62. Accordingly, per this first erase scheme, selected bitcell 62 is the only bitcell erased.
In a second erase scheme, the erase operation is substantially similar to the second programming scheme. However, the second erase scheme is intended to avoid the necessity for generating negative voltages for erasing the bitcell. In this second erase scheme, Vpp2 is applied to row line 66 while all other row lines are grounded. An inhibitory bias, Vinhe, is applied to all column lines except column line 74. Column line 74 is grounded to erase the selected bitcell 62. Bitcells on the same column as the selected cell have no applied bias and so are not erased. Bitcells on other columns, not common with the column line of the selected bitcell have Vinhe applied across them. Vinhe is selected to be low enough not to be capable of causing erasure by itself and so these bitcells are not erased. Other bitcells on row line 66 have the differential voltage of (Vpp2-Vinhe) applied across them and so are not erased. The full Vpp2 bias is applied across the selected bitcell 62. Accordingly, per this second erase scheme, selected bitcell 62 is the only bitcell erased.
In a third erase scheme, the erase operation interchanges the roles of the row lines and column lines in the second erase scheme. That is, in the third erase scheme, the inhibitory biases are applied to all row lines except row line 66, which is grounded. All column lines except column line 74 are also grounded, while Vpp1 is applied to column line 74. Vpp1 is of a negative polarity in order to erase the selected bitcell, wherein the selected bitcell is the only cell erased with properly chosen values of Vpp1 and Vinhe.
Accordingly, in the dual MIM capacitor version of the bitcell structure 10, the presence of two control gate capacitors and their associated metal lines enables a “half-select” bitcell selection mechanism. Because of this, the ability to create an array of bitcells with no “select gate transistor” to protect unselected bitcells is possible. Such an array is denser, and therefore more cost-effective, than an array which requires a select transistor.
Bitcell structure 80 still further includes a MOS transistor 83. MOS transistor 83 includes a source region 84 and drain region 86 formed within an active region of substrate 82. MOS transistor 83 further includes gate dielectric 88 and a floating gate 90. Floating gate 90 comprises a conductive gate electrode, for example, metal, polysilicon, or other suitable gate electrode material and/or structure. Electrical contact to the source region 84 and drain region 86 is accomplished via metalizations 85 and 87, respectively.
Further with respect to the embodiment of
Accordingly, the dual MIM capacitor control gate structure of
In other words, with respect to the bitcell structure 80 of
Further with respect to the bitcell structure 80 of
As discussed herein, the structure of
The bitcell structure 10, illustrated in
Bitcell structure 100 still further includes a MOS transistor 83. MOS transistor 83 includes a source region 84 and drain region 86 formed within an active region of substrate 82. MOS transistor 83 further includes gate dielectric 88 and a floating gate 90. Floating gate 90 comprises a conductive gate electrode, for example, metal, polysilicon, or other suitable gate electrode material and/or structure. Electrical contact to the source region 84 and drain region 86 is accomplished via metalizations 85 and 87, respectively.
Further with respect to the embodiment of
Bitcell structure 100 still further includes erase well 114 formed within substrate 82. A contact region 116 is formed in erase well 114 for providing for electrical contact to the well. A dielectric 118 is formed over a portion of erase well 114. Furthermore, a electrode is formed over the dielectric 118. As illustrated, the electrode formed over the dielectric 118 is an extension of gate electrode 90 of transistor 83. Alternatively, electrode formed over the dielectric 118 could be an electrode separate from gate electrode 90, but electrically coupled to the electrode formed over the dielectric 118. The combination of the electrode over the dielectric 118, the dielectric 118, and the erase well 114 form a capacitor structure 120.
As feature sizes decrease, the source and drain junctions become less able to sustain the voltages necessary for tunneling and the structure of
As disclosed herein, the embodiments have been included MIM capacitors as the storage node. However, for the embodiment including two capacitors but no transistor in the storage node, it is possible to use double-poly capacitors or metal-insulator-poly capacitors. The double-poly capacitors or metal-insulator-poly capacitors provide the benefit of removing the thin transistor gate oxide from the storage node. Furthermore, a double-poly capacitor can generally be built more reliably than a MIM capacitor with current process technology.
In the foregoing specification, the disclosure has been described with reference to various embodiments. However, one of ordinary skill in the art appreciates that various modifications and changes can be made without departing from the scope of the present embodiments as set forth in the claims below. Accordingly, the specification and figures are to be regarded in an illustrative rather than a restrictive sense, and all such modifications are intended to be included within the scope of the present embodiments.
Benefits, other advantages, and solutions to problems have been described above with regard to specific embodiments. However, the benefits, advantages, solutions to problems, and any element(s) that may cause any benefit, advantage, or solution to occur or become more pronounced are not to be construed as a critical, required, or essential feature or element of any or all the claims. As used herein, the term “comprises,” “comprising,” or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus.
