Number | Date | Country | Kind |
---|---|---|---|
61-213114 | Sep 1986 | JPX |
Number | Name | Date | Kind |
---|---|---|---|
4200917 | Moench | Apr 1980 | |
4275312 | Saitou et al. | Jun 1981 | |
4309629 | Kamuro | Jan 1982 | |
4446386 | Kurafuji | May 1984 | |
4571510 | Seki et al. | Feb 1986 | |
4700086 | Ling et al. | Oct 1987 | |
4730133 | Yoshida | Mar 1988 |
Entry |
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IEEE, Katsutaka Kimura et al, "Power Reduction Techniques in Megabit DRAMS's", vol. SC-21, No. 3, Jun. 1986, pp. 381-389. |
Hafani, "Bit Line Discharge Circuit for NAND Logic Read-Only Storage Arrays", IBM T.D.B., vol. 23, No. 7B, Dec. 1980, pp. 3181-3182. |
Lane et al, "FET Parallel Decoder", IBM T.D.B., vol. 11, No. 5, Oct. 1968, p. 444. |