The present invention relates generally to semiconductor processing, and more particularly to a method for chemical-mechanical polishing (“CMP”) of a workpiece. Specifically, the present invention relates to processes for reducing defects on a semiconductor wafer.
Some known chemical-mechanical processes for polishing a semiconductor wafer may include forming a dielectric layer over the semi-conductor substrate, etching a plurality of trenches into the dielectric layer, and forming a barrier layer over the dielectric layer and the trenches. These known processes also may include forming a copper seed layer over the barrier layer and forming a copper layer over the copper seed layer, such that a portion of the copper seed layer and a portion of the copper layer also are disposed in the trenches. In these known processes, the copper layer, the copper seed layer, and the barrier layer may be removed over portions of the wafer via a rotating polishing pad, wherein the polishing pad rotates with respect to the wafer. The wafer may also rotate with respect to the rotating polishing pad, and a slurry composition is disposed on the side of the polishing pad in contact with the various layers on the wafer, wherein the slurry composition assists in polishing and/or oxidizing the layers.
Moreover, one polishing pad may be used to remove the copper layer(s) and another polishing pad may be used to remove the barrier layer, wherein the each polishing pad polishes the wafer in a generally serial manner.
Typically, in a process wherein several polishing and buffing processes are serially performed on the same wafer, pressure is applied to the wafer by the polishing or buffing pads, wherein the slurry composition(s) is utilized to aid in the polishing or buffing processes. Once each the respective polishing or buffing process is complete, the pressure applied by the respective polishing or buffing pads to the wafer is alleviated, however, the wafer is not moved to the next polishing or buffing process until the next process is ready. During the time that the wafer is waiting, de-ionized water or other solutions may be introduced between the polishing or buffing pads and the wafer, in an attempt to reduce defects in the wafer.
In serial processing, however, one polishing process or buffing process may take less time than the remaining processes, and as such, the polished and/or buffed wafer waits until the completion of the longest processes before being moved to the next polishing process. In one example, an “all heads ready” signal or “AHR” situation is needed in a multiple-pad polishing CMP apparatus before the wafers can be moved to the next process step. During this wait, the wafer(s) continue to rotate and are exposed to the polishing pads and slurry or rinsing agent, despite there being very little to no pressure being applied thereto the polishing pads. It is at this time that some particles between the wafer and the polishing and buffing pads may cause defects on the wafer. Further, defects that are formed after a particular polishing process is completed, such as deep scratches or strongly adherent particles or residues, may not be removable by the subsequent polishing or buffing process.
Therefore, a need has arisen for processes that overcome these and other shortcomings of the related art. The following presents a simplified summary of the invention in order to provide a basic understanding of some aspects of the invention. This summary is not an extensive overview of the invention. It is intended to neither identify key or critical elements of the invention nor delineate the scope of the invention. Its purpose is to present some concepts of the invention in a simplified form as a prelude to the more detailed description that is presented later.
The present invention is generally directed toward a method for serially polishing a plurality of semiconductor wafers, wherein defects are generally mitigated. The method comprises providing a chemical-mechanical polishing (CMP) apparatus having at least a first polishing stage having a first polishing pad associated therewith and a second polishing stage having a second polishing pad associated therewith. The CMP apparatus may further comprise one or more additional polishing stages comprising one or more additional polishing pads, and/or a buffing pad. In accordance with the present invention, a first slurry composition is generally disposed between the first polishing pad and a first wafer when the first wafer is in a first state of polishing at the first polishing stage. The first state of polishing, for example, is a “raw” wafer, wherein no polishing has been yet performed on the first wafer. The first wafer, for example, comprises at least a first layer formed thereon, wherein the first layer may comprise a metal or other material such as a dielectric material. A second slurry composition is further generally disposed between the second polishing pad and a second wafer when the second wafer is in a second state of polishing at the second polishing stage. The second state of polishing, for example, may be after the second wafer has undergone polishing at the first polishing stage, wherein at least a portion of the first layer has been generally removed from the surface of the second wafer.
A first polishing on the first wafer is commenced at a first commencement time, wherein the first polishing generally polishes the first wafer via relative motion of the first polishing pad and first slurry composition over the first wafer. A first pressure may be applied to the first polishing pad during the first polishing. A second polishing on the second wafer is commenced at a second commencement time, wherein the second polishing generally polishes the second wafer via relative motion of the second polishing pad and second slurry composition over the second wafer. A second pressure may further be applied to the second polishing pad during the second polishing. Likewise, additional polishing, cleaning, and/or buffing processes may be performed on additional wafers in a similar manner at the one or more additional polishing stages.
In accordance with the present invention, the second commencement time differs from the first commencement time by a first intermediate period. According to the invention, one or more of the first wafer and the second wafer are generally rinsed with a pre-rinse agent for at least a portion of the first intermediate period, wherein the rinsing is based on a status of the respective first polishing and second polishing. The status of the first polishing and second polishing, for example, is associated with whether the respective first wafer and second wafer is presently being polished by the respective first polishing pad and second polishing pad.
The first polishing on the first wafer and second polishing on the second wafer are halted at substantially the same end time, therein placing the first wafer in the second state and the second wafer in a third state. The third state, for example, may be after at least another portion of the first layer has been generally removed from the surface of the second wafer.
To the accomplishment of the foregoing and related ends, the invention comprises the features hereinafter fully described and particularly pointed out in the claims. The following description and the annexed drawings set forth in detail certain illustrative embodiments of the invention. These embodiments are indicative, however, of a few of the various ways in which the principles of the invention may be employed. Other objects, advantages and novel features of the invention will become apparent from the following detailed description of the invention when considered in conjunction with the drawings.
The present invention is directed towards chemical-mechanical polishing (CMP) of a workpiece, wherein defects are generally mitigated. Accordingly, the present invention will now be described with reference to the drawings, wherein like reference numerals are used to refer to like elements throughout. It should be understood that the description of these aspects are merely illustrative and that they should not be taken in a limiting sense. In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the present invention. It will be evident to one skilled in the art, however, that the present invention may be practiced without these specific details.
Referring now to the figures,
The CMP apparatus 100, for example, comprises a first polishing stage 112 comprising a first wafer carrier 113 and a first polishing pad 115, and a second polishing stage 117 comprising a second wafer carrier 118 and a second polishing pad 120, wherein the first polishing pad is configured to substantially remove at least a portion of the one or more layers of a first wafer 110A, and the second polishing pad 120 is configured substantially remove at least another portion of the one or more layers of a second wafer 110B. For example, the first polishing pad 115 and second polishing pad 120 are configured to respectively substantially remove a copper layer (not shown) and a barrier layer (not shown) associated with the first and second wafers 110A and 110B. The CMP apparatus 100, for example, may further comprise one or more additional polishing stages 122 comprising one or more additional wafer carriers 123 and one or more additional polishing pads 124, wherein the one or more additional polishing pads may be configured to remove yet another portion of the one or more layers on an additional wafer 110C (e.g., a third wafer). In one example, the one or more additional polishing stages 122 may comprise a buffing pad 125, wherein the buffing pad is configured to buff or surface condition the third wafer 110C in order to buff out topographical defects. In the present example, the first wafer carrier 113, second wafer carrier 118 and one or more additional wafer carriers 123 are configured to serially transfer the plurality of wafers 110 between the first, second, and additional polishing stages 112, 117, and 122.
In order to mitigate defects, in accordance with the present invention, a method 200 for serial CMP processing of a plurality of workpieces or wafers is provided in
The method 200 begins with act 205, wherein a CMP apparatus is provided, and wherein the CMP apparatus comprises at least a first polishing pad at a first polishing stage and a second polishing pad at a second polishing stage. The CMP apparatus provided in act 205 may further comprise additional polishing pads and/or a buffing pad at additional stages, and all such CMP apparatus are contemplated as falling within the scope of the present invention. In act 210, a first slurry composition is generally disposed between the first polishing pad and a first wafer when the first wafer is in a first state of polishing at the first stage. The first state of polishing, for example, is a “raw” or unpolished wafer state, wherein, in general, no polishing has been yet performed on the first wafer. A second slurry composition is further generally disposed between the second polishing pad and a second wafer in act 215 when the second wafer is in a second state of polishing at the second stage. The second state of polishing, for example, may be after at least a portion of the first layer has been generally removed from the surface of the second wafer.
A first polishing on the first wafer at the first stage is commenced at a first commencement time in act 220, wherein the first polishing generally polishes the first wafer via relative motion of the first polishing pad and first slurry composition with respect to the first wafer. A first pressure, for example, may be applied between the first polishing pad and the first wafer during the first polishing. A second polishing on the second wafer is commenced at a second commencement time in act 225, wherein the second polishing generally polishes the second wafer via relative motion of the second polishing pad and second slurry composition with respect to the second wafer. A second pressure, for example, may be applied between the second polishing pad and the second wafer during the second polishing. In accordance with the present invention, the second commencement time differs from the first commencement time by a first intermediate period.
In accordance with the invention, prior to the commencement of act 220, the first wafer is generally rinsed with a pre-rinse agent for at least a portion of the first intermediate period in act 230. The pre-rinse agent, for example, comprises one or more of de-ionized water, benzotriazole (BTA), or another moisture maintaining compound or pre-rinse agent. The pre-rinse agent, for example, generally prevents degradation and/or corrosion of the first layer. Likewise, prior to the commencement of act 225, the second wafer is generally rinsed with the pre-rinse agent for at least another portion of the first intermediate period in act 235, wherein the rinsing of acts 230 and 235 is based on a status of the respective first polishing and second polishing of acts 220 and 225. The pre-rinse agent may be similar for the rinsing of acts 230 and 235, or different pre-rinse agents may be utilized. The status of the first polishing and second polishing, for example, is associated with whether the respective first wafer and second wafer is presently being polished by the respective first polishing pad and second polishing pad.
In act 240, the first polishing on the first wafer of act 220 and the second polishing on the second wafer of act 225 are halted at substantially the same end time, therein placing the first wafer in the second state and the second wafer in a third state. The third state, for example, may be after at least another portion of the first layer has been generally removed from the surface of the second wafer.
Act 245, for example, a third slurry composition is further generally disposed between a third polishing pad or buffing pad and a third wafer when the third wafer is in the third state of polishing at a third stage. In act 250, a commencement of an additional polishing or buffing on the third wafer in the third state at the third stage via the third polishing pad or buffing pad at a third commencement time, wherein the third commencement time differs from the first commencement time by a second intermediate period, and wherein the third commencement time differs from the second commencement time by a third intermediate period. Prior to the commencement of act 250, however, in act 255, the third wafer is rinsed with the pre-rinse agent for at least a portion of one or more of the first intermediate period, second intermediate period, and third intermediate period. As such, act 240 further generally halts the polishing or buffing on the third wafer at substantially the same end time as the halting of the first polishing of act 220 and halting of the second polishing of act 225, therein placing the third wafer in a fourth state at the additional or third stage. In an alternative example, act 240 may provide for any serial process wherein halting of polishing of acts 220, 225, and 250 is controlled such that the rinsing of acts 230, 235, and 255 is performed prior to the respective polishing, wherein defects are generally reduced. It should be further noted that during at least a portion of one or more of the first intermediate time, second intermediate time, and third intermediate time, one or more of the first polishing pad, the second polishing pad, and the buffing pad can be further rinsed with a residual slurry removal compound.
In act 260, the next CMP process on the plurality of wafers is performed. For example, the first wafer is moved from the first stage to the second stage, to be polished by the second polishing pad, the second wafer is moved from the second stage to the additional stage to be polished or buffed by the additional polishing pad or buffing pad. Accordingly, in the present example, the third wafer is removed from the additional stage of the CMP apparatus, and a fourth wafer (e.g., another un-polished wafer in the first state) is polished by the first polishing pad in the first stage, thus serially processing the plurality of wafers. Furthermore, while an exemplary cross-shaped CMP apparatus 100 is illustrated in
Although the invention has been shown and described with respect to a certain aspect or various aspects, it is obvious that equivalent alterations and modifications will occur to others skilled in the art upon the reading and understanding of this specification and the annexed drawings. In particular regard to the various functions performed by the above described components (assemblies, devices, circuits, etc.), the terms (including a reference to a “means”) used to describe such components are intended to correspond, unless otherwise indicated, to any component which performs the specified function of the described component (i.e., that is functionally equivalent), even though not structurally equivalent to the disclosed structure which performs the function in the herein illustrated example embodiments of the invention. In addition, while a particular feature of the invention may have been disclosed with respect to only one of several aspects of the invention, such feature may be combined with one or more other features of the other aspects as may be desired and advantageous for any given or particular application. Furthermore, to the extent that the term “includes” is used in either the detailed description or the claims, such term is intended to be inclusive in a manner similar to the term “comprising.”
This application claims priority to Ser. No. 60/876,740 filed Dec. 22, 2006, which is entitled “CMP Related Scratch and Defect Improvement”.
Number | Date | Country | |
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60876740 | Dec 2006 | US |