Patent Application
20160260794
1. Field of the Invention
Generally, the present disclosure relates to the field of integrated circuits and semiconductor devices and, more particularly, to the formation of high quality coil inductors used in integrated circuits.
2. Description of the Related Art
The fabrication of advanced integrated circuits, such as CPUs, storage devices, ASICs (application specific integrated circuits) and the like, requires the formation of a large number of circuit elements on a given chip area according to a specified circuit layout. More recently, with the advent of integrated circuits and electronic miniaturization, the need arose to reduce the size of external discrete components necessary with an integrated circuit product, preferably, elimination of any discrete components was a primary goal. More and more, formerly discrete components were fabricated onto integrated circuits, i.e., resistors, capacitors and inductors, for both size and cost reasons. Inductors ere especially a problem because of the physical size and geometry normally required for an effective inductor over a desired range of frequencies. In general, inductors are important components in many of the building blocks in wireless communication systems, such as RF bandpass filters, oscillators, impedance matching networks and/or emitter degeneration circuits. Wireless communication standards place stringent requirements on performance and operating parameters, such as noise interference/immunity and power consumption. To accommodate the stringent requirements, high quality (Q) inductors are needed.
Ideally, an inductor acts as a purely reactive device. However, in reality, the performance of an inductor is impacted by parasitic losses distributed within the inductor. The real inductor incurs losses that are due to, for example, built-in resistance of the wire. Other losses may also include those due to, for example, skin effect, proximity effect, as well as eddy current in the underlying substrate. The losses incurred by the inductor are represented as Rs or effective series resistance. The total impedance Z of the circuit is defined as Z=Rs+XL including real component Rs, and an imaginary component XL which is the effective reactance. The effective reactance of the inductor XL is equal to jωL. As such the total impedance Z of the inductor is defined as Z=Rs+jωL. The Q factor indicates how close a real inductor is to an ideal inductor. The higher the Q factor, the better is the performance of the inductor. The Q factor is defined by Q=Im(Z)/Re(Z)=ωL/Rs. Typically, a high Q factor is associated with a low signal loss. Despite the recent engineering progress, there is still a need for methods of manufacturing inductors with increased Q values.
The switch-on and switch-off characteristics of the current in an LR series circuit is given by
respectively, where RL denotes the line resistivity.
Thus, the inductor coil quality is affected by the resistivity of the involved metal lines, typically, Cu lines. It should be noted that the coil quality depends on the resistance of the coil trenches (conductor lines filled in trenches formed in a dielectric material) as well as the number of coil windings (coil density) but not on the k-value of the dielectric wherein the coil is formed.
An inductor fabricated on an integrated circuit substrate generally has been formed in the shape of a spiral coil structure in a single metal layer on an insulation layer using typical integrated circuit fabrication techniques. This spiral coil structure requires a substantial area of the silicon integrated circuit substrate, typically, for example, 200 μm×200 μm. The conventional spiral coil structure also suffers from parasitic capacitive influence from the integrated circuit substrate on which it is fabricated.
Thus, there is particularly a need for the formation of a high Q inductor with reduced spatial dimensions as compared to conventionally Back-End-of-Line (BEOL) manufactured inductors.
In view of the situation described above, the present disclosure provides techniques that allow for the formation of space-saving inductors with high Q values.
The following presents a simplified summary of the invention in order to provide a basic understanding of some aspects of the invention. This summary is not an exhaustive overview of the invention. It is not intended to identify key or critical elements of the invention or to delineate the scope of the invention. Its sole purpose is to present some concepts in a simplified form as a prelude to the more detailed description that is discussed later.
An illustrative method of the formation of a semiconductor device with an inductor includes the steps of forming a first dielectric layer of a first dielectric material over a substrate, removing a part of the first dielectric layer to create an opening in the first dielectric layer, filling the opening with a second dielectric layer of a second dielectric material different from the first dielectric material, forming a trench in the second dielectric layer and filling the trench with a conductive material to form an inductor coil. Herein, by the term “conductive,” it is meant “electrically conductive.” The first dielectric layer may be formed as part of, or on, or over a metallization layer formed over the substrate. The first dielectric layer may be formed on or over a device layer that includes a variety of semiconductor devices, for example, transistor devices and/or resistors and/or capacitors. The device layer may be formed over the substrate or on and partially in the substrate. The formed opening may reach to an underlying metallization layer or device layer. The second dielectric material may be chosen to allow for the formation of deep trenches with small critical dimensions, in particular, smaller than the critical dimensions of trenches used for the formation of inductor coils of the art.
It is further provided a semiconductor device including an inductor, wherein the semiconductor device comprises a first dielectric layer made of a first dielectric material, a second dielectric layer made of a second dielectric material different from the first dielectric material and embedded in the first dielectric layer and a trench filled with a conductive material and formed in the second dielectric layer and representing at least a part of an inductor coil of the inductor.
Furthermore, it is provided a method of forming a semiconductor device including an inductor, including the steps of forming a dielectric layer over or as part of a metallization layer or over a device layer and performing a two-step etching process of the dielectric layer. The two-step etching process includes a first etching step to form a first trench with a first depth in the dielectric layer and a second etching step to form a second trench with a second depth in the dielectric layer and to further etch the first trench to increase the depth of the first trench to a third depth deeper than the second depth. During the second etching step, the second trench is formed and simultaneously the depth of the first trench is increased in one single processing step. After the first trench with the third depth has been formed, a process of filling the first trench with the third depth with a conductive material to form an inductor coil is performed. For example, the conductive material may consist of or comprise copper.
All or some of the above-mentioned dielectric layers may be formed of a low-k material, with a dielectric constant k less than 3, for example.
The disclosure may be understood by reference to the following description taken in conjunction with the accompanying drawings, in which like reference numerals identify like elements, and in which:
While the subject matter disclosed herein is susceptible to various modifications and alternative forms, specific embodiments thereof have been shown by way of example in the drawings and are herein described in detail. It should be understood, however, that the description herein of specific embodiments is not intended to limit the invention to the particular forms disclosed, but on the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the invention as defined by the appended claims.
Various illustrative embodiments of the invention are described below. In the interest of clarity, not all features of an actual implementation are described in this specification. It will of course be appreciated that in the development of any such actual embodiment, numerous implementation-specific decisions must be made to achieve the developers' specific goals, such as compliance with system-related and business-related constraints, which will vary from one implementation to another. Moreover, it will be appreciated that such a development effort might be complex and time-consuming, but would nevertheless be a routine undertaking for those of ordinary skill in the art having the benefit of this disclosure.
The following embodiments are described in sufficient detail to enable those skilled in the art to make use of the invention. It is to be understood that other embodiments would be evident, based on the present disclosure, and that system, structure, process or mechanical changes may be made without departing from the scope of the present disclosure. In the following description, numeral-specific details are given to provide a thorough understanding of the disclosure. However, it will be apparent that the embodiments of the disclosure may be practiced without the specific details. In order to avoid obscuring the present disclosure, some well-known circuits, system configurations, structure configurations and process steps are not disclosed in detail.
The present disclosure will now be described with reference to the attached figures. Various structures, systems and devices are schematically depicted in the drawings for purposes of explanation only and so as to not obscure the present disclosure with details which are well known to those skilled in the art. Nevertheless, the attached drawings are included to describe and explain illustrative examples of the present disclosure. The words and phrases used herein should be understood and interpreted to have a meaning consistent with the understanding of those words and phrases by those skilled in the relevant art. No special definition of a term or phrase, i.e., a definition that is different from the ordinary or customary meaning as understood by those skilled in the art, is intended to be implied by consistent usage of the term or phrase herein. To the extent that a term or phrase is intended to have a special meaning, i.e., a meaning other than that understood by skilled artisans, such a special definition shall be expressively set forth in the specification in a definitional manner that directly and unequivocally provides the special definition for the term or phrase.
The present disclosure provides methods for forming an inductor, in particular, a coil inductor. As will be readily apparent to those skilled in the art upon a complete reading of the present application, the present method is applicable to a variety of technologies, for example, NMOS, PMOS, CMOS, etc., and is readily applicable to a variety of devices, including, but not limited to, logic devices, memory devices, etc., in principle. The techniques and technologies described herein can be utilized to fabricate MOS integrated circuit devices, including NMOS integrated circuit devices, PMOS integrated circuit devices, and CMOS integrated circuit vices. Although the term “MOS” properly refers to a device having a metal gate electrode and an oxide gate insulator, that term is used throughout to refer to any semiconductor device that includes a conductive gate electrode (whether metal or other conductive material) that is positioned over a gate insulator (whether oxide or other insulator) which, in turn, is positioned over a semiconductor substrate. It should be stressed that according to the method of manufacturing a semiconductor device that is described herein, the formation of an inductor, may be integrated within the process flow of manufacturing a plurality of active devices on a wafer, including transistor devices. Exemplary embodiments will now be described with reference to the drawings.
The semiconductor device 100 may comprise a dielectric 2, which may be formed over a metallization layer or represent the dielectric material of a metallization layer (“wiring layer”), or may be any interlayer dielectric (ILD) material and the like. In highly advanced semiconductor devices, the dielectric layer 2 may comprise a low-k dielectric material so as to reduce the parasitic capacitance between neighboring metal lines. In this respect, a low-k dielectric material is to be understood as a dielectric having a relative permittivity (dielectric constant k) that is less than approximately 3.0 and hence exhibits a significantly smaller permittivity than, for instance, well-established “conventional” dielectrics, such as silicon dioxide, silicon nitride and the like. After any well-established process techniques for forming any circuit elements and microstructural elements in and on the substrate 1, the dielectric layer 2 may be formed, which may comprise two or more s layers, depending on device requirements. For example, the dielectric layer 2 may be formed on the basis of well-established plasma enhanced chemical vapor deposition (PECVD) techniques, when comprising silicon dioxide, silicon nitride and the like. However, other deposition techniques may be used, such as spin-on techniques for any low-k polymer materials and the like.
Another layer 3 is formed over the dielectric layer 2. The layer 3 may be a device layer comprising active and/or passive semiconductor devices formed on a substrate or a metallization layer. The layer 3 may be a metallization layer. Above this layer 3, another dielectric layer 4 is formed that may be an (interlayer dielectric) ILD layer. The dielectric layer 4 may also be formed of a low-k material. A planarization process, for example, a chemical mechanical polishing process, may be performed after the deposition of the dielectric layer 4 for obtaining a substantially planar surface. In the chemical mechanical polishing process, the surface of the semiconductor structure 100 is moved relative to a polishing pad while a slurry is supplied to an interface between the surface of the semiconductor structure 100 and the polishing pad. The slurry can react chemically with portions of the semiconductor structure 100 at the surface, and reaction products may be removed by friction between the semiconductor structure 100 and the polishing pad and/or by abrasion caused by abrasive particles in the slurry.
Above the dielectric layer 4, a first mask layer 5 and a second mask layer 6 are formed. The first and second mask layers 5 and 6 may be formed as hard masks. Suitable materials include metals and SiN, for example. The second mask layer 6 may be formed of a material different from the one of the first mask layer 5. The second mask layer 6 is patterned to expose the first mask layer 5 in a first open region (see
A first trench 9 is formed, for example, by anisotropic etching, in the dielectric layer 4 through the first opening 7 of the patterned second mask layer 6, as is shown in
In order to form an inductor, the trench 9′ is filled with some conductive material, for example, copper. Filling the trench 9′ may comprise forming a barrier layer that may be formed by any appropriate deposition technique, such as sputter deposition, chemical vapor deposition, atomic layer deposition and the like. For instance, the barrier layer may be comprised of conductive materials, such as tantalum, tantalum nitride, titanium, titanium nitride, tungsten, tungsten nitride or any other appropriate material, wherein, in some embodiments, two or more different material compositions and layers may be provided, as is required for achieving the desired adhesion and diffusion blocking characteristics. For example, the barrier layer may be deposited on the basis of an electrochemical deposition process so as to form a conductive capping layer in the trench 9′, wherein an appropriate catalyst material may be deposited prior to the actual formation of the harder layer. For instance, palladium may act as a catalyst material for initiating the deposition of the conductive capping layer in an electroless plating process, wherein, after an initial deposition of the material, such as COWP, the subsequent deposition process is auto catalyzed by the previously deposited material.
After the deposition of the barrier layer, a copper seed layer may be deposited by any appropriate deposition technique, such as sputter deposition, electroless deposition and the like, if a copper-based material is to be filled in on the basis of well-established electroplating techniques. In other embodiments, the provision of a seed layer may not be required. Thereafter, a metal material, for example in the form of a copper-containing metal, may be deposited in the trench 9′ on the basis of well-established techniques, such as electroplating, electroless plating and the like.
By the process described with reference to
By the method described with reference to
The coil inductor shown in
Segments of different levels may be connected to each other by means of electrical connections or vias 261 and 262 formed in the dielectric materials. The coil inductor shown in
Another exemplary method of forming an inductor will now be described with reference to
The first and second dielectric layers 303 and 305 may be made of a low-k material. In one example, ILDs including a silicon oxide material and having thicknesses of about 50 nm to about 1 micron, for example a thickness of about 100 nm to about 500 nm, may be provided. According to an example, the ILDs may consist of or comprise an ultralow-k (ULK) material with k of at most 2. The ILDs may be blanket-deposited using, for example, plasma enhanced chemical vapor deposition (PECVD), a low pressure chemical vapor deposition (LPCVD), or a chemical vapor deposition (CVD) process.
However, according to the shown example, parts of the first and second dielectric layer 303 and 305 as well as the second metallization layer 304 are removed (see
The opened area 306 is filled with another dielectric material 307 (
Moreover, the resistance of the trenches may be adjusted by a proper choice of material of the additional dielectric independent of the normal BEOL processing using the dielectric material of dielectric layers 303 and 305. The additional dielectric material 307 may be chosen such that it allows for a proper deposition of a ferromagnetic material into trenches formed in the additional dielectric material 307 thereby significantly increasing, the performance of the finished inductor. The additional dielectric material 307 may be blanket-deposited using, for example, plasma enhanced chemical vapor deposition (PECVD), a low pressure chemical vapor deposition (LPCVD), or a CVD process. The additional dielectric material 307 may comprise or consist of SiCOH with different porosities, carbon doped or fluorine doped silicon dioxide, (organic) polymers, etc.
Due to the properties of the additional dielectric material 307, the trenches 308 are formed deeper than “normal” trench 309. In particular, the trenches 308 of the conductor to be formed may extend beyond the second metallization layer 304. Moreover, the critical dimensions (CDs) at the bottom of the trenches 308 are smaller than the CD of the “normal” trench 309. In the context of the 28 nm technology, examples of values of CDs comprise a nominal minimum trench width of about 50 nm and in the context of the 20 nm technology of about 40 nm.
A higher coil density as compared to the art may be achieved by means of the provision of the additional dielectric material 307 wherein the trenches 308 are formed.
The particular embodiments disclosed above are illustrative only, as the invention may be modified and practiced in different but equivalent manners apparent to those skilled in the art having the benefit of the teachings herein. For example, the process steps set forth above may be performed in a different order. Furthermore, no limitations are intended to the details of construction or design herein shown, other than as described in the claims below. It is, therefore, evident that the particular embodiments disclosed above may be altered or modified and all such variations are considered within the scope and spirit of the invention. Accordingly, the protection sought herein is as set forth in the claims below.
