Kandemin et al., “Improving cache Locality by a Combination of Loop and Data Transformations”, 1999, IEEE, p159-167.* |
Trancoso et al., “Cache Optimization for Memory-Resident Decision Support Commercial Workloads”, 1999, IEEE, p546-554.* |
Carr et al., “Compiler Optimizations for Improving Data Locality”, 1994, ACM, p252-262.* |
McKinley et al., “Improving Data Locality with Loop Transformations”, 1996, ACM, p424-453.* |
IBM, “Executable Program Restructuring for Optimal Cache/Real Memory Utilization”, IBM TDB, vol. 36, issue 12, p153-154, 1993.* |
IBM, “Code Optimization by Hints to the Compiler”, IBM TDB, vol. 40, issue 9, p125-128, 1997.* |
Gupta et al, “Improving Instruction Cache Behvior by Reducing Cache Pollution”, 1990, IEEE, p82-91.* |
Hwu et al., “Achieving High Instruction Cache Performance with an Optimizing Compiler”, 1989 ACM, p242-251.* |
IBM, “Selective Prefetching Based on Miss Latencye” IBM TDB, vol. 36, issue 10, p411-412, 1993.* |
IBM, “Grouping of Instructions”, IBM TDB, vol. 38, issue 8, p531-534, 1995.* |
Holler, A.M.; “Optimization for a Superscalar Out-of-Order Machine,” Proceedings of the 29th Annual IEEE/ACM Int'l. Symposium on Microarchitecture, Micro-29, Paris, Dec. 2-4, 1996; Proceedings of the Annual IEEE/ACM Int'l. Symposium on Microarchitecture (Micro), Los Alamitos, IEEE Comp. Soc. Press, U, vol. SYMP. 29, Dec. 2 1996, pp. 336-348. |
Wolf, M.E. et al.; “Combining Loop Transformations Considering Caches and Scheduling,” Proceedings of the 29th Annual IEEE/ACM Int'l. Symposium on Microarchitecture, Micro-29, Paris, Dec. 2-4, 1996; Proceedings of the Annual IEEE/ACM Int'l. Symposium on Microarchitecture (Micro), Los Alamitos, IEEE Comp. Soc. Press, U, vol. SYMP. 29, Dec. 2 1996, pp. 274-286. |
PCT International Search Report, Sep. 30, 2002, 4 pgs. |