Claims
- 1. A complementary semiconductor device having a high speed operating capability and a high integration density, formed in a semiconductor substrate having a first conductivity type, on which an input/output circuit operatively connectable to an external circuit is formed in a peripheral area thereof, and an inner circuit operatively connected to said input/output circuit is formed in an inner area thereof, said complementary semiconductor device comprising:
- a first well region of a second conductivity type formed in said semiconductor substrate, said first well region having a higher dopant concentration than that of said semiconductor substrate wherein said first conductivity type is opposite to said second conductivity type;
- a second well region of said first conductivity type formed in said substrate, said second well region having a higher dopant concentration than that of said substrate;
- an impurity region of said first conductivity type formed in said substrate, said impurity region having a higher dopant concentration than that of said semiconductor substrate;
- a first conductivity type channel MIS field effect transistor formed in said first well region having a source region, a drain region, and a channel region, all of which are formed in said first well region;
- a second conductivity type channel MIS field effect transistor of a first type formed in said second well region, and having a source region, a drain region and a channel region, all of which are formed in said second well region; and
- a second conductivity type channel MIS field effect transistor of a second type formed in said substrate and having a source region and drain region formed directly in said substrate and a channel region substantially located at said impurity region, wherein said second conductivity type channel MIS field effect transistor of said first type and said first conductivity type channel MIS field effect transistor are disposed in said input/output circuit of said complementary device, and wherein said second conductivity type channel MIS field effect transistor of said second type and said first conductivity type channel MIS field effect transistor are selectively disposed in said inner circuit.
- 2. A complementary semiconductor device having a high speed operating capability and a high integration density, formed in a semiconductor substrate having a first conductivity type, on which an input/output circuit operatively connectable to an external circuit is formed in a peripheral area thereof, and an inner circuit operatively connected to said input/output circuit is formed in an inner area thereof, said complementary semiconductor device, comprising:
- a field insulation layer formed over a surface of said semiconductor substrate for defining transistor regions in which MIS field effect transistors are formed and electrically separating said transistors from each other by surrounding each of said MIS field effect transistor regions;
- a well region of a second conductivity type formed in said semiconductor substrate, said well region having a higher dopant concentration than that of said semiconductor substrate, and extending beneath said field insulation layer, wherein said first conductivity type is opposite to said second conductivity type;
- a first impurity region of said first conductivity type formed in said semiconductor substrate, and extending beneath a part of said field insulation layer, said first impurity region having a higher dopant concentration than that of said substrate including a plurality of empty portions selectively formed in said first impurity region, wherein said first impurity region is absent from said plurality of empty portions;
- a second impurity region of said first conductivity type formed in said substrate, said second impurity region having a higher dopant concentration than that of said semiconductor substrate;
- a first conductivity type channel MIS field effect transistor formed in said well region of said second conductivity type and having a source region, a drain region, and a channel region, all of which are formed in said well region;
- a second conductivity type channel MIS field effect translator of a first type formed in said semiconductor substrate, and having a source region, drain region and channel region which are formed in said first impurity region, wherein at least a portion of each of said drain region and said source region formed in at least one empty portion in said first impurity region to thereby have said portion of each of said drain region and said source region directly contact said semiconductor substrate for increasing switching speed of said second conductivity type channel MIS field effect transistor of a first type;
- a second conductivity type channel MIS field effect transistor of a second type formed in said substrate and having a source region and drain region formed directly in said substrate and a channel region substantially located at said second impurity region to thereby increase switching speed of said second conductivity type channel MIS field effect transistor of a second type, wherein said second conductivity type channel MIS field effect transistor of said first type and said first conductivity type channel MIS field effect transistor are selectively disposed in said input/output circuit, and said second conductivity type channel MIS field effect transistor of said second type and said first conductivity type channel MIS field effect transistor are disposed selectively in said inner circuit.
- 3. A complementary semiconductor device of one of claims 1 or 2, wherein said second conductivity type channel MIS field effect transistor of the second type has a lower junction capacitance than that of said second conductivity type channel MIS field effect transistor of said first type.
- 4. A complementary semiconductor device of one of claims 1 or 2, wherein the MIS field effect transistors include MOS field effect transistors.
- 5. A complementary semiconductor device of claim 2, wherein said plurality of empty - portions are rectangular substantially in plan view.
Priority Claims (1)
Number |
Date |
Country |
Kind |
59-214617 |
Oct 1984 |
JPX |
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Parent Case Info
This application is a continuation of application Ser. No. 178,788 filed Apr. 1, 1988, now abandoned, which is a continuation of application Ser. No. 786,939, filed Oct. 11, 1985, now abandoned.
US Referenced Citations (8)
Foreign Referenced Citations (8)
Number |
Date |
Country |
0091256 |
Oct 1983 |
EPX |
0144248 |
Dec 1985 |
EPX |
0178991 |
Apr 1986 |
EPX |
57-143854 |
Sep 1982 |
JPX |
58-21857 |
Feb 1983 |
JPX |
58-71650 |
Apr 1983 |
JPX |
60-123055 |
Jul 1985 |
JPX |
2104284 |
Mar 1983 |
GBX |
Continuations (2)
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Number |
Date |
Country |
Parent |
178788 |
Apr 1988 |
|
Parent |
786939 |
Oct 1985 |
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