The present invention relates generally to the field of substrate processing equipment. More particularly, the present invention relates to a method and apparatus for controlling the temperature of substrates, such as semiconductor substrates, used in the formation of integrated circuits.
Modern integrated circuits contain millions of individual elements that are formed by patterning the materials, such as silicon, metal and/or dielectric layers, that make up the integrated circuit to sizes that are small fractions of a micrometer. The technique used throughout the industry for forming such patterns is photolithography. A typical photolithography process sequence generally includes depositing one or more uniform photoresist (resist) layers on the surface of a substrate, drying and curing the deposited layers, patterning the substrate by exposing the photoresist layer to electromagnetic radiation that is suitable for modifying the exposed layer and then developing the patterned photoresist layer.
It is common in the semiconductor industry for many of the steps associated with the photolithography process to be performed in a multi-chamber processing system (e.g., a cluster tool) that has the capability to sequentially process semiconductor wafers in a controlled manner. One example of a cluster tool that is used to deposit (i.e., coat) and develop a photoresist material is commonly referred to as a track lithography tool.
Track lithography tools typically include a mainframe that houses multiple chambers (which are sometimes referred to herein as stations) dedicated to performing the various tasks associated with pre- and post-lithography processing. There are typically both wet and dry processing chambers within track lithography tools. Wet chambers include coat and/or develop bowls, while dry chambers include thermal control units that house bake and/or chill plates. Track lithography tools also frequently include one or more pod/cassette mounting devices, such as an industry standard FOUP (front opening unified pod), to receive substrates from and return substrates to the clean room, multiple substrate transfer robots to transfer substrates between the various chambers/stations of the track tool and an interface that allows the tool to be operatively coupled to a lithography exposure tool in order to transfer substrates into the exposure tool and receive substrates from the exposure tool after the substrates are processed within the exposure tool.
Over the years there has been a strong push within the semiconductor industry to increase throughput of wafers in semiconductor processing tools while at the same time increasing yields of semiconductor devices in wafers. The reduced feature sizes have caused the industry's tolerance to shrink, which in turn, has resulted in semiconductor manufacturing specifications having more stringent requirements for process uniformity and repeatability. An important factor in improving the throughput of semiconductor processing tools while at the same time increasing yields across wafers, is the ability to reliably, quickly and consistently achieve and maintain uniform process conditions, such as temperature, across the entire wafer. Those skilled in the art will recognize that processing a wafer when there are temperature differences across the wafer can reduce yields.
Track lithography tools include heaters and chillers which heat or cool wafers to an optimum processing temperature before the wafers are processed. Although sophisticated heater and chiller assemblies are used to heat and cool wafers, they are unable to meet today's stringent requirements for rapid uniform heating and cooling of wafers. Since many heater and chiller assemblies do not provide sufficiently uniform cooling and/or heating of wafers, the throughput of semiconductor processing tools that use heater and chiller assemblies is reduced because a wait time is built into the process to allow the temperature of the wafer to reach equilibrium. The non-uniform heating and cooling of wafers causes either a reduction in throughput because the process must be delayed until temperature uniformity is achieved or a reduction in yields if the wafer is processed before the temperature across the entire wafer is substantially uniform. One cause of the non-uniform heating and cooling is the limitation to how flat the wafer support can be made. Another cause in the non-uniform cooling or heating of the wafer is the variation in the air gap from the heater or chill plate to the wafer.
Therefore what is needed is a system that uniformly heats and cools a wafer, thereby making the heating and cooling process more efficient.
According to the present invention, methods and apparatus related to semiconductor manufacturing equipment are provided. More particularly, embodiments of the present invention relate to a method and apparatus for heating and/or cooling a substrate in a highly controllable manner. Embodiments of the invention contemplate multiple substrates being processed according to the same heating and cooling sequence in a highly controllable manner, thus helping to ensure a consistent wafer temperature for each substrate. While some embodiments of the invention are particularly useful in heating and/or cooling substrates in a chamber or station of a track lithography tool, other embodiments of the invention can be used in other applications where it is desirable to heat and cool substrates in a highly controllable manner.
In an embodiment of the present invention, a system for chilling wafers includes a low thermal mass wafer support for providing support to a bottom surface of a wafer and a chill plate coupled to the low thermal mass wafer support for cooling the wafer. The low thermal mass wafer support has a higher thermal conductivity in the plane parallel to the bottom surface of the wafer than in the direction perpendicular to the bottom surface of the wafer. In one embodiment the thermal conductivity of the low thermal mass wafer support can be ten times greater in the plane parallel to the bottom surface of the wafer than in the direction perpendicular to the bottom surface of the wafer. In another embodiment, the thermal conductivity of the low thermal mass wafer support is one hundred times greater in the plane parallel to the bottom surface of the wafer than in the direction perpendicular to the bottom surface of the wafer.
In another embodiment of the invention, the low thermal mass wafer support is made of a carbon composite.
In yet another embodiment of the invention, the low thermal mass wafer support is a heat pipe containing fluid.
In yet another embodiment of the invention, the low thermal mass wafer support has a thickness of less than 2 mm. In some applications the thickness of the low thermal mass wafer support is less than 1.2 mm.
In yet another embodiment of the invention, the low thermal mass wafer support has a coefficient of thermal expansion that is less than the coefficient of thermal expansion of the wafer.
In another embodiment of the present invention, the low thermal mass wafer support is in intermittent or user selectable direct contact with the chill plate. Alternatively, and in a different embodiment, support pins are used to separate the low thermal mass wafer support from the chill plate. When support pins are used, an exchange gas can also be used to provide a thermal link between the low thermal wafer support and the chill plate.
In an additional embodiment of the present invention, a system for chilling wafers includes a low thermal mass wafer support for providing support to a bottom surface of a wafer and a chill plate coupled to the low thermal mass wafer support for cooling the wafer. The low thermal mass wafer support has a higher thermal conductivity in the plane parallel to the bottom surface of the wafer than in the direction perpendicular to the bottom surface of the wafer, and the low thermal mass wafer support further includes a plurality of proximity pins for supporting the wafer.
In another embodiment of the invention, the proximity pins protrude about 30 to 100 microns above a surface of the low thermal mass wafer support. In other embodiments, the proximity pins protrude about 30 to 70 microns above a surface of the low thermal mass wafer support.
In another embodiment of the present invention, the proximity pins are spheres that are partially embedded in the low thermal mass wafer support. The proximity pins can be hard spheres made out of materials such as sapphire.
In yet another embodiment of the present invention, the proximity pins are uniformly distributed over the surface of the low thermal mass wafer support. The proximity pins can be dispersed randomly throughout the low thermal mass wafer support or according to a fixed pattern such a grid pattern, striped pattern or circular pattern.
In yet another embodiment of the present invention, the plurality of proximity pins is at least three.
In an additional embodiment of the present invention, a system for chilling wafers includes a chill plate for cooling a wafer, a low thermal mass wafer support for supporting the wafer while the wafer is cooled with the chill plate, the low thermal wafer support further comprising at least one resistive element to heat the wafer and to provide an electrostatic force to the wafer during heating, and a bendable support positioned between the low thermal mass wafer support and the chill plate for regulating motion generated by activation of the electrostatic chuck. The low thermal mass wafer support has a higher thermal conductivity in the plane parallel to the bottom surface of the wafer than in the direction perpendicular to the bottom surface of the wafer. The low thermal mass wafer support can further include a plurality of proximity pins for supporting the wafer.
In yet another embodiment of the present invention, an integrated system for baking and chilling wafers includes a heater for heating a wafer to an elevated temperature, a chiller for cooling the wafer, and a shuttle operatively connected to the heater and the chiller for transferring wafers between the heater and the chiller. The chiller further includes a low thermal mass wafer support for providing support to a bottom surface of the wafer and a chill plate coupled to the low thermal mass wafer support for cooling the wafer. The low thermal mass wafer support has a higher thermal conductivity in the plane parallel to the bottom surface of the wafer than in the direction perpendicular to the bottom surface of the wafer. The low thermal mass wafer support can further include a plurality of proximity pins for supporting the wafer.
In another embodiment of the present invention, a system for heating wafers includes a low thermal mass wafer support for providing support to a bottom surface of a wafer and a heat plate coupled to the low thermal mass wafer support for heating the wafer. The low thermal mass wafer support has a higher thermal conductivity in the plane parallel to the bottom surface of the wafer than in the direction perpendicular to the bottom surface of the wafer. In one embodiment the thermal conductivity of the low thermal mass wafer support can be ten times greater in the plane parallel to the bottom surface of the wafer than in the direction perpendicular to the bottom surface of the wafer. In another embodiment, the thermal conductivity of the low thermal mass wafer support is one hundred times greater in the plane parallel to the bottom surface of the wafer than in the direction perpendicular to the bottom surface of the wafer.
In another embodiment of the invention, the low thermal mass wafer support used in the heating system is made of a carbon composite.
In yet another embodiment of the invention, the low thermal mass wafer support used in the heating system is a heat pipe containing fluid.
Another embodiment of the invention includes an integrated system for heating and chilling wafers including a heater for heating a wafer to an elevated temperature, a chiller for cooling the wafer, a shuttle operatively connected to the heater and the chiller for transferring the wafer between the heater and the chiller. The chiller further includes a low thermal mass wafer support for providing support to a bottom surface of a wafer and a chill plate coupled to the low thermal mass wafer support for cooling the wafer. The low thermal mass wafer support has a higher thermal conductivity in the plane parallel to the bottom surface of the wafer than in the direction perpendicular to the bottom surface of the wafer. The low mass wafer support can also include a plurality of proximity pins for supporting the wafer.
Another embodiment of the invention includes an integrated system for heating and chilling wafers including a heater for heating a wafer to an elevated temperature, a chiller for cooling the wafer, a shuttle operatively connected to the heater and the chiller for transferring the wafer between the heater and the chiller. The heater further includes a low thermal mass wafer support for providing support to a bottom surface of a wafer and a heat plate coupled to the low thermal mass wafer support for heating the wafer. The low thermal mass wafer support has a higher thermal conductivity in the plane parallel to the bottom surface of the wafer than in the direction perpendicular to the bottom surface of the wafer. The low mass wafer support can also include a plurality of proximity pins for supporting the wafer.
Still another embodiment of the invention includes an integrated system for heating and chilling wafers including a heater for heating a wafer to an elevated temperature, a chiller for cooling the wafer, a shuttle operatively connected to the heater and the chiller for transferring the wafer between the heater and the chiller. The heater further includes a first low thermal mass wafer support for providing support to a bottom surface of a wafer and a heat plate coupled to the first low thermal mass wafer support for supporting the first low thermal mass wafer support and for heating the wafer. The chiller further includes a second low thermal mass wafer support for providing support to a bottom surface of a wafer and a chill plate coupled to the second low thermal mass wafer support for supporting the second low thermal mass wafer support and for cooling the wafer. Both the first and second low thermal mass wafer supports have a higher thermal conductivity in the plane parallel to the bottom surface of the wafer than in the direction perpendicular to the bottom surface of the wafer. In another embodiment the both the first and second low thermal mass wafer supports further include a plurality of proximity pins for supporting the wafer.
Controlling temperature uniformity across a wafer during semiconductor processing can be very useful in producing uniform properties of devices made on wafers. For example, when cooling or heating a wafer during a semiconductor manufacturing process, it can be advantages if the wafer is uniformly cooled or heated so that all portions of the wafer are processed at nearly the same temperature. The present invention provides a system and method for efficiently, rapidly and uniformly cooling or heating a wafer during semiconductor processing. Although the invention is described in terms of cooling or heating wafers in a track lithography tool, the invention can be implemented in tools which cool or heat a wafer during processing. Further details of the track lithography tool configuration can be found in copending U.S. patent application Ser. No. 11/174,681 filed on Jul. 5, 2005 which is hereby incorporated by reference in its entirety.
The low thermal mass wafer support 110 is constructed so that it has a higher thermal conductivity in the plane parallel to the top wafer surface 130 and bottom wafer surface 135 than in the direction perpendicular to the top wafer surface 130 and bottom wafer surface 135. The thermal conductivity is illustrated by the values QX, QY, and QZ, which represent the thermal conductivity in the x, y, and z directions where the x and y directions define a plane substantially parallel to the top wafer surface 130 and the bottom wafer surface 135, and where the z direction is perpendicular to both the x and y directions as illustrated in
In one embodiment of the invention the low thermal mass wafer support 110 has a thickness of less than 2 mm, and preferably less than 1.2 mm. Additionally, the low thermal mass wafer support 110 is constructed out of materials having high thermal conductivity, extremely low thermal expansion coefficients, high rigidity and toughness. One example of such a material is pyrolytic graphite which has density of 2.18-2.22 cc, a thermal conductivity of 300 W/m-K in the “ab” plane and 3.5 W/m_K in the c direction, a thermal expansion of 0.5×10-6/K in the “ab” plane and 20×10-6 in the c direction. Another example of such a material is carbon composite which is made of a carbon fiber mesh embedded in epoxy. A wafer support made of such a carbon composite with these properties will not warp when subjected to rapid heating or cooling on one side. Additionally, a carbon composite wafer support expands or contracts less than wafers or other materials such as aluminum nitride (AlN), which reduces the possibility of particle formation due to rubbing of two parts.
In another embodiment of the present invention, the low thermal mass wafer support 110 is made of a high thermal conductivity carbon composite. An example of a high thermal conductivity carbon composite is a composite having thermal conductivity such as the carbon composites manufactured by ThermoComposite of Denver, Colo. The thermal conductivity can be as high as six times that of aluminum. The high thermal conductivity of the low mass wafer support reduces the temperature variation across the wafer providing for better wafer temperature control. The low thermal mass wafer support having high thermal conductivity can be used with fewer heater zones because the temperature reaches equilibrium much faster than when a wafer support having a low thermal conductivity is used.
In another embodiment, the low thermal mass wafer support 110 is made of copper coated carbon fiber. The copper coated carbon fibers can be arranged within the low thermal mass wafer support to optimize each of the QX, QY, and QZ thermal conductivity values. In another embodiment the low thermal mass wafer support can be made of heat pipes containing fluid such as those manufactured by HeatLane Technology of Japan. Other embodiments can include heat pipes containing fluid that undergoes phase transitions from solid to liquid, or liquid to gas, or solid to gas. As discussed above, the high thermal conductivity of the low mass wafer support 110 reduces the temperature variation across the wafer 125 providing for better wafer temperature control. The low thermal mass wafer support 110 having high thermal conductivity can be used with fewer heater zones because the temperature reaches an equilibrium much faster than when a wafer support having a low thermal conductivity is used.
Because the low thermal mass wafer support 110 has high strength and rigidity, the proximity pins 115 can be spaced further apart than usual, in accordance with another embodiment of the present invention. The proximity pins are placed further apart then usual, which permits more uniform spacing between the heater/chiller and the wafer. Normally 22 proximity pins are used, but with the low thermal mass wafer support 110, fewer proximity pins can be used. In one embodiment of the present invention the number or proximity pins is less than 22. In another embodiment of the invention, nine (9) proximity pins are used. Moreover by using the proximity pins to separate the low thermal mass wafer support with the back side of the wafer a warped wafer can be made to have uniform thermal contact with the heater or chill plate with minimum chucking voltage.
The proximity pins 115 can be formed by embedding sapphire or similarly hard spheres in the composite during curing. This technique of forming the proximity pins 115 allows the height of the proximity pin 115 to be controlled by the mold used to form the carbon composite low thermal mass wafer support 110. Since only a small percentage of the sapphire balls extend outside of the carbon composite, the sapphire balls are held in place from all directions by the carbon composite. The technique of inserting the sapphire balls into the composite during curing also eliminates the need for a secondary bonding materials which reduces the number of materials needed to make the low thermal mass wafer support 110 and proximity pin 115 combination. Additionally, the stresses on the composite around the proximity pins 115 are low because the fatigue life of carbon composites over the thermal cycling is very long and the thermal expansion coefficient is small.
The electrostatic chuck and heater 330 can be made by depositing a thin layer of metal on the low thermal mass wafer support 330. The thin layer of metal can be deposited onto the low thermal mass wafer support 310 using a variety of techniques including sputtering, chemical vapor deposition, ion beam deposition, and plasma enhanced vapor deposition as well as other techniques known in the art. In one embodiment, the thin layer of metal can be deposited onto a composite, which makes up the low thermal mass wafer support 310, after the composite has been molded. In another embodiment, the low thermal mass wafer support 310 can be made conductive by adding an additive to it such as carbon. Once the low thermal mass wafer support 310 has been made electrically conductive, the wafer 325 can be chucked electrically to the chill plate for faster and more uniform cooling.
Central module 612 generally contains a first central processing rack 622A, a second central processing rack 622B, and a central robot 624. Rear module 614 generally contains first and second rear processing racks 626A, 626B and a back end robot 628. Front end robot 618 is adapted to access processing modules in front end processing racks 620A, 620B; central robot 624 is adapted to access processing modules in front end processing racks 620A, 620B, first central processing rack 622A, second central processing rack 622B and/or rear processing racks 626A, 626B; and back end robot 628 is adapted to access processing modules in the rear processing racks 626A, 626B and in some cases exchange substrates with a stepper/scanner 602.
The stepper/scanner 602, which may be purchased from Canon USA, Inc. of San Jose, Calif., Nikon Precision Inc. of Belmont, Calif., or ASML US, Inc. of Tempe, Ariz., is a lithographic projection apparatus used, for example, in the manufacture of integrated circuits (ICs). The scanner/stepper tool 602 exposes a photosensitive material (resist), deposited on the substrate in the cluster tool, to some form of electromagnetic radiation to generate a circuit pattern corresponding to an individual layer of the integrated circuit (IC) device to be formed on the substrate surface.
Each of the processing racks 620A, 620B; 622A, 622B and 626A, 626B contains multiple processing modules in a vertically stacked arrangement. That is, each of the processing racks may contain multiple stacked integrated thermal units 605, multiple stacked coater modules 632, multiple stacked coater/developer modules with shared dispense 634 or other modules that are adapted to perform the various processing steps required of a track photolithography tool. As examples, coater modules 632 may deposit a bottom antireflective coating (BARC); coater/developer modules 634 may be used to deposit and/or develop photoresist layers and integrated thermal units 605 may perform bake and chill operations associated with hardening BARC and/or photoresist layers.
In one embodiment, a system controller 640 is used to control all of the components and processes performed in the cluster tool 600. The controller 640 is generally adapted to communicate with the stepper/scanner 602, monitor and control aspects of the processes performed in the cluster tool 600, and is adapted to control all aspects of the complete substrate processing sequence. In some instances, controller 640 works in conjunction with other controllers, such as controllers not shown, which control the heater 607 and chiller 608 of integrated thermal unit 605, to control certain aspects of the processing sequence. In one embodiment of the invention, the heater 607 and chillers 608 described above with reference to
It is to be understood that embodiments of the invention are not limited to use with a track lithography tool such as that depicted in
This aspect of the invention is illustrated in
Maintaining such a height difference in the positions of bake plate 810 and chill plate 815 helps minimize thermal cross-talk between the two stations and helps ensure a highly controlled, repeatable thermal treatment among multiple wafers.
Another aspect of the present invention that helps ensure an extremely high degree of uniformity in the thermal treatment of each wafer is the design of shuttle 710. As shown in
The coolant is delivered to passages 845 by tubes that connect to inlets/outlets 910, which in turn connect to a manifold (not shown) within portion 915 of shuttle 710 that helps distribute the fluid evenly throughout the shuttle. The fluid tubes are at least partially supported by fingers 920 of tube support mechanism 925 as shuttle 710 traverses the length of the integrated thermal unit. Actively cooling wafer receiving surface 905 helps maintain precise thermal control of wafer temperature during all times while the wafer is within thermal unit 605. Actively cooling shuttle 710 also starts the wafer cooling process sooner than it would otherwise be initiated if such active cooling did not occur until the wafer is transferred to a dedicated chill station, which in turn reduces the overall thermal budget of the wafer.
Also shown in
Proximity pins 940 are distributed across upper surface 905 of shuttle 710 and are fabricated from a material with a low coefficient of friction, such as sapphire. Proximity pins 940 allow the wafer being transported by shuttle 710 to be brought into very close proximity of temperature controlled surface 905. The small space between the wafer and temperature controlled surface 905 helps create uniform cooling across the entire surface area of the wafer while at the same time minimizing contact between the underside of the wafer and the shuttle thus reducing the likelihood that particles or contaminants may be generated from such contact. Further details of proximity pins 940 are set forth in U.S. application Ser. No. 11/111,155, entitled “Purged Vacuum Chuck with Proximity Pins” filed on Apr. 20, 2005, which is hereby incorporated by reference for all purposes. In one particular embodiment shuttle 710 includes four pocket buttons 935 and seventeen proximity pins 940.
Shuttle 710 also includes an elongated U-shaped support bracket 945 that allows the shuttle to be mounted to a support plate 950 shown in
Referring now to
Also not shown in
Reference is now made to
Bake plate 810 is operatively coupled to a motorized lift 1425 so that the bake plate can be raised into a clam shell enclosure 720 and lowered into a wafer receiving position. Typically, wafers are heated on bake plate 810 when it is raised to a baking position as shown in
Although the low thermal mass wafer support 110 is not shown in
During the baking process, a faceplate 1430 shown in
Gas from radially inward gas flow 1435 is initially introduced into heater 607 at an annular gas manifold 1245 that encircles the outer portion of top heat plate 1215 by a gas inlet line 1255. Gas manifold 1245 includes numerous small gas inlets 1250 (128 inlets in one embodiment) that allow gas to flow from manifold 1245 into the cavity 1445 between the lower surface of top heat plate 1215 and the upper surface of faceplate 1430. The gas flows radially inward towards the center of the station through a diffusion plate 1310 that includes a plurality of gas outlet holes 1315. After flowing through diffusion plate 1310, gas exits heater 607 through gas outlet line 1260.
An aspect of the invention that helps minimize any delay associated with switching from one thermal recipe to another thermal recipe an thus helps ensure high wafer throughput through integrated thermal unit 605 is discussed below with respect to
As previously mentioned, bake plate 810 heats a wafer according to a particular thermal recipe. One component of the thermal recipe is typically a set point temperature at which the bake plate is set to heat the wafer. During the baking process, the temperature of the wafer is routinely measured and one or more zones of the bake plate can be adjusted to ensure uniform heating of the substrate. Typically bake plate is heated to the desired set point temperature while a large batch of wafers is processed according to the same thermal recipe. Thus, for example, if a particular thermal recipe calls for a set point temperature of 175° C. and that recipe is to be implemented on 100 consecutive wafers, bake plate 810 will be heated to 175° C. during the length of time it takes to process the 100 consecutive wafers. If, however, a subsequent batch of 200 wafers is to be processed according to a different thermal recipe that, for example, requires a set point temperature of 130° C., the set point temperature of bake plate 810 needs to be rapidly changed from 175° C. to 130° C. between processing the 100th and 101st wafers.
Embodiments of the present invention enable a rapid reduction in the set point temperature of bake plate 810 by lowering the bake plate with motor 850 into a lower cooling position that is below the wafer receiving position. In the cooling position a bottom surface 1610 of the bake plate contacts an upper surface 1615 of each heat sink 1510. Contact between the heat sinks and bake plate is possible because bottom cup 1235 includes a plurality of holes 1515 that correspond to the plurality of heat sinks 1510 allowing the heat sinks to extend through bottom cup 1235 to contact bake plate 810.
When bake plate 810 is lowered into the cooling position, spring 1640 causes heat sink 1510 to press upon lower surface of 1610 of the bake plate. The combined thermal mass of all heat sinks 1510 allows bake plate 810 to be rapidly cooled from one set point temperature to a lower set point temperature as may be required, for example, when transitioning to a new thermal recipe. Since the support surface 830 of bake plate 810 is connected to the low thermal mass wafer support 110, any wafer resting on the low thermal mass wafer support 110 will also cool rapidly when the heat sink is engaged.
While heat sink 1510 shown in
In order to better appreciate and understand the general operation of integrated thermal unit 605, reference is now made to
As shown in
At heater 607, the wafer is placed on lift pins and shuttle 710 is free to handle another task or return to its home position at shuttle station (
After completion of bake step 1755, the bake plate 810 is lowered to its wafer receiving position dropping the wafer off on lift pins (
The wafer is then cooled on chill plate 715 according to a predetermined thermal recipe (
Embodiments of the invention allow a process such as that described above to be carried out in a highly controllable and highly repeatable manner. Thus, embodiments of the invention help ensure an extremely high degree of uniformity in the thermal treatment of each wafer that is processed within integrated thermal unit 10 according to a particular thermal recipe. As discussed in more detail below, a number of specific aspects of the present invention can be used independent from each other or in combination to help achieve such a repeatable, uniform wafer history.
One such aspect is the placement of hot plate 810 with respect to chill plate 715. Specifically, in some embodiments of the invention hot plate 810 is positioned within integrated thermal unit 605 at a position that is higher than the position of chill plate 715. Because heat generated from bake plate 810 generally rises to an upper portion of thermal unit 605, such positioning helps minimize thermal cross-talk between the heater 607 and chiller 608 that may otherwise lead to discrepancies in the thermal treatment of wafers over time.
In step 1810, a semiconductor substrate is transferred to a coat module. Referring to
The BARC coat step 1812 is a step used to deposit an organic material over a surface of the substrate. The BARC layer is typically an organic coating that is applied onto the substrate prior to the photoresist layer to absorb light that otherwise would be reflected from the surface of the substrate back into the resist during the exposure step 1826 performed in the stepper/scanner 602. If these reflections are not prevented, standing waves will be established in the resist layer, which cause feature size to vary from one location to another depending on the local thickness of the resist layer. The BARC layer may also be used to level (or planarize) the substrate surface topography, which is generally present after completing multiple electronic device fabrication steps. The BARC material fills around and over the features to create a flatter surface for photoresist application and reduces local variations in resist thickness.
BARC coat step 1812 is typically performed using a conventional spin-on resist dispense process in which an amount of the BARC material is deposited on the surface of the substrate while the substrate is being rotated which causes a solvent in the BARC material to evaporate and thus causes the material properties of the deposited BARC material to change. The air flow and exhaust flow rate in the BARC processing chamber is often controlled to control the solvent vaporization process and the properties of the layer formed on the substrate surface.
Post BARC bake step 1814, is a step used to assure that all of the solvent is removed from the deposited BARC layer in BARC coat step 1812, and in some cases to promote adhesion of the BARC layer to the surface of the substrate. The temperature of post BARC bake step 1814 is dependent on the type of BARC material deposited on the surface of the substrate, but will generally be less than about 250° C. The time required to complete post BARC bake step 1814 will depend on the temperature of the substrate during the post BARC bake step, but will generally be less than about 60 seconds.
Post BARC chill step 1816, is a step used to control and assure that the time the substrate is above ambient temperature is consistent so that every substrate sees the same time-temperature profile and thus process variability is minimized. Variations in the BARC process time-temperature profile, which is a component of a substrates wafer history, can have an effect on the properties of the deposited film layer and thus is often controlled to minimize process variability. Post BARC chill step 1816, is typically used to cool the substrate after post BARC bake step 1814 to a temperature at or near ambient temperature. The time required to complete post BARC chill step 1816 will depend on the temperature of the substrate exiting the post BARC bake step, but will generally be less than about 30 seconds.
Photoresist coat step 1818, is a step used to deposit a photoresist layer over a surface of the substrate. The photoresist layer deposited during the photoresist coat step 1818 is typically a light sensitive organic coating that is applied onto the substrate and is later exposed in the stepper/scanner 602 to form the patterned features on the surface of the substrate. Photoresist coat step 1818 is a typically performed using conventional spin-on resist dispense process in which an amount of the photoresist material is deposited on the surface of the substrate while the substrate is being rotated which causes a solvent in the photoresist material to evaporate and thus causes the material properties of the deposited photoresist layer to change. The air flow and exhaust flow rate in the photoresist processing chamber is controlled to control the solvent vaporization process and the properties of the layer formed on the substrate surface. In some cases it may be necessary to control the partial pressure of the solvent over the substrate surface to control the vaporization of the solvent from the resist during the photoresist coat step by controlling the exhaust flow rate and/or by injecting a solvent near the substrate surface. Referring to
Photoresist bake step 1820, is a step used to assure that all of the solvent is removed from the deposited photoresist layer in photoresist coat step 1818, and in some cases to promote adhesion of the photoresist layer to the BARC layer. The temperature of post photoresist bake step 1820 is dependent on the type of photoresist material deposited on the surface of the substrate, but will generally be less than about 350° C. The time required to complete post photoresist bake step 1820 will depend on the temperature of the substrate during the post photoresist bake step, but will generally be less than about 60 seconds.
Post photoresist chill step 1822 is a step used to control the time the substrate is at a temperature above ambient temperature so that every substrate sees the same time-temperature profile and thus process variability is minimized. Variations in the time-temperature profile can have an effect on properties of the deposited film layer and thus is often controlled to minimize process variability. The temperature of post photoresist chill step 1822 is thus used to cool the substrate after post photoresist bake step 1820 to a temperature at or near ambient temperature. The time required to complete post photoresist chill step 1822 will depend on the temperature of the substrate exiting the post photoresist bake step, but will generally be less than about 30 seconds.
Optical edge bead removal (OEBR) step 1824, is a process used to expose the deposited light sensitive photoresist layer(s), such as, the layers formed during photoresist coat step 1818 and the BARC layer formed during BARC coat step 1812, to a radiation source (not shown) so that either or both layers can be removed from the edge of the substrate and the edge exclusion of the deposited layers can be more uniformly controlled. The wavelength and intensity of the radiation used to expose the surface of the substrate will depend on the type of BARC and photoresist layers deposited on the surface of the substrate. An OEBR tool can be purchased, for example, from USHIO America, Inc. Cypress, Calif.
Exposure step 1826 is a lithographic projection step applied by a lithographic projection apparatus (e.g., stepper scanner 602) to form a pattern which is used to manufacture integrated circuits (ICs). The exposure step 1826 forms a circuit pattern corresponding to an individual layer of the integrated circuit (IC) device on the substrate surface, by exposing the photosensitive materials, such as, the photoresist layer formed during photoresist coat step 1818 and the BARC layer formed during the BARC coat step 1812 of some form of electromagnetic radiation.
Post exposure bake (PEB) step 1828 is a step used to heat a substrate immediately after exposure step 1826 in order to stimulate diffusion of the photoactive compound(s) and reduce the effects of standing waves in the resist layer. For a chemically amplified resist, the PEB step also causes a catalyzed chemical reaction that changes the solubility of the resist. The control of the temperature during the PEB is typically critical to critical dimension (CD) control. The temperature of PEB step 1828 is dependent on the type of photoresist material deposited on the surface of the substrate, but will generally be less than about 250° C. The time required to complete PEB step 1828 will depend on the temperature of the substrate during the PEB step, but will generally be less than about 60 seconds.
Post exposure bake (PEB) chill step 1830 is a step used to control the assure that the time the substrate is at a temperature above ambient temperature is controlled so that every substrate sees the same time-temperature profile and thus process variability is minimized. Variations in the PEB process time-temperature profile can have an effect on properties of the deposited film layer and thus is often controlled to minimize process variability. The temperature of PEB chill step 1830 is thus used to cool the substrate after PEB step 1828 to a temperature at or near ambient temperature. The time required to complete PEB chill step 1830 will depend on the temperature of the substrate exiting the PEB step, but will generally be less than about 30 seconds.
Develop step 1832 is a process in which a solvent is used to cause a chemical or physical change to the exposed or unexposed photoresist and BARC layers to expose the pattern formed during exposure process step 1826. The develop process may be a spray or immersion or puddle type process that is used to dispense the developer solvent. In some develop processes, the substrate is coated with a fluid layer, typically deionized water, prior to application of the developer solution and spun during the development process. Subsequent application of the developer solution results in uniform coating of the developer on the substrate surface. In step 1834, a rinse solution is provided to surface of the substrate, terminating the develop process. Merely by way of example, the rinse solution may be deionized water. In alternative embodiments, a rinse solution of deionized water combined with a surfactant is provided. One of ordinary skill in the art would recognize many variations, modifications, and alternatives.
In step 1836 the substrate is cooled after the develop and rinse steps 1832 and 1834. In step 1838, the substrate is transferred to the pod, thus completing the processing sequence. Transferring the substrate to the pod in step 1838 generally entails the process of having the front end robot 618 return the substrate to a cassette 630 resting in one of the pod assemblies 616.
Based on the description of the present invention herein, a person of skill in the art will appreciate that embodiments of the invention may be beneficially used to heat and/or cool a substrate during, among other steps not described in
While the present invention has been described with respect to particular embodiments and specific examples thereof, it should be understood that other embodiments may fall within the spirit and scope of the invention. The scope of the invention should, therefore, be determined with reference to the appended claims along with their full scope of equivalents.