COMPUTATION OF ELECTRICAL PROPERTIES OF AN IC LAYOUT

Abstract

A system for calculating electrical properties of features to be created in an integrated circuit. All or a portion of a desired layout design is corrected for photolithographic or other process distortions using one or more resolution enhancement techniques. A simulated layout image of a corrected layout is used as an input to a field solver program that calculates the electrical properties of the features as they will be printed on a wafer.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

The foregoing aspects and many of the attendant advantages of this invention will become more readily appreciated as the same become better understood by reference to the following detailed description, when taken in conjunction with the accompanying drawings, wherein:

FIG. 1 illustrates a conventional process for determining electrical properties of features in an integrated circuit design;

FIG. 2 illustrates a process for determining electrical properties of features in an integrated circuit design in accordance with one embodiment of the present invention;

FIG. 3 illustrates a desired layout pattern and a simulated layout image of the desired layout pattern;

FIG. 4 illustrates a hierarchical organization of a layout design and corresponding sets of polygons defining features in various layers of an integrated circuit; and

FIG. 5 illustrates a representative computer system for implementing the present invention.

Claims

1. A method for computing electrical properties of features in an integrated circuit layout design, comprising: receiving a target layout design defining features to be created in an integrated circuit or portion thereof;producing a corrected layout including one or more of the features that are compensated for photolithographic process distortions with one or more resolution enhancement techniques;simulating how the features in the corrected layout will be formed on a wafer; andusing the simulation of how the features in the corrected layout will be formed on the wafer as an input to a field solver to compute the electrical properties of the features.

2. The method of claim 1, wherein the features in the simulated layout image are defined as polygons and the electrical properties of the features are computed by applying the polygons of the simulated layout image to a finite element field solver.

3. The method of claim 1, wherein the one or more resolution enhancement techniques include an optical and process correction (OPC) tool.

4. The method of claim 1, wherein the electrical properties of the features in the corrected layout are stored in a netlist.

5. The method of claim 1, further comprising computing electrical properties for uncorrected features in the target layout design and combining the electrical properties of the uncorrected features with the electrical properties of the features defined by the corrected layout.

6. A computer-readable media including a sequence of instructions that are executable by the computer to perform the method of any of claims 1-5.

7. A system for computing electrical properties of features in an integrated circuit layout design, comprising: a computer that executes a sequence of programmed instructions that causes the computer to: receive a target layout design defining features to be created in an integrated circuit or portion thereof;produce a corrected layout including features that are compensated for photolithographic process distortions using one or more resolution enhancement techniques;simulate how the features in the corrected layout will be formed on a wafer; anduse the results of the simulation of how the features will be formed on the wafer as an input to a field solver to compute the electrical properties of the features in the integrated circuit.