Patent Application
20060048088
This application is based upon and claims the benefit of priority from the prior Japanese Patent Applications No. P2004-244069, filed on Aug. 24, 2004; the entire contents of which are incorporated herein by reference.
1. Field of the Invention
The present invention relates to a layout design methodology for a semiconductor integrated circuit, more specifically to a layout design methodology for wiring processes.
2. Description of the Related Art
In the field of layout design of semiconductor integrated circuits, a maze routing is known as a method of obtaining a wiring path between two points. The maze routing is a wiring path finding method configured to set a grid (lattice) on a plane subject to wiring, and to find a path for connecting between two rectangular areas which are divided by the grid. Even when there is an obstacle such as an existing line, the maze routing can find a wiring path to bypass such an obstacle. The maze routing is widely used for detailed routing after global routing, and the like.
In the field of manufacturing semiconductor integrated circuits, along with increasing demands for downsizing and higher integration, it has become more difficult to form wiring shapes for connecting between elements in accordance with the original design. For example, as the wiring is downsized, a phenomenon that a line does not reach a position of a via for connecting upper and lower wiring layers (shortening), and the like are apt to occur more frequently. Accordingly, faulty connection and an increase in resistance of vias are incurred and product yields are thereby reduced.
To prevent a reduction in yields attributable to defective vias, a method of replacing one via (a single cut via) for connecting lines with a plurality of vias (multiple cut vias) has been proposed. However, the method generally used today is applied as a post process after designing the wiring. Accordingly, it is not taken into consideration in the method that are placement with multiple cut vias can be made in the course of designing the wiring. Therefore, there are numerous areas in which the single cut vias cannot be replaced with the multiple cut vias due to the design, and it is not possible to improve the rate of replacement with the multiple cut vias.
An aspect of the present invention inheres in a computer automated design method encompassing: defining rectangular areas serving as a starting point area and an ending point area of a wiring, the rectangular areas being selected from wiring areas assigned in a plurality of layers, each of layers being divided into a plurality of areas by a lattice; accumulating wiring costs by adding respective wiring cost whenever an exploration of a wiring path from the starting point area to the ending point area advances one rectangular area, multiplying the wiring cost by a via cost, when a multiple cut via is provided between the wiring areas assigned in two of the layers in the plurality of layers, and adding an obstacle cost based on obstacle information to a result of multiplication of the via cost; finding a final wiring path routing through a plurality of wiring areas in the two of layers based on a value obtained by accumulating the wiring costs to connect the starting point area and the ending point area; and arranging corresponding multiple cut via in the final wiring path connecting areas in the two of layers.
Another aspect of the present invention inheres in a program configured to be executed by a computer for executing an application on a computer automated design system, comprising: defining rectangular areas serving as a starting point area and an ending point area of a wiring, the rectangular areas being selected from wiring areas assigned in a plurality of layers, each of layers being divided into a plurality of areas by a lattice; accumulating wiring costs by adding respective wiring cost whenever an exploration of a wiring path from the starting point area to the ending point area advances one rectangular area, multiplying the wiring cost by a via cost, when a multiple cut via is provided between the wiring areas assigned in two of the layers in the plurality of layers, and adding an obstacle cost based on obstacle information to a result of multiplication of the via cost; finding a final wiring path routing through a plurality of wiring areas in the two of layers based on a value obtained by accumulating the wiring costs to connect the starting point area and the ending point area; and arranging the corresponding multiple cut via in the final wiring path connecting areas in the two of layers.
Still another aspect of the present invention inheres in a semiconductor integrated circuit manufactured by using a computer automated design method, the method comprising: defining rectangular areas serving as a starting point area and an ending point area of a wiring, the rectangular areas being selected from wiring areas assigned in a plurality of layers, each of layers being divided into a plurality of areas by a lattice; accumulating wiring costs by adding respective wiring cost whenever an exploration of a wiring path from the starting point area to the ending point area advances one rectangular area, multiplying the wiring cost by a via cost, when a multiple cut via is provided between the wiring areas assigned in two of the layers in the plurality of layers, and adding an obstacle cost based on obstacle information to a result of multiplication of the via cost; finding a final wiring path routing through a plurality of wiring areas in the two of layers based on a value obtained by accumulating the wiring costs to connect the starting point area and the ending point area; and arranging the corresponding multiple cut via in the final wiring path connecting areas in the two of layers.
Various embodiments of the present invention will be described with reference to the accompanying drawings. It is to be noted that the same or similar reference numerals are applied to the same or similar parts and elements throughout the drawings, and the description of the same or similar parts and elements will be omitted or simplified. In the following descriptions, numerous details are set forth such as specific signal values, etc. to provide a thorough understanding of the present invention. However, it will be obvious to those skilled in the art that the present invention may be practiced without such specific details.
As shown in
The CPU 1a automatically provides lines in a plurality of layers and vias for connecting between the lines onto a chip area of a semiconductor integrated circuit which is located virtually inside a memory space of the computer automated design system. The CPU 1a shown in
As shown in
The wiring cost addition unit 121 adds a wiring cost at each time of advancing one rectangular area through the exploration of the wiring path between the two rectangular areas. The via cost multiplication unit 122 multiplies the wiring cost by a via cost for providing a plurality of vias in any of different layers, when an exploration is performed in the different layers. The obstacle cost addition unit 123 adds an obstacle cost based on information on an obstacle located around the rectangular area subject to exploration, when the exploration is performed in the different layers. The counting unit 124 counts up the costs calculated by the wiring cost addition unit 121, the via cost multiplication unit 122, and the obstacle cost addition unit 123.
For example, in terms of the layouts shown in
Wiring cost for advancing one rectangular area in a horizontal direction in a wiring area in a first layer: 1
Wiring cost for advancing one rectangular area in a vertical direction in the wiring area in the first layer: 4
Wiring cost for advancing one rectangular area in a horizontal direction in a wiring area in a second layer: 4
Wiring cost for advancing one rectangular in a vertical direction in the wiring area in the second layer: 1
Wiring cost for advancing one rectangular area to a wiring area in a different layer: 2
Via cost for arranging multiple cut vias: 2
Obstacle cost for an obstacle O existing in any of rectangular areas adjacent to four sides defining a rectangular area subject to exploration: 1 Here the “horizontal direction” indicates the right-to-left direction in the page spaces of
As shown in
An exploration to advance one rectangular area in the upper direction from the rectangular area (B-2-1) to the rectangular area (A-2-1) corresponds to the “wiring cost for advancing one rectangular area in the vertical direction in the wiring area in the first layer”. For this reason, the wiring cost addition unit 121 adds the wiring cost “4” for the rectangular area (A-2-1). The exploration from the rectangular area (B-2-1) to the rectangular area (A-2-1) is not an exploration to a different layer. Here, no obstacles O such as an existing line exist around the rectangular area (A-2-1). For this reason, the obstacle cost addition unit 123 does not add the obstacle cost for the rectangular area (A-2-1). As a result, the counting unit 124 counts a value of the cost “4”, which is obtained by adding the wiring cost “4” to the cost “0” of the starting point area S, and stores the information on “4” in the area of the rectangular area (A-2-1) as shown in
A case of performing an exploration to advance one rectangular area in the direction of an upper layer from the rectangular area (B-2-1) to the rectangular area (B-2-2) corresponds to the “wiring cost for advancing one rectangular area to a wiring area in a different layer”. For this reason, the wiring cost addition unit 121 adds the wiring cost “2” for the rectangular area (B-2-2). The exploration from the rectangular area (B-2-1) to the rectangular area (B-2-2) is an exploration to a different layer, and it is therefore necessary to form a via. The via cost multiplication unit 122 multiplies the wiring cost “2” by the cost value “2” as the via cost for disposing a multiple cut via and thereby calculates the value “4”. Consequently, the counting unit 124 sets, as a counting result, a cost value “4”, which is obtained by adding the multiplication result “4” found by the via cost multiplication unit 122 to the cost “0” of the starting point area S, and stores the information on “4” as shown in
The connection unit 130 of
The data storage unit 2a of
In
Next, a computer automated design method according to the first embodiment will be described in detail with reference to flowcharts shown in
(a) In Step S100 of
(b) In Step S200, a path finding process for the wiring is performed in accordance with the maze routing. In Step S201, the costs of all the lattice areas divided by the grid are initialized to “0”. As shown in
(c) In Step S205 the path finding unit 110 of
(d) In Step S209, the path finding unit 110 selects one direction of the exploration (an exploration area P) to be started from the origin area M. In
As shown in
(e) In Step S213, the wiring cost calculation unit 121 calculates the wiring cost based on the information stored in the wiring cost storage unit 21. As shown in
(f) In Step S217, the cost calculation unit 120 judges whether or not the exploration area P is unexplored. The process goes to Step S221 when the exploration area P is unexplored, and the process goes to Step S219 when the exploration area P is not unexplored. Since the rectangular area (B-3-1) is unexplored at this point, the process goes to Step S221. In Step S221, the counting unit 124 counts up the wiring cost of the exploration area P and the like stored in the program storage unit 2m, adds a counting result to the cost of the origin area M, and stores the added value in the rectangular area list storage unit 25. The cost of the rectangular area (B-3-1) is equal to “1” which is obtained by adding the wiring cost “1” the obstacle cost “0”, and the value “0” of the starting point area S together. For this reason, as shown in
(g) In Step S223, the path finding unit 110 judges whether or not there is an unexplored direction from the origin area M. The process goes to Step S209 when there is an unexplored direction, and the process goes to Step S205 when there is not an unexplored direction. Since the rectangular area (B-3-1) is the only area which has been explored as the exploration area P at this point, the process goes to Step S209. In Step S209, the path finding unit 110 selects another direction of the exploration (the exploration area P) to be started from the origin area M. Here, the path finding unit 110 is assumed to select the rectangular area (B-2-2) in the direction of the upper layer as the direction of the exploration from the rectangular area (B-2-1). In Step S211, the cost calculation unit 120 judges whether or not the exploration area P is located in the upper layer or the lower layer. Since the rectangular area (B-2-2) corresponds to an exploration in the direction of the upper layer, the process goes to Step S215.
(h) In Step S215, the wiring cost calculation unit 121 calculates the cost based on the information stored in the wiring cost storage unit 21. Since the rectangular area (B-2-2) incurs the “wiring cost for advancing one rectangular area to a different layer” from the viewpoint of the rectangular area (B-2-1), the wiring cost addition unit 121 adds the cost “2” and stores the cost in the program memory 2m. Subsequently, the via cost multiplication unit 122 multiplies the value, which is added by the wiring cost addition unit 121, by the via cost based on the information stored in the via cost storage unit 22. Here, the via cost stored in the via cost storage unit 22 is equal to “2”. Accordingly, the via cost multiplication unit 122 multiplies the value “2” added by the wiring cost addition unit 121 by the via cost “2”, and stores the information on the cost “4” in the program storage unit 2m. Moreover, the obstacle cost addition unit 123 adds the obstacle cost existing around the exploration area P based on the information stored in the obstacle cost storage unit 23. Here, since there exists no obstacle around the exploration area P, the obstacle cost is equal to “0”. The obstacle cost addition unit 123 stores the information “0” in the program memory 2m.
(i) In Step S217, the cost calculation unit 120 judges whether or not the exploration area P is unexplored. Since the rectangular area (B-2-2) is unexplored, the process goes to Step S221. In Step S221, the counting un it 124 counts each cost of the exploration area P calculated by the cost calculation unit 120 to the cost of the origin area M, and stores the added value in the rectangular area list storage unit 25. Here, the cost of the rectangular area (B-2-2) stored in the rectangular area list storage unit 25 is equal to ”4”, which is obtained by adding the value “0” of the starting point area S, the value “4” found by multiplying the wiring cost by the via cost, and the obstacle cost “0”0 together. As shown in
(j) In Step S223, the path finding unit 110 judges whether or not there is an unexplored direction from the origin area M. Since the rectangular area (B-3-1) and the rectangular area (B-2-2) are the only areas explored as the exploration areas P at this point and there exist unexplored directions, the process goes to Step S209. Likewise, each of the Steps S209 to S223 is repeated, and the costs of all the rectangular areas around the origin area M are stored in the rectangular area list storage unit 25.
(k) When a judgment is made in Step P223 that all the exploration areas P have been explored, the process goes to Step S205 and the path finding unit 110 explores a new origin area M. In the example shown in
(l) In Step S207, the path finding unit 110 judges whether or not the origin area M coincides with the ending point area E. Since the rectangular area (B-3-1) of the origin area M is different from the rectangular area (E-6-1) of the ending point area E, the process goes to Step S209. In Step S209, the path finding unit 110 selects one direction of the exploration to be started from the origin area M, and thereby determines the exploration area P. Here, the left direction will be selected as the exploration area P. As a result, the rectangular area (B-2-1) becomes the exploration area. In Step S211, the cost calculation unit 120 judges whether or not the exploration area P is located in the upper or lower layer direction. Since the rectangular area (B-2-1) does not correspond to the exploration in the upper or lower layer direction, the process goes to Step S213.
(m) In Step S213, the wiring cost calculation unit 121 calculates the cost based on the information stored in the wiring cost storage unit 21. Since the rectangular area (B-2-1) incurs the “wiring cost for advancing one rectangular area in the horizontal direction in a wiring area in a first layer”, the wiring cost addition unit 121 adds the cost “1” and stores the cost in the program memory 2m.
(n) In Step S217, the cost calculation unit 120 judges whether or not the exploration area P is unexplored. Since the rectangular area (B-2-1) is not unexplored, the process goes to Step S219. In Step S219, the counting unit 124 counts up the costs of the exploration area P calculated by the cost calculation unit 120, and judges whether or not the newly calculated cost is greater than the cost of the exploration area P, which was calculated in the previous exploration. Here, the cost of the rectangular area (B-2-1) as the exploration area P is equal to “2”, which is obtained by adding the wiring cost “1” to the value “1” of the origin area M. Meanwhile, a relation in size between the cost of the exploration area calculated in the previous exploration and the cost of the exploration area calculated in the recent exploration is expressed as 2>0, and the cost of the exploration area calculated in the recent exploration is greater. Accordingly, the process goes to Step S223.
(o) As shown in
A method of calculating the costs by use of the computer automated design method according to the first embodiment will be described with reference to a schematic diagram shown in
Meanwhile, when the obstacles (existing lines) O exist in an area C and an area I among areas C, D, E, and F, which are adjacent to the area A, and areas G, H, I, and J, which are adjacent to the area B, the cost of the area B is calculated as a higher value by adding the cost of the area C and area I as an obstacle cost for performing an exploration from the area A to the area B. By calculating the cost of the area congested with the lines as a high value, the vias are less likely to be arranged in the area congested with the lines. Accordingly, it is possible to arrange the vias in the area in which the lines are not congested, and thereby to increase the replacement rate of the multiple cut vias. By increasing the replacement rate of the multiple cut vias, it is possible to suppress a reduction in yields attributable to defective vias. In this way, it is also possible to provide semiconductor integrated circuits in high yields. In the example shown in
The series of automated design processes shown in the flowcharts of
(a) storing a rectangular area serving as a starting point area S of a wiring and storing a rectangular area serving as an ending point area E of the wiring in the rectangular area list storage unit 25, the rectangular areas being selected from wiring areas in a plurality of layers each divided into a plurality of areas by a lattice;
(b) adding a wiring cost whenever an exploration of a wiring path from the starting point area to the ending point area advances one rectangular area by the wiring cost addition unit 121;
(c) multiplying the wiring cost by a via cost to provide a multiple cut via in any of the wiring areas in the plurality of layers by the via cost multiplication unit 122;
(d) adding an obstacle cost based on obstacle information to a result of multiplication of the via cost by the obstacle cost addition unit 123;
(e) counting up the cost calculated by the wiring cost addition unit 121, the via cost multiplication unit 122, and the obstacle cost addition unit 123 and storing count up result in the the rectangular area list storage unit 25 by the counting unit 124:
(f) finding the wiring path in the wiring areas in the plurality of layers based on the count up result by the path finding unit 110;
(g) connecting the starting point area and the ending point area by the connection unit 124; and
(h) arranging the multiple cut via in any of the wiring areas in the plurality of layers by the via arrangement unit 140.
It is also possible to execute the series of automated design processes of the automated design according to the first embodiment by saving an automated design program of the first embodiment in a computer-readable recording medium and causing the program memory 2m to read this recording medium. The “computer-readable recording medium” indicates any medium such as an external memory device of a computer, a semiconductor memory, a magnetic disk, an optical disk, a magneto-optical disk, or a magnetic tape which can record a program, for example. To be more precise, the “computer-readable recording medium” includes a flexible disk, a CD-ROM, an MO disk, and the like. For example, a main body of a computer system may be configured to incorporate or externally connect a flexible disk device (a flexible disk drive) or an optical disk device (an optical disk drive). By inserting a flexible disk from an inlet of the flexible disk drive or a CD-ROM from an inlet of the optical disk drive, and performing a given reading operation, it is possible to install the program stored in these media into the program memory 2m constituting the computer system. Moreover, it is possible to store this program in the program memory 2m through an information processing network such as the Internet.
The semiconductor integrated circuit shown in
As shown in
As shown in
As shown in
As shown in
A CPU 1b includes a path finding unit 110, a cost calculation unit 120, a connection unit 130, a via arrangement unit 140, a chip area division unit 151, a congestion degree calculation unit 152, and a congestion degree judgment unit 153.
As shown in
A data memory 2b includes a wiring cost storage unit 21, a via cost storage unit 22, an obstacle cost storage unit 23, an obstacle list storage unit 24, a rectangular area list storage unit 25, and the congestion degree list storage unit 26. The congestion degree list storage unit 26 stores the information on the congestion degrees of the lines calculated by the congestion degree calculation unit 152. Since other features are substantially similar to those in the first embodiment, a description thereof will be omitted.
Next, a computer automated design method according to the second embodiment will be described with reference to FIGS. 14 to 19B.
(a) In Step S100 of
(b) In Step S110, the computer automated design system of
(c) The congestion degree calculation unit 152 selects one of the wiring areas r out of the chip area shown in
(d) In Step S150, the congestion degree judgment unit 153 judges whether or not the congestion degree of the wiring area r calculated by the congestion degree calculation unit 152 is equal to or below a reference value stored in advance in the data memory 2b and the like. The process goes to Step S200 when the congestion degree of the wiring area r is equal to or below the reference value, and the process goes to Step S250 when the congestion degree exceeds the reference value. For example, the reference value is assumed to be preset to 1.0 in the example of
(e) In Step S200, a path finding process of the detailed routing is carried out. Since Step S200 is substantially similar to the mode shown in
—Second Path Finding Process (Details of Step S250)—
Next, a second path finding process shown in Step S250 will be described. Step S250 is different from the routing method shown in Step S200 in which a finding method not in consideration of replacement with multiple cut vias is used as the wiring path finding method in accordance with the maze routing. Since other features are substantially similar to Step S200, a detailed description thereof will be omitted.
(a) In Step S250a of
(b) In Step S250c, the path finding unit 110 of
(c) In Step S250e, the path finding unit 110 selects one direction of the exploration (an exploration area P) to be started from the origin area M. In
(d) In Step S250g, the cost calculation unit 120 judges whether or not the exploration area P is unexplored. The process goes to Step S250i when the exploration area P is unexplored, and the process goes to Step S250h when the exploration area P is not unexplored. In Step S250h, the counting unit 124 counts up the costs of the exploration area P calculated by the cost calculation unit 120, and judges whether or not the newly calculated cost is greater than the cost of the exploration area P, which was calculated in the previous exploration. The process goes to Step S250i when the newly calculated cost is smaller than the cost of the exploration area which was calculated in the previous exploration, and the process goes to Step S250j when the exploration area P is greater than the cost of the exploration area which was calculated in the previous exploration.
Here, since the rectangular area (B-3-1) is unexplored, the process goes to Step S250i. In Step S250i, a counting unit 124 adds the wiring cost and the like of the exploration area P and the like stored in the program memory 2n to the cost of the origin area M, and stores the added value in the rectangular area list storage unit 25. Here, the cost of the rectangular area (B-3-1) is equal to “1”, which is obtained by adding the wiring cost “1” to the value “0” of the starting point area S. As shown in
(e) In Step S250j, the path finding unit 110 judges whether or not there is an unexplored direction from the origin area M. The process goes to Step S250d when there is an unexplored direction, and the process goes to Step S250c when there is not an unexplored direction. Since the rectangular area (B-3-1) is the only area explored as the exploration area Pat this point, the process goes to Step S250d. Thereafter, in Step S250e, the path finding unit 110 selects another direction of the exploration (the exploration area P) to be started from the origin area M. Here, the path finding unit 110 is assumed to select the rectangular area (B-2-2) in the direction of the upper layer as the direction of the exploration from the rectangular area (B-2-1).
(g) In Step S250f, the cost calculation unit 120 calculates the wiring cost of the exploration area P based on the cost information stored in the data memory 2b. Since the rectangular area (B-2-2) of the exploration area P incurs the “wiring cost for advancing one rectangular area to a different layer”, the wiring cost addition unit 121 adds the cost “2” and stores the cost in the program memory 2n and the like.
(h) In Step S250g, the cost calculation unit 120 judges whether or not the exploration area P is unexplored. Since the rectangular area (B-2-2) is unexplored, the process goes to Step S250i. In Step S250i, the counting unit 124 adds the cost of the exploration area P calculated by the cost calculation unit 120 to the cost of the origin area M, and stores the added value in the rectangular area list storage unit 25. Here, the cost of the rectangular area (B-2-2) to be stored in the program memory 2n is equal to “2”, which is obtained by adding the wiring cost “2” to the value “0“ of the starting point area S. As shown in
(i) In Step S250j, the path finding unit 110 judges whether or not there is an unexplored direction from the origin area M. Since the rectangular area (B-3-1) and the rectangular area (B-2-2) are the only areas explored as the exploration areas P at this point, there are still unexplored direction. Accordingly, the process goes to Step S250d. Likewise, each of the Steps S250d to S250j is repeated, and the process goes to Step S250c when there are no more unexplored directions. In this way, it is possible to obtain cost information as shown in
The mode described in Step S200 in the first embodiment requires more wiring resources as compared to the case of using the general maze routing, since the path in consideration of replacement with the multiple cut vias is to be found. Accordingly, it is difficult to design the wiring in consideration of replacement with the multiple cut vias in an area having a large congestion degree of wiring. Therefore, in the second embodiment, the wiring path finding process f (Step S200) considering replacement with the multiple cut vias is used for an area having a low congestion degree of wiring, while the second wiring path finding process (Step S250) considering replacement with the single cut vias is selectively used for an area having a high congestion degree of wiring. In this way, it is possible to improve a replacement rate of the multiple cut vias without sacrificing wiring possibilities. As a reduction in yields attributable to defective vias is suppressed by increasing the replacement rate of the multiple cut vias, it is possible to provide semiconductor integrated circuits in higher yields.
The series of computer automated design processes shown in the flowcharts of
(a) dividing a chip area into the plurality of wiring areas r by the chip area division unit
(b) calculating a congestion degree of lines in a specific wiring area r among the plurality of wiring areas r by the congestion degree calculation unit 152;
(c) judging whether or not the path finding process for arranging multiple via cuts is processed to the specific wiring area r, based on the result of calculating the congestion degree of lines in the specific wiring area r by the congestion degree judgment unit 153;
(d) storing a rectangular area serving as a starting point area of a wiring and storing a rectangular area serving as an ending point area of the wiring in the rectangular area list storage unit 25,
(e) adding a wiring cost whenever an exploration of a wiring path from the starting point area to the ending point area advances one rectangular area by the wiring cost addition unit 121;
(f) multiplying the wiring cost by a via cost to provide a multiple cut via in any of the wiring areas in the plurality of layers by the via cost multiplication unit 122;
(g) adding an obstacle cost based on obstacle information to a result of multiplication of the via cost by the obstacle cost addition unit 123
(h) counting up the cost calculated by the wiring cost addition unit 121, the via cost multiplication unit 122, and the obstacle cost addition unit 123 and storing count up result in the the rectangular area list storage unit 25 by the counting unit 124
(i) finding the wiring path in the wiring areas in the plurality of layers based on the count up result by the path finding unit 110;
(j) connecting the starting point area and the ending point area by the connection unit 124; and
(k) arranging the multiple cut via in any of the wiring areas in the plurality of layers by the via arrangement unit 140.
It is also possible to execute the series of automated design processes of the automated design according to the first embodiment by saving an automated design program of the first embodiment in a computer-readable recording medium and causing the program memory 2n to read this recording medium. The “computer-readable recording medium” means any medium described in the first embodiment of the present invention.
As shown in
As shown in
The data memory 2c includes a wiring cost storage unit 21, a via cost storage unit 22, an obstacle cost storage unit 23, an obstacle list storage unit 24, a rectangular area list storage unit 25, and the replacement rate list storage unit 27. The replacement rate list storage unit 27 stores the information on the replacement rates of each small area s calculated by the replacement rate calculation unit 161. Other features are substantially similar to those in the first or second embodiment.
Next, a computer automated design method according to the third embodiment will be described with reference to FIGS. 21 to 24.
(a) In Step S100 of
(b) In Step S501, the small area division unit 160 of
(c) The replacement rate calculation unit 161 selects a specific small area s out of the wiring area r in Step S502, and calculates the replacement rate of the multiple cut vias concerning the small area s in Step S503. The method of calculating the replacement rate in Step S503 is not particularly limited. Information on a result of calculation of the replacement rate is stored in a space for the specific small area s in the replacement rate list storage unit 27 as shown in
(d) In Step S505, the rewiring unit 162 reads the information on the replacement rate stored in the replacement rate list storage unit 27, and judges whether or not the replacement rate of the small area s falls below the reference value. The process goes to Step S507 when the replacement rate falls below the reference value, and the process goes to Step S510 when the replacement rate does not fall below the reference value.
(e) In Step S507, when the replacement rate falls below the reference value, the rewiring unit 162 peels off the lines in the specific small area s and other small areas s around the specific small area s. In the example of
According to the computer automated design method according to the third embodiment, as shown in
The series of automated design processes shown in the flowcharts of
(a) storing a rectangular area serving as a starting point area S of a wiring and storing a rectangular area serving as an ending point area E of the wiring in the rectangular area list storage unit 25, the rectangular areas being selected from wiring areas in a plurality of layers each divided into a plurality of areas by a lattice;
(b) adding a wiring cost whenever an exploration of a wiring path from the starting point area to the ending point area advances one rectangular area by the wiring cost addition unit 121;
(c) multiplying the wiring cost by a via cost to provide a multiple cut via in any of the wiring areas in the plurality of layers by the via cost multiplication unit 122;
(d) adding an obstacle cost based on obstacle information to a result of multiplication of the via cost by the obstacle cost addition unit 123;
(e) counting up the cost calculated by the wiring cost addition unit 121, the via cost multiplication unit 122, and the obstacle cost addition unit 123 and storing count up result in the the rectangular area list storage unit 25 by the counting unit 124:
(f) finding the wiring path in the wiring areas in the plurality of layers based on the count up result by the path finding unit 110;
(g) connecting the starting point area and the ending point area by the connection unit 124; and
(h) arranging the multiple cut via in any of the wiring areas in the plurality of layers by the via arrangement unit 140.
(i) dividing the wiring area into a plurality of small areas by the small area division unit 160;
(j) calculating a replacement rate of the multiple cut via in terms of a specific small area among the plurality of small areas and storing a result of calculation of the replacement rate in the replacement rate list storage unit 27; and
(k) comparing the result of calculation with a reference value, peeling off lines in the specific small area and in other small areas around the specific small area, and rewiring lines when the result of calculation falls below the reference value.
It is also possible to execute the series of automated design processes of the automated design according to the first embodiment by saving an automated design program of the first embodiment in a computer-readable recording medium and causing the program memory 20 to read this recording medium.
Various modifications will become possible for those skilled in the art after receiving the teachings of the present disclosure without departing from the scope thereof.
| Number | Date | Country | Kind |
|---|---|---|---|
| P2004-244069 | Aug 2004 | JP | national |
