Patent Application
20120030639
1. Technical Field
Embodiments of the present disclosure relates to circuit simulating systems and methods, and more particularly, to a computing device and a method for checking signal transmission lines of a circuit board.
2. Description of Related Art
A circuit board may be arranged with thousands of signal transmission lines. To ensure integrity of signals transmitted by the signal transmission lines, designs of the signal transmission lines should satisfy design standards. For example, a length of each line segment of a signal transmission line should satisfy a predetermined standard, so that each line segment of the signal transmission line has an appropriate impedance to ensure signal integrity. Spaces between neighboring signal transmission lines should also satisfy predetermined standards, to reduce crosstalk of the neighboring signal transmission lines. Therefore, it is necessary to incorporate design simulations and checks during the design and layout process of the circuit board. However, presently, obtaining information from a circuit board layout are often acquired manually. With the large quantity of signal transmission lines distributed on the circuit board, manual operation is not only time-consuming, but also error-prone.
The disclosure, including the accompanying drawings in which like references indicate similar elements, is illustrated by way of examples and not by way of limitation. It should be noted that references to “an” or “one” embodiment in this disclosure are not necessarily to the same embodiment, and such references mean at least one.
In general, the word “module,” as used hereinafter, refers to logic embodied in hardware or firmware, or to a collection of software instructions, written in a programming language, such as, for example, Java, C, or Assembly. One or more software instructions in the modules may be embedded in firmware. It will be appreciated that modules may comprised connected logic units, such as gates and flip-flops, and may comprise programmable units, such as programmable gate arrays or processors. The modules described herein may be implemented as either software and/or hardware modules and may be stored in any type of computer-readable medium or other computer storage device.
The display 15 displays the circuit board layout file 11 and a user interface allowing selection of signal transmission lines to be checked and output check results. Depending on the embodiment, the storage device 13 may be a smart media card, a secure digital card, or a compact flash card. The computing device 10 may be a personal computer, or a server, for example.
The file reading module 121 reads the circuit board layout file 11 from the storage device 13. In one embodiment, the circuit board layout file 11 includes design information of the signal transmission lines of the circuit board 10, such as the number of the signal transmission lines arranged on the circuit board 10, a length of each signal transmission line, and orientation of each signal transmission line. It is understood that a signal transmission line may include a number of line segments. For example, as shown in
The line selection module 122 receives one or more signal transmission lines selected by a user from the circuit board layout file 11. It is understood that the user can select one signal transmission line at one time, or select more than one signal transmission lines having the same design standards at one time. For example, in one embodiment, data line 1, data line 2, and data line 3 in
The design standard obtaining module 123 obtains design standards of the selected signal transmission lines from the storage device 13. In one embodiment, the design standards include a reference length of each line segment of a selected signal transmission line, and a reference distance between each line segment of the selected signal transmission line and a corresponding line segment of each neighboring signal transmission line. For example, in
The information check module 124 computes an actual length of each line segment of the selected signal transmission line, and computes an actual distance between each line segment of the selected signal transmission line and a corresponding line segment of each neighboring signal transmission line. For example, in one embodiment, actual lengths of the five line segments of data line 1 (e.g., a1, b1, c1, d1, f1) is “150 mil, 80 mil, 75 mil, 100 mil, 200 mil,” actual lengths of the five line segments of data line 2 (e.g., a2, b2, c2, d2, f2) is “150 mil, 80 mil, 90 mil, 100 mil, 200 mil,” and actual lengths of the five line segments of data line 3 (e.g., a3, b3, c3, d3, f3) is “150 mil, 80 mil, 73 mil, 100 mil, 200 mil.” Furthermore, actual distances between each line segment of data line 2 and a corresponding line segment of data line 1 may be “4 mil, 6 mil, 8 mil, 10 mil, 9 mil,” and actual distances between each line segment of data line 2 and a corresponding line segment of data line 3 may be “4 mil, 6 mil, 7.5 mil, 10 mil, 9 mil.”
Furthermore, the information check module 124 checks if each actual length is less than or equal to the reference length of the line segment, and checks if each actual distance is more than or equal to a corresponding reference distance. If each actual length is less than or equal to a corresponding reference length, and each actual distance is more than or equal to a corresponding reference distance, the information check module 124 determines a design of the selected signal transmission line satisfies the design standards. Otherwise, if any actual length is more than a reference length, or if any actual distance is less than a corresponding reference distance, the information check module 124 determines the design of the signal transmission line does not satisfy the design standards.
For example, as mentioned above, reference lengths of the five line segments of each data line (e.g., data line 1, data line 2, or data line 3) in
The error prompt module 125 highlights the selected signal transmission lines which do not satisfy the design standards and displays unsatisfied reasons. For example, the error prompt module 125 may highlight data line 2 and data line 3 in the circuit board layout file 11 and displays unsatisfied reasons, such as the actual length of the third line segment of data line 2 is too long, and the actual distance between the third line segment of data line 2 and which the third line segment of data line 3 is too short.
In block S301, the file reading module 121 reads the circuit board layout file 11 from the storage device 13. As mentioned above, the circuit board layout file 11 includes arrangement information of the signal transmission lines of the circuit board 20, such as the number of the signal transmission lines arranged on the circuit board 20, a length of each signal transmission line, and orientation of each signal transmission line.
In block S303, the line selection module 122 receives a signal transmission line selected by a user from the circuit board layout file 11. For example, in one embodiment, data line 2 shown in
In block S305, the design standard obtaining module 123 obtains design standards of the selected signal transmission line from the storage device 13. As mentioned above, the design standards include a reference length of each line segment of the selected signal transmission line, and a reference distance between each line segment of the selected signal transmission line and a corresponding line segment of each neighboring signal transmission line. For example, in
In block S307, the information check module 124 computes an actual length of each line segment of the selected signal transmission line, and computes an actual distance between each line segment of the selected signal transmission line and a corresponding line segment of each neighboring signal transmission line. For example, as mentioned above, actual lengths of the five line segments of data line 2 is “150 mil, 80 mil, 90 mil, 100 mil, 200 mil.” Furthermore, actual distances between each line segment of data line 2 and a corresponding line segment of data line 1 is “4 mil, 6 mil, 8 mil, 10 mil, 9 mil,” and actual distances between each line segment of data line 2 and a corresponding line segment of data line 3 is “4 mil, 6 mil, 7.5 mil, 10 mil, 9 mil.”
In block S309, the information check module 124 checks if each actual length of the line segments of the selected signal transmission line is less than or equal to a corresponding reference length, and checks if each actual distance is more than or equal to a corresponding reference distance. If each actual length is less than or equal to a corresponding reference length, and each actual distance is more than or equal to a corresponding reference distance, the procedure goes to block S311, the information check module 124 determines a design of the selected signal transmission line satisfies the design standards. Then, the procedure goes to block S315.
Otherwise, if any actual length of the line segments of the selected signal transmission line is more than a reference length, or if any actual distance is less than a corresponding reference distance, the procedure goes to block S313 the information check module 124 determines the design of the signal transmission line does not satisfy the design standards. Then, the procedure goes to block S315.
In block S315, the error prompt module 125 highlights the selected signal transmission line in the circuit board layout file 11 and displays unsatisfied reasons. For example, the error prompt module 125 may highlight data line 2 in the circuit board layout file 11 and displays unsatisfied reasons, such as that the third line segment of data line 2 is too long, and the actual distance between the third line segment of data line 2 and the third line segment of data line 3 is too short.
In block S317, the information check module 124 checks if there is any signal transmission line that has not been selected in the circuit board layout file 11. If there is any signal transmission line that has not been selected in the circuit board layout file 11, the procedure returns to block S303. Otherwise, if all signal transmission lines in the circuit board layout file 11 have been selected, the procedure ends.
Although certain inventive embodiments of the present disclosure have been specifically described, the present disclosure is not to be construed as being limited thereto. Various changes or modifications may be made to the present disclosure without departing from the scope and spirit of the present disclosure.
| Number | Date | Country | Kind |
|---|---|---|---|
| 201010240215.2 | Jul 2010 | CN | national |
