Patent Application
20130006561
1. Technical Field
Embodiments of the present disclosure relate to printed circuit board (PCB) analysis systems and methods, and particularly to a computing device, a storage medium, and a method for analyzing a signal group delay of data signal lines and clock signal lines included in a PCB.
2. Description of Related Art
Electronic apparatuses utilize high frequency clock signals in order to achieve high processing speeds and multifunctional abilities. In design of a printed circuit board (PCB) for an electronic apparatus, length of a clock signal line should be equal to length of a data signal line corresponding to the clock signal line. In order to evaluate a signal delay between the data signal line and the clock signal line, a designer conventionally performs a timing analysis to examine whether the signal delay satisfies PCB design specifications. If the signal delay fails to satisfy the PCB design specifications, the designer determines that the layout design of the data line and the clock signal line should be redesigned in the PCB.
However, it is difficult to make sure that the length of each clock signal line equals to the length the data signal line during the design of a PCB, and such design error may result in signal delay failing to satisfy the PCB design specifications. Therefore, there is need for a system and method for analyzing a signal group delay between the data signal lines and clock signal lines, to make sure that a layout of the PCB satisfies the PCB design specifications.
The present disclosure, including the accompanying drawings, is illustrated by way of examples and not by way of limitation. It should be noted that references to “an” or “one” embodiment in this disclosure are not necessarily to the same embodiment, and such references mean at least one.
In the present disclosure, the word “module,” as used herein, refers to logic embodied in hardware or firmware, or to a collection of software instructions, written in a program language. In one embodiment, the program language may be Java, C, or assembly. One or more software instructions in the modules may be embedded in firmware, such as an EPROM. The modules described herein may be implemented as either software and/or hardware modules and may be stored in any type of non-transitory computer-readable medium or other storage device. Some non-limiting examples of non-transitory computer-readable medium include CDs, DVDs, flash memory, and hard disk drives.
In one embodiment, the signal measuring device 2 may be an oscilloscope that is used to measure a plurality of S-parameters from a pair of data signal lines and clock signal lines of a printed circuit board (PCB). In one embodiment, the PCB may be a motherboard of a computer or a passive circuit board of an electronic apparatus, such as a game machine or a household appliance. The PCB may include a plurality of data signal lines (e.g., two data signal lines) and a plurality of clock signal lines (e.g., two clock signal lines). Each of the data signal lines is used to transmit data from one component (e.g., a memory) to another component (e.g., a CPU) installed in the PCB, and each of the clock signal lines is used to transmit a clock signal for controlling the data transmission on different components of the PCB. Each of the S-parameters is a signal parameter representing an electrical frequency of the signal, such as an incident voltage parameter and a reflective voltage parameter.
The signal group delay analysis system 10 analyzes a signal delay of each of the data signal lines and the clock signal lines included in the PCB, and verifies whether a length of the data signal line is equal to a length of the clock signal line. In one embodiment, the signal delay is defined as a time difference between a data transmission time of the data signal line and a clock transmission time of the clock signal line.
In one embodiment, the signal group delay analysis system 10 includes an S-parameter matrix creating module 101, an S-parameter analysis module 102, a signal delay calculation module 103, and a signal delay analysis module 104. The modules 101-104 may comprise computerized instructions in the form of one or more programs that are stored in the storage system 12 and executed by the at least one processor 11. A detailed description of each module will be given in the following paragraphs.
In block S21, the S-parameter matrix creating module 101 obtains a plurality of S-parameters from a pair of data signal lines and clock signal lines measured by the signal measuring device 2, and creates a S-parameter matrix according to the S-parameters. In one embodiment, each of the S-parameters is a signal parameter representing an electrical frequency, such as an incident voltage parameter and a reflective voltage parameter. The S-parameter matrix is created using a circuit simulation tool, such as a SPICE program or a HSPICE program.
In block S22, the S-parameter analysis module 102 defines a port connection between each of the data signal lines and a clock signal line corresponding to the data signal line according to the S-parameters. In one embodiment, the S-parameter analysis module 102 may define the port connection as a standard timing connection if the S-parameters of the data signal line are identical to the S-parameters of the clock signal line. The standard timing connection is defined as a correct port relationship between a data signal line and a clock signal line corresponding to the data signal line. Referring to
In block S23, the S-parameter analysis module 102 analyzes a differential loss coefficient of the data signal line and the clock signal line based on the S-parameter matrix. In one embodiment, the differential loss coefficient is defined as a voltage input loss of the clock signal line when data is transmitted on the data signal line, and can be represented by the voltage loss “SDD11”, “SDD12”, “SDD21” and “SDD22” according to the S-parameter matrix. The S-parameter analysis module 102 defines the voltage loss “SDD21” as the differential loss coefficient of the data signal line and the clock signal line according to the port connection between the data signal line and the clock signal line.
In block S24, the signal delay calculation module 103 calculates a first signal delay of the data signal line according to a data transmission frequency of the data signal line and the differential loss coefficient. In one embodiment, the data transmission frequency of the data signal line may be denoted as “ω1”, and the differential loss coefficient is the voltage loss “SDD21” that is a complex number, which can be extracted as a phase value φ(ω1). The signal delay calculation module 103 calculates a first signal delay τ1(ω) of the data signal line using a first differential formula τ1(ω)=−τ1(ω)/δω1.
In block S25, the signal delay calculation module 103 calculates a second signal delay of the clock signal line according to a clock frequency of the clock signal line and the differential loss coefficient. In one embodiment, the data transmission frequency of the data signal line may be denoted as “ω2”, and the differential loss coefficient is the voltage loss “SDD21” that is a complex number, which can be extracted as a phrase value φ(ω2). The signal delay calculation module 103 calculates a second signal delay τ2(ω) of the clock signal line using a second differential formula τ2(ω)=−δτ2(ω)/δω21.
In block S26, the signal delay analysis module 104 analyzes a signal group delay of the data signal line and the clock signal line according to the first signal delay and the second signal delay. In one embodiment, the signal delay analysis module 104 calculates a time difference between the first signal delay and the second signal delay to obtain signal group delay of the data signal line and the clock signal line. The time difference is an absolute value of the first signal delay and the second signal delay, and is calculated according to the equation: TD=|τ1(ω)−τ2(ω)|.
In block S27, the signal delay analysis module 104 determines whether the signal group delay satisfies a PCB design specification. In one embodiment, the PCB design specification may define a timing restriction of the clock signal line included in the PCB, and the timing restriction is defined as 6 mil per second, for example. If the signal group delay does not satisfy the PCB design specification, block S28 is implemented. Otherwise, if the signal group delay satisfies the PCB design specification, the flow is ended.
In block S28, the signal delay analysis module 104 displays the signal group delay of the data signal line and the clock signal line on the display device 3 for showing a designer to design the data signal line and the clock signal line on the PCB. Thus, the designer can arrange the layout of the PCB according to the data signal line and the clock signal line.
All of the processes described above may be embodied in, and fully automated via, functional code modules executed by one or more general purpose processors of computing devices. The code modules may be stored in any type of non-transitory readable medium or other storage device. Some or all of the methods may alternatively be embodied in specialized hardware. Depending on the embodiment, the non-transitory readable medium may be a hard disk drive, a compact disc, a digital video disc, a tape drive or other suitable storage medium.
Although certain disclosed embodiments of the present disclosure have been specifically described, the present disclosure is not to be construed as being limited thereto. Various changes or modifications may be made to the present disclosure without departing from the scope and spirit of the present disclosure.
| Number | Date | Country | Kind |
|---|---|---|---|
| 100122554 | Jun 2011 | TW | national |
