This application is a divisional application of commonly assigned co-pending U.S. Pat. No. 6,051,992, invented by Steven P. Young, Shekhar Bapat, Kamal Chaudhary, Trevor J. Bauer, and Roman Iwanczuk entitled "CONFIGURABLE LOGIC ELEMENT WITH ABILITY TO EVALUATE FIVE AND SIX INPUT FUNCTIONS" filed Apr. 1, 1999 and issued Apr. 18, 2000, which is a divisional application of commonly assigned U.S. Pat. No. 5,920,202, invented by Steven P. Young, Shekhar Bapat, Kamal Chaudhary, Trevor J. Bauer, and Roman Iwanczuk entitled "CONFIGURABLE LOGIC ELEMENT WITH ABILITY TO EVALUATE FIVE AND SIX INPUT FUNCTIONS", filed Apr. 4, 1997 and issued Jul. 6, 1999, which is a continuation-in-part of commonly assigned U.S. Pat. No. 5,914,616 invented by Steven P. Young, Kamal Chaudhary, and Trevor J. Bauer entitled "FPGA REPEATABLE INTERCONNECT STRUCTURE WITH HIERARCHICAL INTERCONNECT LINES" and filed Feb. 26, 1997, all of which are incorporated herein by reference. This application further relates to the following commonly assigned co-pending U.S. patent application Ser. No. 08/786,818 invented by Kenneth D. Chapman and Steven P. Young, entitled "CONFIGURABLE LOGIC BLOCK WITH AND GATE FOR EFFICIENT MULTIPLICATION IN FPGAs" and filed Jan. 21, 1997, which is incorporated herein by reference.
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Number | Date | Country | |
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Parent | 283472 | Apr 1999 | |
Parent | 835088 | Apr 1997 |
Number | Date | Country | |
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Parent | 806997 | Feb 1997 |