the logic functions being realised by the interconnection of rows and columns

Industry

CPC
H03K19/17704

This industry / category may be too specific. Please go to a parent level for more data

Parent Industries

HELECTRICITY H03Electronic circuits H03KPULSE TECHNIQUE H03K19/00Logic circuits

Current Industry

H03K19/17704the logic functions being realised by the interconnection of rows and columns

Industries

Please log in for detailed analytics

Patents Grantslast 30 patents

Information Patent Grant
Power-up switch-interconnect configuration
- Patent number 12,119,819
- Issue date Oct 15, 2024
- Flex Logix Technologies, Inc.
- Robert I-Che Fu
- G11 - INFORMATION STORAGE
Information Patent Grant
3D stacked integrated circuits having failure management
- Patent number 12,074,599
- Issue date Aug 27, 2024
- Micron Technology, Inc.
- Tony M. Brewer
- G11 - INFORMATION STORAGE
Information Patent Grant
Fabric die to fabric die interconnect for modularized integrated ci...
- Patent number 12,009,298
- Issue date Jun 11, 2024
- Intel Corporation
- Chee Hak Teh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Logic cell structure and integrated circuit with the logic cell str...
- Patent number 11,855,632
- Issue date Dec 26, 2023
- Taiwan Semiconductor Manufacturing Company Ltd.
- Shao-Huan Wang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and apparatus for reordering signals
- Patent number 11,782,715
- Issue date Oct 10, 2023
- SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
- Michael Alvin Rencher
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Low power interconnect using resonant drive circuitry
- Patent number 11,784,648
- Issue date Oct 10, 2023
- Power Down Semiconductor, Inc.
- David A Huffman
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Fabric die to fabric die interconnect for modularized integrated ci...
- Patent number 11,670,589
- Issue date Jun 6, 2023
- Intel Corporation
- Chee Hak Teh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
High-speed core interconnect for multi-die programmable logic devices
- Patent number 11,621,713
- Issue date Apr 4, 2023
- Intel Corporation
- Lai Guan Tang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Vertical field-effect transistor (VFET) devices including latches h...
- Patent number 11,282,957
- Issue date Mar 22, 2022
- Samsung Electronics Co., Ltd.
- Jung Ho Do
- G11 - INFORMATION STORAGE
Information Patent Grant
High-speed core interconnect for multi-die programmable logic devices
- Patent number 11,128,301
- Issue date Sep 21, 2021
- Intel Corporation
- Lai Guan Tang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Coarse-grain programmable routing network for logic devices
- Patent number 11,121,715
- Issue date Sep 14, 2021
- Intel Corporation
- Gary Wallichs
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
3D stacked integrated circuits having failure management
- Patent number 11,043,952
- Issue date Jun 22, 2021
- Micron Technology, Inc.
- Tony M. Brewer
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Reconfigurable circuit and the method for using the same
- Patent number 11,018,671
- Issue date May 25, 2021
- NEC Corporation
- Xu Bai
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Fabric die to fabric die interconnect for modularized integrated ci...
- Patent number 10,886,218
- Issue date Jan 5, 2021
- Intel Corporation
- Chee Hak Teh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
High performance QR decomposition systems and methods
- Patent number 10,872,130
- Issue date Dec 22, 2020
- Intel Corporation
- Martin Langhammer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Logic cell structure and integrated circuit with the logic cell str...
- Patent number 10,868,538
- Issue date Dec 15, 2020
- Taiwan Semiconductor Manufacturing Company Ltd.
- Shao-Huan Wang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System level interconnect with programmable switching
- Patent number 10,826,499
- Issue date Nov 3, 2020
- Cypress Semiconductor Corporation
- Bert Sullam
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Data interpolation
- Patent number 10,817,493
- Issue date Oct 27, 2020
- Raytheon Company
- James R. Sackett
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
High-speed core interconnect for multi-die programmable logic devices
- Patent number 10,666,261
- Issue date May 26, 2020
- Intel Corporation
- Lai Guan Tang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
3D stacked integrated circuits having failure management
- Patent number 10,666,264
- Issue date May 26, 2020
- Micron Technology, Inc.
- Tony M. Brewer
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Test apparatus for semiconductor device and method of manufacturing...
- Patent number 10,591,543
- Issue date Mar 17, 2020
- Samsung Electronics Co., Ltd.
- Joo-sung Yun
- G01 - MEASURING TESTING
Information Patent Grant
Coarse-grain programmable routing network for logic devices
- Patent number 10,587,270
- Issue date Mar 10, 2020
- Intel Corporation
- Gary Wallichs
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Clock synchronization in multi-die field programmable gate array de...
- Patent number 10,530,367
- Issue date Jan 7, 2020
- Intel Corporation
- Chooi Pei Lim
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System level interconnect with programmable switching
- Patent number 10,516,397
- Issue date Dec 24, 2019
- Cypress Semiconductor Corporation
- Bert Sullam
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Mapping a computer code to wires and gates
- Patent number 10,481,881
- Issue date Nov 19, 2019
- ARCHEO FUTURUS, INC.
- Daniel Joseph Bentley Kluss
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Embedded FPGA with multiple configurable flexible logic blocks inst...
- Patent number 10,454,480
- Issue date Oct 22, 2019
- Silicon Mobility
- Grégorie Martin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Circuit arrangements and methods for dividing a three-dimensional i...
- Patent number 10,411,709
- Issue date Sep 10, 2019
- Xilinx, Inc.
- Ehsan Ghasemi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
FPGA having a virtual array of logic tiles, and method of configuri...
- Patent number 10,411,711
- Issue date Sep 10, 2019
- Flex Logix Technologies, Inc.
- Anthony Kozaczuk
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
FPGA having programmable powered-up/powered-down logic tiles, and m...
- Patent number 10,411,712
- Issue date Sep 10, 2019
- Flex Logix Technologies, Inc.
- Cheng C. Wang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
3D semiconductor device and system
- Patent number 10,388,568
- Issue date Aug 20, 2019
- Monolithic 3D Inc.
- Zvi Or-Bach
- H03 - BASIC ELECTRONIC CIRCUITRY

Patents Applicationslast 30 patents

Information Patent Application
3D STACKED INTEGRATED CIRCUITS HAVING FAILURE MANAGEMENT
- Publication number 20240421823
- Publication date Dec 19, 2024
- Micron Technology, Inc.
- Tony M. Brewer
- G11 - INFORMATION STORAGE
Information Patent Application
Fabric Die to Fabric Die Interconnect for Modularized Integrated Ci...
- Publication number 20240312909
- Publication date Sep 19, 2024
- Intel Corporation
- Chee Hak Teh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
LOGIC CELL STRUCTURE AND INTEGRATED CIRCUIT WITH THE LOGIC CELL STR...
- Publication number 20240088899
- Publication date Mar 14, 2024
- Taiwan Semiconductor Manufacturing company Ltd.
- SHAO-HUAN WANG
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Fabric Die to Fabric Die Interconnect for Modularized Integrated Ci...
- Publication number 20230378061
- Publication date Nov 23, 2023
- Intel Corporation
- Chee Hak Teh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
LOW POWER INTERCONNECT USING RESONANT DRIVE CIRCUITRY
- Publication number 20220393684
- Publication date Dec 8, 2022
- Power Down Semiconductor, Inc.
- David A Huffman
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Field Programmable Gate Array Architecture Optimized For Machine Le...
- Publication number 20220327434
- Publication date Oct 13, 2022
- Board of Regents, The University of Texas System
- Lizy Kurian John
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS AND APPARATUS FOR REORDERING SIGNALS
- Publication number 20220229665
- Publication date Jul 21, 2022
- Semiconductor Components Industries, LLC
- Michael Alvin RENCHER
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HIGH-SPEED CORE INTERCONNECT FOR MULTI-DIE PROGRAMMABLE LOGIC DEVICES
- Publication number 20210384911
- Publication date Dec 9, 2021
- Intel Corporation
- Lai Guan Tang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
3D STACKED INTEGRATED CIRCUITS HAVING FAILURE MANAGEMENT
- Publication number 20210313990
- Publication date Oct 7, 2021
- Micron Technology, Inc.
- Tony M. Brewer
- G11 - INFORMATION STORAGE
Information Patent Application
Fabric Die to Fabric Die Interconnect for Modularized Integrated Ci...
- Publication number 20210111116
- Publication date Apr 15, 2021
- Intel Corporation
- Chee Hak Teh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
LOGIC CELL STRUCTURE AND INTEGRATED CIRCUIT WITH THE LOGIC CELL STR...
- Publication number 20210091769
- Publication date Mar 25, 2021
- Taiwan Semiconductor Manufacturing company Ltd.
- SHAO-HUAN WANG
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
COARSE-GRAIN PROGRAMMABLE ROUTING NETWORK FOR LOGIC DEVICES
- Publication number 20200395942
- Publication date Dec 17, 2020
- Intel Corporation
- Gary Wallichs
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
3D SEMICONDUCTOR DEVICE AND STRUCTURE
- Publication number 20200365463
- Publication date Nov 19, 2020
- MonolithIC 3D Inc.
- Zvi Or-Bach
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MAPPING A COMPUTER CODE TO WIRES AND GATES
- Publication number 20200348915
- Publication date Nov 5, 2020
- Archeo Futurus, Inc.
- Daniel Joseph Bentley Kluss
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
3D SEMICONDUCTOR DEVICE AND STRUCTURE
- Publication number 20200335399
- Publication date Oct 22, 2020
- MonolithIC 3D Inc.
- Zvi Or-Bach
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
HIGH-SPEED CORE INTERCONNECT FOR MULTI-DIE PROGRAMMABLE LOGIC DEVICES
- Publication number 20200321964
- Publication date Oct 8, 2020
- Intel Corporation
- Lai Guan Tang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
RECONFIGURABLE CIRCUIT AND THE METHOD FOR USING THE SAME
- Publication number 20200295764
- Publication date Sep 17, 2020
- NEC Corporation
- Xu BAI
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
LOGIC INTEGRATED CIRCUIT
- Publication number 20200266822
- Publication date Aug 20, 2020
- NEC Corporation
- Yukihide TSUJI
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
3D Stacked Integrated Circuits Having Failure Management
- Publication number 20200244268
- Publication date Jul 30, 2020
- Micron Technology, Inc.
- Tony M. Brewer
- G11 - INFORMATION STORAGE
Information Patent Application
3D STACKED INTEGRATED CIRCUITS HAVING FAILURE MANAGEMENT
- Publication number 20200195252
- Publication date Jun 18, 2020
- Micron Technology, Inc.
- Tony M. Brewer
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SYSTEM LEVEL INTERCONNECT WITH PROGRAMMABLE SWITCHING
- Publication number 20200169259
- Publication date May 28, 2020
- CYPRESS SEMICONDUCTOR CORPORATION
- Bert Sullam
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
TEST APPARATUS FOR SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING...
- Publication number 20190377028
- Publication date Dec 12, 2019
- Samsung Electronics Co., Ltd.
- Joo-sung YUN
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Fabric Die to Fabric Die Interconnect for Modularized Integrated Ci...
- Publication number 20190326210
- Publication date Oct 24, 2019
- Chee Hak Teh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
COARSE-GRAIN PROGRAMMABLE ROUTING NETWORK FOR LOGIC DEVICES
- Publication number 20190296744
- Publication date Sep 26, 2019
- Intel Corporation
- Gary Wallichs
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
SYSTEM LEVEL INTERCONNECT WITH PROGRAMMABLE SWITCHING
- Publication number 20190214995
- Publication date Jul 11, 2019
- CYPRESS SEMICONDUCTOR CORPORATION
- Bert Sullam
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
METHODS TO PRODUCE A 3D SEMICONDUCTOR MEMORY DEVICE AND SYSTEM
- Publication number 20190164834
- Publication date May 30, 2019
- MonolithIC 3D Inc.
- Zvi Or-Bach
- G11 - INFORMATION STORAGE
Information Patent Application
METHOD FOR PRODUCING A 3D MEMORY DEVICE
- Publication number 20190148234
- Publication date May 16, 2019
- MonolithIC 3D Inc.
- Zvi Or-Bach
- G11 - INFORMATION STORAGE
Information Patent Application
HIGH-SPEED CORE INTERCONNECT FOR MULTI-DIE PROGRAMMABLE LOGIC DEVICES
- Publication number 20190140649
- Publication date May 9, 2019
- Intel Corporation
- Lai Guan Tang
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
3D SEMICONDUCTOR DEVICE AND SYSTEM
- Publication number 20190139827
- Publication date May 9, 2019
- MonolithIC 3D Inc.
- Zvi Or-Bach
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Embedded FPGA with Multiple Configurable Flexible Logic Blocks Inst...
- Publication number 20190131970
- Publication date May 2, 2019
- Silicon Mobility
- Grégorie Martin
- G06 - COMPUTING CALCULATING COUNTING

the logic functions being realised by the interconnection of rows and columns

Industry

Parent Industries

Current Industry

Patents Grantslast 30 patents

Power-up switch-interconnect configuration

3D stacked integrated circuits having failure management

Fabric die to fabric die interconnect for modularized integrated ci...

Logic cell structure and integrated circuit with the logic cell str...

Methods and apparatus for reordering signals

Low power interconnect using resonant drive circuitry

Fabric die to fabric die interconnect for modularized integrated ci...

High-speed core interconnect for multi-die programmable logic devices

Vertical field-effect transistor (VFET) devices including latches h...

High-speed core interconnect for multi-die programmable logic devices

Coarse-grain programmable routing network for logic devices

3D stacked integrated circuits having failure management

Reconfigurable circuit and the method for using the same

Fabric die to fabric die interconnect for modularized integrated ci...

High performance QR decomposition systems and methods

Logic cell structure and integrated circuit with the logic cell str...

System level interconnect with programmable switching

Data interpolation

High-speed core interconnect for multi-die programmable logic devices

3D stacked integrated circuits having failure management

Test apparatus for semiconductor device and method of manufacturing...

Coarse-grain programmable routing network for logic devices

Clock synchronization in multi-die field programmable gate array de...

System level interconnect with programmable switching

Mapping a computer code to wires and gates

Embedded FPGA with multiple configurable flexible logic blocks inst...

Circuit arrangements and methods for dividing a three-dimensional i...

FPGA having a virtual array of logic tiles, and method of configuri...

FPGA having programmable powered-up/powered-down logic tiles, and m...

3D semiconductor device and system

Patents Applicationslast 30 patents

3D STACKED INTEGRATED CIRCUITS HAVING FAILURE MANAGEMENT

Fabric Die to Fabric Die Interconnect for Modularized Integrated Ci...

LOGIC CELL STRUCTURE AND INTEGRATED CIRCUIT WITH THE LOGIC CELL STR...

Fabric Die to Fabric Die Interconnect for Modularized Integrated Ci...

LOW POWER INTERCONNECT USING RESONANT DRIVE CIRCUITRY

Field Programmable Gate Array Architecture Optimized For Machine Le...

METHODS AND APPARATUS FOR REORDERING SIGNALS

HIGH-SPEED CORE INTERCONNECT FOR MULTI-DIE PROGRAMMABLE LOGIC DEVICES

3D STACKED INTEGRATED CIRCUITS HAVING FAILURE MANAGEMENT

Fabric Die to Fabric Die Interconnect for Modularized Integrated Ci...

LOGIC CELL STRUCTURE AND INTEGRATED CIRCUIT WITH THE LOGIC CELL STR...

COARSE-GRAIN PROGRAMMABLE ROUTING NETWORK FOR LOGIC DEVICES

3D SEMICONDUCTOR DEVICE AND STRUCTURE

MAPPING A COMPUTER CODE TO WIRES AND GATES

3D SEMICONDUCTOR DEVICE AND STRUCTURE

HIGH-SPEED CORE INTERCONNECT FOR MULTI-DIE PROGRAMMABLE LOGIC DEVICES

RECONFIGURABLE CIRCUIT AND THE METHOD FOR USING THE SAME

LOGIC INTEGRATED CIRCUIT

3D Stacked Integrated Circuits Having Failure Management

3D STACKED INTEGRATED CIRCUITS HAVING FAILURE MANAGEMENT

SYSTEM LEVEL INTERCONNECT WITH PROGRAMMABLE SWITCHING

TEST APPARATUS FOR SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING...

Fabric Die to Fabric Die Interconnect for Modularized Integrated Ci...

COARSE-GRAIN PROGRAMMABLE ROUTING NETWORK FOR LOGIC DEVICES

SYSTEM LEVEL INTERCONNECT WITH PROGRAMMABLE SWITCHING

METHODS TO PRODUCE A 3D SEMICONDUCTOR MEMORY DEVICE AND SYSTEM

METHOD FOR PRODUCING A 3D MEMORY DEVICE

HIGH-SPEED CORE INTERCONNECT FOR MULTI-DIE PROGRAMMABLE LOGIC DEVICES

3D SEMICONDUCTOR DEVICE AND SYSTEM

Embedded FPGA with Multiple Configurable Flexible Logic Blocks Inst...