Patent Application
20230006375
Edge connectors are widely used for add-in cards (AICs) in high-speed differential I/O (input/output) applications. For example, most desktop computers include multiple PCIe (Peripheral Component Interconnect Express) expansion slots with connectors mounted to the motherboard that are configured to interface with edge connectors on PCIe AICs (also referred to as expansions cards). This PCIe connectors are mounted perpendicular to the motherboard PCB (printed circuit board).
In 2012, Intel® Corporation introduced M.2 (pronounced M dot 2) for internal expansion cards on PC motherboards and laptop and the like. M.2, which originally Next Generation Form Factor (NGFF), was conceived as a successor of the mSATA interface. Today, M.2 supports multiple types of interfaces, including Peripheral Interconnect Connect Express (PCIe) 3.0 and 4.0, Serial ATA 3.0, USB 3.0, and Non-volatile Memory Express (NVMe).
PCI-SIG (Special Interest Group), the PCIe standards body, developed and standardized the PCIe M.2 card edge and mating PCIe M.2 connector, which is a right-angle connector that enables the expansion card to be installed parallel to the motherboard. Examples of an SSD M.2 edge card 100 and an M.2 connector 120 are shown in
SSD edge card 100 includes a PCB 102 including an PCIe M.2 edge connector 104, Various integrated circuits (aka chips) and other electronic components are mounted to PCB 102, including a memory controller chip 106, a DRAM memory chip 108, and a pair of non-volatile (NV) memory chips 110 and 112. PCIe M.2 edge connector has a Key B+M form factor with pins on a single side (the top side of SSD edge card 100 in this example).
PCIe M.2 connector 120 includes a body 122 having a slot in which edge contacts 124 are disposed. The edge contacts 124 are electrically coupled to contacts 126, which are soldered to pads in the motherboard PCB (or other type of PCB). When installed in PCIe M.2 connector 120, the pins in PCIe M.2 edge connector are electrically coupled to edge contacts 124, and thus to the pads in the PCB.
The PCIe M.2 connector was designed for PCIe 3.0 and PCIe 4.0 (3rd and 4th generation) standards. For high speed I/O, such as PCIe5 (PCIe 5th generation), the M.2 connector shows performance degradation. The connector performance improvement is critical for higher data rate I/O applications. In addition, the pin count of this connector is not scalable with given PCIe edge card form factor, which limit the bandwidth of the card.
The M.2 connector used for WWAN has a current limitation of 500 mA per pin. There are 5 pins allocated for current, which means the present M.2 connector can support only up to 3.3V×5×500 mA=8.25 W(atts). With the advent of 5G and LTE advanced, the power requirement has increased significantly and hence the present M.2 connector cannot be used to support all the advanced feature of these new technologies. With the advancement in technologies (Next Gen SSD and WWAN module sub-6 with mm-wave), the PCIe interface needs to support higher speed and bandwidth. However, the current connectors are not designed to work at PCIe speed.
The foregoing aspects and many of the attendant advantages of this invention will become more readily appreciated as the same becomes better understood by reference to the following detailed description, when taken in conjunction with the accompanying drawings, wherein like reference numerals refer to like parts throughout the various views unless otherwise specified:
Embodiments of apparatus comprising connector-less modules are described herein. In the following description, numerous specific details are set forth to provide a thorough understanding of embodiments of the invention. One skilled in the relevant art will recognize, however, that the invention can be practiced without one or more of the specific details, or with other methods, components, materials, etc. In other instances, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring aspects of the invention.
Reference throughout this specification to “one embodiment” or “an embodiment” means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present invention. Thus, the appearances of the phrases “in one embodiment” or “in an embodiment” in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.
For clarity, individual components in the Figures herein may also be referred to by their labels in the Figures, rather than by a particular reference number. Additionally, reference numbers referring to a particular type of component (as opposed to a particular component) may be shown with a reference number followed by “(typ)” meaning “typical.” It will be understood that the configuration of these components will be typical of similar components that may exist but are not shown in the drawing Figures for simplicity and clarity or otherwise similar components that are not labeled with separate reference numbers. Conversely, “(typ)” is not to be construed as meaning the component, element, etc. is typically used for its disclosed function, implement, purpose, etc.
In accordance with aspects of the embodiment described and illustrated herein, a connector-less M.2. module solution and associated platform employing the M.2 module are provided. In one aspect, the M.2. module solution employs a Land Grid Array (LGA) comprising an array of LGA pins on the underside of the module PCB that are configured to engage respective pads patterned on the motherboard or system board PCB by applying a downward force to the module PCB. In another aspect, a novel clip assembly is provided to apply the downward force. According to another aspect, a heat shield is provided that is configured to be disposed over the module PCB to facilitate enhanced thermal spreading and lowering thermal resistance both towards the heat shield and the PCBs.
A Land Grid Array (LGA) 213 comprising an array of LGA pins 214 coupled to pads 216 is disposed on the underside of PCB 206. LGA pins 214 are coupled to pads 218 on BB chip 208 via wiring (traces and vias) in PCB 206. In one embodiment, BB chip 208 is a Ball Grid Array (BGA) package and pads 218 are BGA pads; however, the chips illustrated herein, including BB chip 208 may use other types of packages, as well. Some of LGA pins 214 may also be coupled to other WWAN circuitry via wiring that is not separately shown. In addition, a portion of the LGA pins will be used for power signals (input voltage(s) and ground) that may be routed to various WWAN circuitry.
As illustrated in
As further shown in
During installation of clip assembly 308, tabs 510 or 512 of hinge bracket 500 are inserted into slots 600 and 602. In one embodiment, the bottom of hinge bracket 500 is soldered to the topside of motherboard 304. Alternatively, other means may be used to secure hinge bracket 500 to motherboard 304, such as using a suitable adhesive.
To enhance heat transfer, debossed features 714, 716, and 718 are formed in cap 700. The shelves of debossed features 714, 716, and 718, which may have variable depths (as applicable) are configured to be disposed above respective chips in the baseband circuitry, with an appropriate thermal interface material (TIM) between the top of the chips and the underside of the debossed features to facilitate heat transfer from high power components such as the baseband modem SoC to the heat shield cap. The shielding height of RF portion is retained to avoid any possible cavity effect which might degrade RF performance. In the illustrated embodiment, a parting barrier 720 is transversely disposed across the width of cap 700. The parting barrier is used to isolate the BB components from the sensitive RF side.
In one embodiment, the heat transfer is further enhanced by strategically placing the GND (ground) vias. TIM is added between the bottom side of the WWAN module and the motherboard or main board on which it is snugly fitted. This helps in increasing the heat dissipation through a larger PCB area; spreading can further be improved by adding a high conductivity spreader on the bottom side of the motherboard/main board.
M.2 Form Factor
In accordance with an aspect of some embodiments, the module PCB has an outline form factor in accordance with the M.2 specification. The M.2 PCB form factors define a PCB width of 22 millimeters (mm) and varying lengths of 30, 42, 60, 80, and 110 mm. Each PCB form factor includes a notch having a radius formed in the end of the PCB opposite the connector end that is used to align that end of the PCB with a mounting screw. The M.2 specification defines several edge connector configurations, including connectors with a single row of pins and connectors with two columns of pins. Under some embodiments herein, the module PCBs employ an M2 PCB form factor while employing a connection-less LGA rather than a card edge configured to mate with an edge connector.
In addition to the M.2 form factors, other PCB form factors may also be used. The form factors include the Next Generation Small Form Factor (NGSFF, aka NF1 or M.3) recently introduced by Samsung®.
Signal traces (e.g., wiring) in PCB 902 are used to provide signal paths between LGA pins 914 and memory controller chip 904 and other electronic components on NVMe SSD 900. Upon installation of NVMe SSD 900 (e.g., in a laptop or notebook computer), LGA pins 914 would be electrically coupled to respective pads patterned on the motherboard PCB in a similar manner to that shown for the WWAN module. The use of a heat shield for an NVMe SSD is optional.
Generally, the number of LGA pins, dimensions of the LGA array, size of the SM pads, and pitch are all parameters that may be varied to suit the needs of a given application. In some embodiments, the number of LGA pins and SM pads may be substantially more than the number of pins on conventional PCIe M.2 edge connectors (or other types of edge connectors). The use of more LGA pins and SM pads enables support for a larger number of I/O signals and an increase in I/O bandwidth.
Generally, in addition to CPUs and/or SoCs, the teaching and principles disclosed herein may be applied to Other Processing Units (collectively termed XPUs) including one or more of Graphic Processor Units (GPUs) or General Purpose GPUs (GP-GPUs), Tensor Processing Units (TPUs), Data Processing Units (DPUs), Infrastructure Processing Units (IPUs), Artificial Intelligence (AI) processors or AI inference units and/or other accelerators, FPGAs and/or other programmable logic (used for compute purposes), etc. While some of the diagrams herein show the use of GPUs, this is merely exemplary and non-limiting. Moreover, as used in the following claims, the term “processor” is used to generically cover CPUs, GPUs, and various forms of other XPUs.
The thermal solutions described and illustrated above provide advantages over conventional M.2 modules by reducing the critical component temperatures owing to improved shield cap design and larger main board used for direct heat sinking and spreading. For example, simulations shown in
The stack height is also reduced, when compared to conventional M.2 solutions. For example, in one embodiment the stack height above the motherboard is only 2.25 mm, including the heat shield.
Although some embodiments have been described in reference to particular implementations, other implementations are possible according to some embodiments. Additionally, the arrangement and/or order of elements or other features illustrated in the drawings and/or described herein need not be arranged in the particular way illustrated and described. Many other arrangements are possible according to some embodiments.
In each system shown in a figure, the elements in some cases may each have a same reference number or a different reference number to suggest that the elements represented could be different and/or similar. However, an element may be flexible enough to have different implementations and work with some or all of the systems shown or described herein. The various elements shown in the figures may be the same or different. Which one is referred to as a first element and which is called a second element is arbitrary.
In the description and claims, the terms “coupled” and “connected,” along with their derivatives, may be used. It should be understood that these terms are not intended as synonyms for each other. Rather, in particular embodiments, “connected” may be used to indicate that two or more elements are in direct physical or electrical contact with each other. “Coupled” may mean that two or more elements are in direct physical or electrical contact. However, “coupled” may also mean that two or more elements are not in direct contact with each other, but yet still co-operate or interact with each other. Additionally, “communicatively coupled” means that two or more elements that may or may not be in direct contact with each other, are enabled to communicate with each other. For example, if component A is connected to component B, which in turn is connected to component C, component A may be communicatively coupled to component C using component B as an intermediary component.
An embodiment is an implementation or example of the inventions. Reference in the specification to “an embodiment,” “one embodiment,” “some embodiments,” or “other embodiments” means that a particular feature, structure, or characteristic described in connection with the embodiments is included in at least some embodiments, but not necessarily all embodiments, of the inventions. The various appearances “an embodiment,” “one embodiment,” or “some embodiments” are not necessarily all referring to the same embodiments.
Not all components, features, structures, characteristics, etc. described and illustrated herein need be included in a particular embodiment or embodiments. If the specification states a component, feature, structure, or characteristic “may”, “might”, “can” or “could” be included, for example, that particular component, feature, structure, or characteristic is not required to be included. If the specification or claim refers to “a” or “an” element, that does not mean there is only one of the element. If the specification or claims refer to “an additional” element, that does not preclude there being more than one of the additional element.
As used herein, a list of items joined by the term “at least one of” can mean any combination of the listed terms. For example, the phrase “at least one of A, B or C” can mean A; B; C; A and B; A and C; B and C; or A, B and C.
The above description of illustrated embodiments of the invention, including what is described in the Abstract, is not intended to be exhaustive or to limit the invention to the precise forms disclosed. While specific embodiments of, and examples for, the invention are described herein for illustrative purposes, various equivalent modifications are possible within the scope of the invention, as those skilled in the relevant art will recognize.
These modifications can be made to the invention in light of the above detailed description. The terms used in the following claims should not be construed to limit the invention to the specific embodiments disclosed in the specification and the drawings. Rather, the scope of the invention is to be determined entirely by the following claims, which are to be construed in accordance with established doctrines of claim interpretation.
