This present invention relates generally to computer memory, and more specifically to constrained coding to reduce floating gate coupling in non-volatile memories.
Phase-change memories (PCMs) and flash memories are examples of non-volatile memories with limited endurance (also referred to as a “limited life”). Such memories have limited endurance in the sense that after undergoing a number of writing cycles (RESET cycles for PCM, program/erase cycles for flash memory), the memory cells wear out and can no longer reliably store information.
Not-and (NAND) flash memories are widely used in contemporary memory systems due to their relatively low cost and high density. One source of errors in NAND flash memory is the capacitive coupling between adjacent floating gates that may cause cell-to-cell interference between adjacent cells in a NAND flash memory block. This type of potential error is of increasing importance with the increasing prominence of multi-level cells with increasing numbers of storage levels, and with the decreasing size of flash memory cells. Both the increasing number of storage levels and the decreasing size of flash memory cells improve storage density. As described in the article “A Zeroing Cell-to-Cell Interference Page Architecture with Temporary LSB Storing and Parallel MSB Program Scheme for MLC NAND Flash Memories” by Park et al., in the April 2008 IEE Journal of Solid-State Circuits, floating-gate coupling may be the dominant cause of errors for small multi-level cell (MLC) flash devices.
Contemporary flash memory controllers use error correction coding (ECC) to correct up to a certain number of bit errors per page. However, such ECC is limited, and can only correct a few bit errors per data block (for example, it may correct up to 12 bits per 512 bytes of data). Given the limitations on ECC, restrictions may be imposed on how writing to a NAND flash block may be performed. For example, MLC memories may restrict the user to sequential writing of pages in a block, with only one write allowed per page. Restrictions such as this can cause an increase in write latency, and can also cause write amplification. Write amplification adversely affects the lifetime of the flash device due to the wear caused by the additional program/erase cycles.
An exemplary embodiment is a computer implemented method for storing data. The method includes receiving write data to be written to a flash memory device, selecting a codeword in response to the write data, and writing the codeword to the flash memory device. The codeword is selected to reduce floating gate coupling in the flash memory device by preventing specified symbol patterns from occurring in the codeword.
Another exemplary embodiment is a computer implemented method for storing data. The method includes receiving write data to be written to a flash memory device, where the flash memory device includes a plurality of pages characterized by a page length. The write data is compressed, resulting in compressed write data. A codeword is selected in response to the compressed write data. The codeword is selected to reduce floating gate coupling in the flash memory device by preventing specified symbol patterns from occurring in the codeword. A length of the codeword is determined. The codeword is written a page in the flash memory device in response to the length of the codeword being less than or equal to the page length.
A further exemplary embodiment is a system that includes a receiver for receiving write data to be written to a flash memory device, and encoder for selecting a codeword in response to the write data, and a flash write processor for writing the codeword to the memory device. The codeword selected by the encoder to reduce floating gate coupling in the flash memory device by preventing specified symbol patterns from occurring in the codeword.
Additional features and advantages are realized through the techniques of the present embodiment. Other embodiments and aspects are described herein and are considered a part of the claimed invention. For a better understanding of the invention with the advantages and features, refer to the description and to the drawings.
The subject matter that is regarded as the invention is particularly pointed out and distinctly claimed in the claims at the conclusion of the specification. The foregoing and other features, and advantages of the invention are apparent from the following detailed description taken in conjunction with the accompanying drawings in which:
Exemplary embodiments of the present invention provide a system and method for writing to a not-and (NAND) flash memory to reduce floating gate coupling. In an exemplary embodiment, data is converted to a (possibly two-dimensional) bit pattern in which certain sub-patterns are forcibly absent. The absent sub-patterns are selected to be the patterns that have a high possibility of inducing errors due to floating gate coupling. Exemplary embodiments do not require any changes to the hardware design of the memory. Exemplary embodiments simply require a memory controller that converts data to the desirable form, and this can be done by hardware and/or software. Thus, exemplary embodiments are very flexible, because they can be used with any NAND flash memory technology; all that is required is to simply change the data conversion such that the restricted sub-patterns are adapted to the flash memory being used.
In an exemplary embodiment the encoder 106, decoder 108, and shared data 110 are located on a memory controller or memory module. In an alternate exemplary embodiment, the encoder 106, decoder 108, and shared data 110 are located on a memory device. The shared data 110 may be stored in a register or any other storage location that is accessible by both the encoder 106 and the decoder 108.
In an exemplary embodiment, the memory 102 is implemented by NAND flash memory devices or other non-volatile memory devices. In an exemplary embodiment, the memory 102 is implemented by a multi-level cell NAND flash memory device. In another exemplary embodiment, the memory 102 is implemented by a single level cell (SLC) NAND flash memory device.
Inputs to the encoder 106 depicted in
An input to the decoder 108 depicted in
An output from the decoder 108 depicted in
As used herein, the term “bit” refers to an element of an alphabet with two letters, conventionally the alphabet {0,1}. Also as used herein, the term “symbol” refers to an element from an alphabet with possibly more than two letters, thus a bit is a symbol. For example, in a 4-ary MLC flash, each cell can store one of four levels, labeled say {L0,L1,L2,L3}. Thus, a symbol may be an element of this 4-ary set. For both SLC and MLC flash, a symbol could also be formed by concatenating the values of multiple cells. For example, for SLC, each symbol could be formed by taking three consecutive single-bit cell locations and concatenating the binary data levels stored in these cells. Such a symbol would be an element of the set {000,001,010,011,100,101,110,111}. Exemplary embodiments described herein in terms of bits may be extended in other exemplary embodiments to symbols.
In a typical flash device, a mapping between physical and logical block addresses is maintained in the controller. Given a logical address and data for a write, the controller selects a physical page to write the data onto and records the logical-to-physical mapping. A typical example is the use of a log based file system (LBFS) where the physical page is the next erased page in the block to which the last logical page was written to, wherein the pages are sequenced, for example on the basis of proximity to the GSL.
In NAND flash memory, pages are the smallest write units and blocks are the smallest erase units. In an exemplary embodiment, the NAND flash memory has two-level cells (called single-level cell or “SLC” NAND flash, since there is only a single programmed level), and once a memory cell is programmed (e.g., changed from a “1” to a “0”), it cannot be changed until the entire block is erased. In this exemplary embodiment, erasing results in all memory cells in the block having a value of “1”.
In another exemplary embodiment the NAND flash memory has multi-level cells supporting more than two-levels (called multi-level cell or “MLC” NAND flash). For example, a four MLC memory may consist of cells capable of storing four levels. Each of the four levels may be denoted by a two-bit string, say, levels {11, 10, 01, 00} in order of increasing floating-gate charge, where the level “11” represents the erased state and level ‘00’ the highest charge. In this example, level “11” corresponds to programmed charge level zero (L0), “10” to level one (L1), “01” to level two (L2), and “00” to level three (L3).
As depicted in
In an example case, where the memory is a MLC memory, if memory cells 206e has a programmed charge level of L1, then memory cell 206e has a maximum floating gate coupling shift if all of its neighboring cells (memory cell 206a, memory cell 206b, memory cell 206c, memory cell 206d, memory cell 206f, memory cell 206g, memory cell 206h and memory cell 206i) have a charge level of L3. In this example, a write pattern where memory cell 206a has a value of L1 and all its neighboring cells have a value of L3 may be flagged as a forbidden write pattern. As used herein, the term “forbidden write pattern” refers to a data pattern that has a high probability of inducing errors due to floating gate coupling. In exemplary embodiments, constrained coding is applied to write data prior to writing to memory 102 to reduce (or eliminate) the possibility of the forbidden write patterns being written to memory 102.
Another example of a prohibited sub-pattern (also referred to herein as forbidden patterns) is one where for each memory cell 206 that has a particular level (e.g., L1) written, every n-neighborhood of the memory cell 206 may have no more than a certain number of each higher level (e.g., L2, L3). For example, in a four MLC memory, each cell that has the lowest programmed level L1 written may be restricted to being surrounded by no more than five L3s being written in an eight neighborhood. Thus, as depicted in
A further example of a forbidden pattern is that in a four MLC memory, the two by three pattern [x, L3, x; L3, L1, L3] may be forbidden as there is a large chance that the coupling between the middle L1 cell and the horizontal and vertical L3 cells may induce an error with a relatively high probability. Referring back
Other forbidden patterns may be implemented by exemplary embodiments based, with forbidden patterns being selected based on criteria such as, but not limited to, properties of the specific memories being utilized, usage conditions such as desired retention time, and environmental conditions. The forbidden patterns described herein are examples of just a few forbidden patterns that may be implemented by exemplary embodiments.
As shown in
The output of the compressor 304 is input to the floating gate coupling encoder 306 to generate a codeword (i.e., to convert the compressed write data into a codeword) to be written to the memory 302. Also input to the floating gate coupling encoder 306 is data stored in the log based file system (LBFS) buffer 310. Contents of the LBFS buffer 310 include one or more of the previously written pages in the memory 302. Data from the LBFS buffer 310 is utilized by the floating gate coupling code encoder 306 to prevent forbidden write patterns from being written to the memory 302 by taking into account the data stored in a previously written page(s). The LBFS buffer 310 is one example of a way to store previously written data. In an alternate exemplary embodiment, a different storage mechanism and/or storage arrangement is used to store the previously written data. The codeword is output from the floating gate coupling code encoder 306 and input to the flash write processor 308 for writing the codeword to the memory 302. Among other tasks, the write processor computes and adds ECC parity bits, as required, to the codeword generated by the floating gate coupling code encoder.
The floating gate coupling encoder 306 generates a one or two dimensional bit pattern from which the data to be written can be recovered, such that the bit pattern does not contain a given set of one or two dimensional sub-patterns which have a high chance of inducing floating gate coupling errors (i.e., the forbidden write patterns). The resulting bit pattern, or codeword, is input to the conventional flash write processor 308 which writes the data to the physical flash memory 302.
As shown in
Based on the state graph 402 or state table 404, a floating gate encoder can access a code table 408 in order to ensure that prohibited sub-patterns are not written within a group of memory cells. In the exemplary embodiment, a SLC flash memory has 5 cell (bit or symbol) pages, in which 4 bit (or 4 symbol) data will be written. The code table is indexed by the four-bit write data. The table is filled with 5 bit codewords (i.e., candidate codewords), which are formed by traversing the state graph 402 (or the state table 404). Codewords corresponding to different four-bit data are required to be different in order to ensure decodability. Thus, each codeword in the table is guaranteed to not contain the prohibited bit-pattern “010”. Given a four-bit write data 406, the codeword 410 indexed by the write data is determined from the code table and is written to memory. Thus, for example, if the data is “1011”, the corresponding codeword “11011” is selected and the selected codeword is written to memory. In general, because there are forbidden patterns, the read data will be expanded from four bits to more than four bits by the encoding process. The use of compression along with the code table can help to alleviate the amount of expansion that occurs, as will be described later. Also, in practice the data and flash page size will be much larger than the example just considered. In one embodiment, the flash page is partitioned into small (e.g. 5-bit) sub-pages, the data is partitioned into small blocks (e.g. 4 bit blocks), and the code-table based encoder is applied independently for each block-sub page pair. This approach reduces the computational complexity of coding. In this case the forbidden pattern is guaranteed to not occur in each sub-page (though it may occur across sub-page boundaries). Thus the frequency of the forbidden pattern can be significantly reduced.
If there are more bits in the write data, then block 710 is performed to compute the two dimensional neighborhood pattern surrounding bit c in the codeword. Both the prior page in the memory and the prior bits in the current page are known by the write process. For each cell location, c, to be written, the encoder 106 computes the 2D neighborhood of the location at block 710 and then determines, at block 712, if there exists any symbol which, when written to the current location, would cause a prohibited pattern from occurring. If such a symbol exits, then block 718 is performed and the encoder 106 writes a pre-determined symbol (referred to herein as a “stuffed bit” or “stuffed symbol”) into location c of the codeword. The pre-determined symbol may be a function of the computed two-dimensional neighborhood or may be a pre-fixed symbol common for all neighborhoods. The index into the codeword is incremented at block 720 and processing continues at block 710. If, as determined at block 712, there is not a symbol which, when written to the current location, would cause a prohibited pattern from occurring, then processing continues at block 714. At block 714, the data bit at index i is store in location c of the codeword. At block 716, the index into the codeword and the index into the write data is incremented. Processing then continues at block 706; here the processing is continued until all the data in the write word has been written into the codeword. In this manner, the bit patterns specified in the list of forbidden patterns are prevented from occurring in the resulting codeword.
The process depicted in
One issue that arises with the encoder processing depicted in
In an exemplary embodiment, if the codeword output from the encoder 106 is equal to or less than the page size then the codeword is written to the memory. Alternatively, if the resulting codeword is longer than the page size, then the original write data is written. An example of this process is depicted in
As depicted in
In an alternate embodiment the encoder can use one of multiple pre-specified floating gate coupling codes, each of which prevents or reduces the frequency of occurrence of a different set of bit-patterns. As an example, the encoder can use codes based on any of the three state tables shown in
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises” and/or “comprising,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
The corresponding structures, materials, acts, and equivalents of all means or step plus function elements in the claims below are intended to include any structure, material, or act for performing the function in combination with other claimed elements as specifically claimed. The description of the present invention has been presented for purposes of illustration and description, but is not intended to be exhaustive or limited to the invention in the form disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the invention. The embodiment was chosen and described in order to best explain the principles of the invention and the practical application, and to enable others of ordinary skill in the art to understand the invention for various embodiments with various modifications as are suited to the particular use contemplated.
As will be appreciated by one skilled in the art, aspects of the present invention may be embodied as a system, method or computer program product. Accordingly, aspects of the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment (including firmware, resident software, micro-code, etc.) or an embodiment combining software and hardware aspects that may all generally be referred to herein as a “circuit,” “module” or “system.” Furthermore, aspects of the present invention may take the form of a computer program product embodied in one or more computer readable medium(s) having computer readable program code embodied thereon.
Any combination of one or more computer readable medium(s) may be utilized. The computer readable medium may be a computer readable signal medium or a computer readable storage medium. A computer readable storage medium may be, for example, but not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination of the foregoing. More specific examples (a non-exhaustive list) of the computer readable storage medium would include the following: an electrical connection having one or more wires, a portable computer diskette, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or Flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing. In the context of this document, a computer readable storage medium may be any tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device.
A computer readable signal medium may include a propagated data signal with computer readable program code embodied therein, for example, in baseband or as part of a carrier wave. Such a propagated signal may take any of a variety of forms, including, but not limited to, electro-magnetic, optical, or any suitable combination thereof. A computer readable signal medium may be any computer readable medium that is not a computer readable storage medium and that can communicate, propagate, or transport a program for use by or in connection with an instruction execution system, apparatus, or device.
Program code embodied on a computer readable medium may be transmitted using any appropriate medium, including but not limited to wireless, wire line, optical fiber cable, RF, etc., or any suitable combination of the foregoing.
Computer program code for carrying out operations for aspects of the present invention may be written in any combination of one or more programming languages, including an object oriented programming language such as Java, Smalltalk, C++ or the like and conventional procedural programming languages, such as the “C” programming language or similar programming languages. The program code may execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer or server. In the latter scenario, the remote computer may be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or the connection may be made to an external computer (for example, through the Internet using an Internet Service Provider).
Aspects of the present invention are described below with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems) and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and/or block diagrams, and combinations of blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions/acts specified in the flowchart and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer readable medium that can direct a computer, other programmable data processing apparatus, or other devices to function in a particular manner, such that the instructions stored in the computer readable medium produce an article of manufacture including instructions which implement the function/act specified in the flowchart and/or block diagram block or blocks.
The computer program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other devices to cause a series of operational steps to be performed on the computer, other programmable apparatus or other devices to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide processes for implementing the functions/acts specified in the flowchart and/or block diagram block or blocks.
The flowchart and block diagrams in the Figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that, in some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems that perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.
Number | Name | Date | Kind |
---|---|---|---|
5502728 | Smith, III | Mar 1996 | A |
5623436 | Sowards et al. | Apr 1997 | A |
5751993 | Ofek et al. | May 1998 | A |
5818755 | Koyanagi et al. | Oct 1998 | A |
5860080 | James et al. | Jan 1999 | A |
5867429 | Chen et al. | Feb 1999 | A |
5912839 | Ovshinsky et al. | Jun 1999 | A |
5987570 | Hayes et al. | Nov 1999 | A |
6009547 | Jaquette et al. | Dec 1999 | A |
6026464 | Cohen | Feb 2000 | A |
6040993 | Chen et al. | Mar 2000 | A |
6076183 | Espie et al. | Jun 2000 | A |
6222762 | Guterman et al. | Apr 2001 | B1 |
6226723 | Gustavson et al. | May 2001 | B1 |
6292398 | Pasotti et al. | Sep 2001 | B1 |
6292903 | Coteus et al. | Sep 2001 | B1 |
6301151 | Engh et al. | Oct 2001 | B1 |
6370324 | Kawahara et al. | Apr 2002 | B1 |
6397366 | Tanaka et al. | May 2002 | B1 |
6415363 | Benayoun et al. | Jul 2002 | B1 |
6424566 | Parker | Jul 2002 | B1 |
6457174 | Kuroda et al. | Sep 2002 | B1 |
6473879 | Ishii et al. | Oct 2002 | B1 |
6522580 | Chen et al. | Feb 2003 | B2 |
6570784 | Lowrey | May 2003 | B2 |
6728826 | Kaki et al. | Apr 2004 | B2 |
6748561 | Prasad | Jun 2004 | B2 |
6816413 | Tanzawa | Nov 2004 | B2 |
6870773 | Noguchi et al. | Mar 2005 | B2 |
6937522 | Funaki | Aug 2005 | B2 |
6970382 | Toros et al. | Nov 2005 | B2 |
7031181 | Happ | Apr 2006 | B1 |
7073012 | Lee | Jul 2006 | B2 |
7103812 | Thompson et al. | Sep 2006 | B1 |
7127004 | Sonning et al. | Oct 2006 | B1 |
7177199 | Chen et al. | Feb 2007 | B2 |
7180771 | Cho et al. | Feb 2007 | B2 |
7203886 | Brown et al. | Apr 2007 | B2 |
7292466 | Nirschl | Nov 2007 | B2 |
7301817 | Li et al. | Nov 2007 | B2 |
7305596 | Noda et al. | Dec 2007 | B2 |
7313016 | Dodge et al. | Dec 2007 | B2 |
7327609 | Kim et al. | Feb 2008 | B2 |
7352624 | Roohparvar | Apr 2008 | B2 |
7352627 | Cohen | Apr 2008 | B2 |
7355237 | Lutze et al. | Apr 2008 | B2 |
7362615 | Pham et al. | Apr 2008 | B2 |
7372725 | Philipp et al. | May 2008 | B2 |
7391642 | Gordon et al. | Jun 2008 | B2 |
7397698 | Fong et al. | Jul 2008 | B2 |
7430639 | Bali et al. | Sep 2008 | B1 |
7436703 | Pham et al. | Oct 2008 | B2 |
7440315 | Lung | Oct 2008 | B2 |
7447948 | Galbi et al. | Nov 2008 | B2 |
7471559 | Shibata | Dec 2008 | B2 |
7480176 | Kamei | Jan 2009 | B2 |
7542336 | Han | Jun 2009 | B2 |
7606077 | Li et al. | Oct 2009 | B2 |
20020099996 | Demura et al. | Jul 2002 | A1 |
20030163776 | Prasad | Aug 2003 | A1 |
20040153902 | Machado et al. | Aug 2004 | A1 |
20050138276 | Navada et al. | Jun 2005 | A1 |
20050166006 | Talbot et al. | Jul 2005 | A1 |
20050190609 | Janssen et al. | Sep 2005 | A1 |
20050240745 | Lyer et al. | Oct 2005 | A1 |
20050251621 | Theis | Nov 2005 | A1 |
20060015780 | Fong | Jan 2006 | A1 |
20060090051 | Speier et al. | Apr 2006 | A1 |
20060155791 | Tene et al. | Jul 2006 | A1 |
20060179400 | Qian et al. | Aug 2006 | A1 |
20070153579 | Roohparvar et al. | Jul 2007 | A1 |
20070189065 | Suh et al. | Aug 2007 | A1 |
20080010581 | Alrod et al. | Jan 2008 | A1 |
20080025080 | Chan et al. | Jan 2008 | A1 |
20080034272 | Wu et al. | Feb 2008 | A1 |
20080052424 | Sameshima et al. | Feb 2008 | A1 |
20080114947 | Brox et al. | May 2008 | A1 |
20080151613 | Chao et al. | Jun 2008 | A1 |
20080158959 | Mokhlesi | Jul 2008 | A1 |
20080162858 | Moyer | Jul 2008 | A1 |
20080222368 | Gehrmann | Sep 2008 | A1 |
20080222491 | Lee et al. | Sep 2008 | A1 |
20080266991 | Lee et al. | Oct 2008 | A1 |
20080282106 | Shalvi et al. | Nov 2008 | A1 |
20090003044 | Happ et al. | Jan 2009 | A1 |
20090034324 | Kim et al. | Feb 2009 | A1 |
20090157994 | Hampel et al. | Jun 2009 | A1 |
20100020620 | Kim et al. | Jan 2010 | A1 |
20100034022 | Dutta et al. | Feb 2010 | A1 |
20100036997 | Brewer et al. | Feb 2010 | A1 |
20100125701 | Park | May 2010 | A1 |
20100165730 | Sommer et al. | Jul 2010 | A1 |
20100202198 | Kim et al. | Aug 2010 | A1 |
20100223530 | Son et al. | Sep 2010 | A1 |
20100241929 | Song et al. | Sep 2010 | A1 |
20110145504 | Anh et al. | Jun 2011 | A1 |
20110154160 | Yurzola et al. | Jun 2011 | A1 |
20110216586 | Graef et al. | Sep 2011 | A1 |
Number | Date | Country |
---|---|---|
W02006064497 | Jun 2006 | WO |
Entry |
---|
Feng Qin et al.; “Exploiting ECC-Memory for Detecting Memory Leaks and Memory Corruption during Production Runs”, 11th International Symposium on High-Performance Comptuer Architecture (HPCA-Nov. 2005), pp. 12. |
G. Novark et al.; “Exterminator: Automatically Correcting Memory Errors with High Probability”; PLDI'07; Jun. 11-13, 2007; San Diego, CA; Copyright 2007; 11 pages. |
Ki-Tae Park et al., “A Zeroing Cell-to-Cell Interference Page Architecture with Temporary LSB Storing and Parallel MSB Program Scheme for MLC NAND Flash Memories,” IEEE Journal of Solid-State Circuits, vol. 43, No. 4, Apr. 2008, pp. 919-928. |
Noboru Shibata et al., “A 70 nm 16 Gb 1-Level-Cell NAND Flash Memory”, IEEEJournal of Solid-State Circuits, vol. 43, No. 4, Apr. 2008, pp. 929-937. |
Number | Date | Country | |
---|---|---|---|
20110246703 A1 | Oct 2011 | US |