Patent Grant
10763896
The invention relates to a technical field of channel coding in communication transmission, and more particularly to a construction method for a (n,n(n−1),n−1) permutation group code based on coset partition and a codebook generator thereof.
Multiple interferences comprising multipath fading, permanent narrow-band noise, broadband impulse noise and colored background noises may coexist in a power line channel, which is uncommon for wireless and wired channels. Therefore, information transmission reliability is hard to be guaranteed by applying existing technology of wireless and wired communications directly to power line carrier communication channels, and it is necessary to propose a solution of error-correcting codes with higher reliability to interferences of multiple forms and multiple frequencies in power line carrier communication. Besides, error-correcting codes with higher reliability are still needed for wider wireless transmission environment with interferences of multiple forms and multiple frequencies.
In 2000, Vinck introduced permutation codes into power line carrier communication, and a corresponding dissertation “‘Coded modulation for power line communications’, AEU int. J. Electron. Commun., vol. 54, no. 1, pp: 45-49, 2000” discloses a power line carrier coded modulation method combining permutation code and M-dimension FSK modulation, where time diversity and frequency diversity are introduced simultaneously at a transmitter terminal according to redundancy of permutation codes to increase capability of resisting fading and interferences of multiple frequencies, and a receiving signal is detected by a constant envelope demodulation algorithm at a receiver terminal to form a simple non-coherent demodulation method. It should be noted that Vinck came to a conclusion that permutation codes have an error-correcting capability of d−1 rather than └(d−1)/2┘ through analyzing a permutation code with code length of 4. However, Vinck failed to provide an effective construction method for permutation codes. At present, permutation codes with an error-correcting capability of d−1 develop slowly and are not applied in practice for design methods for algebraic structures of permutation codes are rare and more particularly, the problem of their executable circuits has not been effectively solved yet.
In view of the above-mentioned problems, it is an objective of the invention to provide a construction method of (n,n(n−1),n−1) permutation group code based on coset partition and a codebook generator thereof. More specifically, there is provided an algebraic structural design method and a codebook enumerator for permutation codes with a code length of n, a minimum distance of n−1, a cardinality of n(n−1) and an error-correcting capability of d−1=n−2. For multiple interferences comprising multipath fading, permanent narrow-band noise, broadband impulse noise and colored background noises may coexist in a power line channel, the invention provides a design method for an error-correcting code capable of resisting the mixed interferences. Besides, the permutation group code of the invention features a strong anti-interference capability for multi-frequency interferences in wireless communication and malicious frequency interferences from a human being, and is capable of protecting transmitted signals under the circumstance with low requirement for data rate and coexisted deep fading and various mixed frequency interferences. To achieve the above objective, according to one embodiment of the invention, there is provided a construction method of the (n,n(n−1),n−1) permutation group codes based on coset partition, wherein a construction of this permutation code with a code length of n, a minimum distance of n−1 and a code size of n(n−1) is expressed by Pn={{pβα}β=1n}α=1n-1=CnOn={{Cno1}, {Cno2}, . . . , {Cnon-1}}={{cβ∘oα}β=1n}α=1n-1, Pn=CnOn represents that Cn is a coset of the subgroup On and On is also a coset of the subgroup Cn, Pn={{Cno1}, {Cno2}, . . . , {Cnon-1}} represents dividing Pn into n−1 cosets by the subgroup Cn, each coset {Cnoα} forms an orbit or an cyclic Latin square (C-LS) of a permutation oα, Pn={{pβα}β=1n}α=1n-1={{cβ∘oα}β=1n}α=1n-1 represents a permutation code and each codeword Pβα is generated by composition operation of a permutation cβ of the subgroup Cn and a permutation oα of the subgroup On, α=1, 2, . . . n−1, and β=1, 2, . . . n.
According to another embodiment of the invention, there is provided a generator of the (n,n(n−1),n−1) permutation group code based on coset partition, comprising an orbit leader array generator, a flash memory and a cyclic-bidirectional-shift register group, wherein
the orbit leader array generator is operable for performing an operation of On={αo1}α=1n-1(mod n) to generate n−1 orbit leader permutations;
the flash memory is operable for storing output results of the orbit leader array generator and the cyclic-bidirectional-shift register group; and
the cyclic-bidirectional-shift register group is operable for performing the operation of (l1)n-1 or (rn)n-1 acting on a permutation by calculating an orbit {(l1)n-1oα} or {(rn)n-1oα)} of an orbit leader permutation oα, and a code set {(l1)n-1On} or {(rn)n-1On}, where α=1, 2, . . . , n−1.
The (n,n(n−1),n−1) permutation group code based on coset partition of the invention is an algebraic-structured code, the orbit leader permutation codewords of the code set can be obtained simply by adder and (mod n) calculator instead of complex composition operations, and the whole code set can be realized by a group of cyclic shift registers. As a non-binary error-correcting code, the permutation code has an error-correcting capability of d−1, two times that of non-binary error-correcting codes in prior art. Demodulation can be realized simply by a noncoherent constant envelop detecting technology at a receiver terminal combining permutation code with MFSK modulation technology, and signal transmission reliability can be guaranteed for communication channels with deep fading and mixed frequency noises.
For clear understanding of the objectives, features and advantages of the invention, detailed description of the invention will be given below in conjunction with accompanying drawings and specific embodiments. It should be noted that the embodiments are only meant to explain the invention, and not to limit the scope of the invention.
Basic Principles
Basic principles of a (n,n(n−1),n−1) permutation group code based on coset partition of the invention are given below.
Code symbols can take values in two finite fields, namely, Zn0={0, 1, . . . , n−1} represents a finite field of order n containing element 0, and Zn1={1, 2, . . . , n}represents a finite positive integer field of order n containing no element 0, and is also a cyclic group of order n.
Calling a set formed by all n! permutations of n elements in Zn0 or Zn1 a symmetric group Sn={π1, . . . , πk, . . . , πn!}, an element of Sn can be represented by a permutation πk=[a1 . . . ai . . . an], elements of a permutation by a1 . . . ai . . . an∈Zn0 or a1 . . . ai . . . an∈Zn1, degree (dimension) of a permutation is |πk|=n, and cardinality (order) of the symmetric group is |Sn|=n!. Let π0=e=[a1a2 . . . an]=[01 . . . n−1] or π0=e=[a1a2 . . . an]=[12 . . . n] represent an identity element of the symmetric group Sn, where [a1a2 . . . an] represent a permutation in Sn, and (a1a2 . . . an) represents a permutation operator.
A group H is a cyclic permutation group if H can be generated by a single element, i.e., there is an element x∈H such that H={xi|i∈Zn1, x, xi∈Sn}. We shall write H=<x> and say that H is generated by x or x is a generator of H.
Let γ=(γ2) be a cyclic permutation group of n permutation operators, its generator is γ2=(a2a3 . . . ana1), and its cardinality is |γ|=n. If making the operator set γ=(γ2) act on a permutation π=[a1 . . . ai . . . an], we get {γπ}={{γ2, γ3, . . . , γn, γ1}[a1 . . . ai . . . an]}={<γ2>π}={{γ2, γ22, . . . , γn, γ1}[a1 . . . ai . . . an]}, then {γπ} is regarded as an orbit containing permutation π under the action of cyclic permutation group γ and element number of the orbit {γπ} is |{γπ}|=n.
Basic structure of the (n,n(n−1),n−1) permutation group code based on coset partition is provided by the following two Theorems and a Lemma without a proof.
Lemma 1 [construction of Cn]: Cn={c1, c2, . . . , cn}=<c2> is a subgroup of Sn and also a cyclic permutation group with minimum distance dCγ2
[a1a2 . . . an]}; (ii) its subscript is specified to keep consistent with the value of the first element of each permutation in Cn, i.e., c1=γ1π=c2n=γ2nπ=(a2a3 . . . ana1)n[a1a2 . . . an]=[a1a2, . . . an], c2=γ2π=[a2a3 . . . ana1], c3=γ3π=c22=γ22π=(a2a3 . . . ana1)2[a1a2 . . . an]=[a3a4 . . . ana1a2], . . . , cn=γnπ=c2n-1=γ2n-1π=(a2a3 . . . ana1)n-1[a1a2 . . . an]=[ana1a2 . . . an-1].
Theorem 2 [construction of On]: Let On be a (n−1)×n permutation array or a set formed by n−1 permutations, and construct On={oα}α=1n-1={α·o1}α=1n-1, where o1=[12 . . . n] is an identity permutation, and α=1, 2, . . . , n−1 is the row index of permutation array On, also as an index of the number of permutations in the set On. If and only if i) n is a prime; ii) for all α=1, 2, . . . , n−1, we have (α·n)(mod n)=n; then the set On is a subgroup of Sn, all elements of the nth column in the array On are n, and the minimum distance of On is dO
Theorem 3 [constructing a permutation group code Pn by Cn and On]: For any prime n, let Pn={p11, . . . , pβα, . . . , pn(n−1)} be a nontrivial subgroup of Sn, we use the composition of Cn and On to construct Pn, i.e., Pn={{pβα}β=1n}α=1n-1=CnOn={{cβ∘oα}β=1n}α=1n-1, where cβ∘oα denotes a composition operation between a permutation cβ∈Cn and a permutation oα∈On. If Cn∩On=e=[12 . . . n], then Pn is a permutation group code with the minimum Hamming distance dP
Let n=5, and C5 is obtained by Lemma 1 as follows:
O5 in a form of permutation array is obtained by Theorem 2 as follows:
So that O5 in a form of set is obtained as follows:
Let c1=o1=e=[12345], and P5 is obtained by Theorem 3 as follows:
Example 1 illustrates P5 is a permutation group code with a code length of 5, a minimum distance of 4, a code set size of 20 and an error-correcting capability of 3, and it can be seen that P5 is formed by four orbits {C5o1}, {C5o2}, {C5o3}, {C5o4}.
It is formed by two parts. The first part covers a construction method for a (n,n(n−1),n−1) permutation group code based on coset partition, and the second part covers a generator of this permutation group code thereof.
Part 1: a construction method for a (n,n(n−1),n−1) permutation group code based on coset partition.
In terms of Lemma 1 and Theorems 2 and 3, in the construction method for a (n,n(n−1),n−1) permutation group code based on coset partition, all codewords in the code set are calculated by Pn={{pβα}β=1n}α=1n-1=CnOn={{Cno1}, (Cno2), . . . , {Cnon-1}}={{cβ∘oα}α=1n-1}β=1n, where Pn is a non-trivial subgroup of a symmetric group Sn, with a size of |Pn|=n(n−1) and a minimum distance of d|Pc2
is a subgroup of Pn and also a cyclic group with a size of |Cn=n and a minimum distance of d|C
Each codeword of the code set is calculated by pβα=cβ∘oα representing a composition operation between a permutation cβ∈Cn and a permutation oα∈On, which is unfavorable for hardware realization, and therefore a circuit executable permutation operation function should be constructed. Since Cn is a cyclic group, it is possible to substitute cyclic shift operation of a permutation for the action of Cn, so that composition operation of two permutations are equivalently transferred to cyclic shift operation of being able to be performed by basic unit circuit namely cyclic shift register. Therefore, operation function and composite operation function are defined first as follows.
Construction of Operation Function
Let T be a set of all operation functions available acting on a permutation, construct a right-shift operation function set Tright={r2, r3, . . . , rn-1, rn}⊂T, where each element ri∈Tright is a function ri:Sn→Sn defined by riπ=ri[a1 . . . ai . . . an]=[aia1 . . . ai−1ai+1, . . . an]∈Sn, and ri∈Tright is called as a partial cyclic right-shift operation function of a permutation. Especially for i=n, we have rnπ=rn[a1a2 . . . an]=[ana1a2 . . . an-1]∈Sn and rn is called as a cyclic-right-shift operation function of a permutation. Similarly, construct a left-shift operation function set Tleft={l1, l2, . . . , ln-1}⊂T, where each element lj∈Tleft is a function lj:Sn→Sn defined by ljπ=lj[a1 . . . aj . . . an]=[a1 . . . aj−1aj+1 . . . anaj]∈Sn, and lj∈Tleft is called as a partial cyclic left-shift operation function of a permutation. Especially for j=1, we have l1π=l1[a1a2 . . . an]=[a2a3 . . . an-1ana1]∈Sn and l1 is called as a cyclic-left-shift operation function of a permutation.
Construction of Cyclic Shift Composite Operation Function
Arrange part or all operation functions of the set Tleft or Tright in a string or consecutive multiplication of powers of different functions, so that the operation function string or the product of function powers forms a composite operation function represented as ƒCF(u,Λ), where u is the number of operation functions in the composite operation function ƒCF(u,Λ), and Λ is an arranging rule of the operation functions, which is: some a function is repeatedly used for λ−1 times, and as λ=n, a left cycle composite operation function is constructed as
and a right cycle composite operation function is constructed as
Performing the two composite operation functions on a permutation π=[a1a2 . . . an] respectively, two sets of n permutations are obtained as {(l1)n-1π}{π, l1π, l12π, . . . , l1n-1π} and {(rn)n-1π}
{π, rnπ, rn2π, . . . , rnn-1π}. {(l1)n-1π} and {(rn)n-1π} are two orbits of the permutation π as the orbit {Cnπ}, we have {Cnπ}={(l1)n-1π}={(rn)n-1π}, namely, three orbits obtained by the three different operations form equivalence class but corresponding C-LSs are not equal each other because of different arrangement of permutations in these orbits.
As a result, the cyclic group Cn of the code set Pn={CnOn} can be replaced by the left cycle composite operation function (l1)n-1 or the right cycle composite operation function (rn)n-1, each orbit {Cnoα} is obtained by {Cnoα}={(rn)n-1oα}={(l1)n-1oα}, the expression enumerating all codewords is, Pn=CnOn={(rn)n-1On}={{(rn)n-1o1}, {(rn)n-1o2}, . . . , {(rn)n-1on-1}}={(l1)n-1On}={{(l1)n-1o1}, {(l1)n-1o2}, . . . , {(l1)n-1on-1}}. Structure features of the orbit leader array On provided by Theorem 2 are analyzed below and several different design methods are provided thereafter.
Structure Features of the Orbit Leader Array On:
An orbit leader array of the presented (n,n(n−1),n−1) permutation group code has the following features: first, it is an array of (n−1)×n, each row thereof is a permutation of Sn, and an unique column thereof contains a same element ak=k, where k,ak∈Zn0 or k,ak∈Zn1; second, removing the column containing the same element, residual rows and columns constitute a Latin square with a size of (n−1)×(n−1); and third, each row of the orbit leader array On has n different adjacent pairs (aμ,av) containing cyclic adjacent pairs, and the orbit leader array On itself contains n(n−1) different adjacent (or cyclic adjacent) pairs, μ, v, aμ, av∈Zn0 or μ, v, aμ, av∈Zn1, aμ≠av, and μ≠v. Generally, n(n−1) different pairs in a form of (aμ,av) can be obtained as constructed by n positive integers, which is a sufficient condition for the orbit leader array containing n(n−1) different adjacent pairs.
Design Method of the Orbit Leader Array On:
An orbit leader array meeting the above three structure features can be calculated by explicit expressions, and the following two design methods can be realized by hardwares for Theorem 2.
Method 1: A Permutation Contains Element 0
Let aα
aα
On1(k)={o0,o1, . . . ,on-2}={{aα
Method 2: A Permutation Contains No Element 0
Let aα
aα
On2(k2)={o1,o2, . . . ,on-1}={{aα
As k2=n, equations (iii) and (iv) in method 2 can be simplified as:
aα,β(n)=[α·β](mod n) for α=1,2, . . . ,n−1 and β=1, 2, . . . , n (v)
On={o1,o2, . . . ,on-1}={{aα,β(n)}β=1n}α=1n-1=[[α·β]β=1n]α=1n-1(mod n)={α·o1}α=1n-1(mod n) (vi)
Calculation of equation (vi) is the same as that of On in Theorem 2.
Let n=5, according to the design method 1, if aα
Performing a cyclic-left-shift composite operation function (l1)4 or a cyclic-right-shift composite operation function (r5)4 on the above five orbit leader arrays of On1(k1) (k1=0, 1, 2, 3, 4) respectively, ten equivalent permutation code sets can be obtained.
Let n=5, according to the design method 2 and a corresponding simplified alternative, if aα
Performing a cyclic-left-shift composite operation function (l1)4 or a cyclic-right-shift composite operation function (r5)4 on five orbit leader arrays of On2(k2) (k2=1, 2, 3, 4, 5) and a simplified orbit leader array O5 respectively, 12 permutation code sets obtained are equivalent to the code set of the (n,n(n−1),n−1) permutation group code obtained by composition operations, namely, for k=1, 2, 3, 4, 5,
Part 2: Structure Design of a Generator of the (n,n(n−1),n−1) Permutation Group Code Based on Coset Partition
Illustration of the generator comprises 4 parts: generator architecture, orbit leader array generator, flash memory and cyclic-bidirectional-shift register group.
Binary Expression of a Permutation:
If m-bit binary data are used to express elements of a permutation with a length of n, the permutation can be described by a binary array of m×n, and 2m-1+1≤n≤2m.
Generator Architecture of the Presented Code Set
As in
The orbit leader array generator is shown in
The orbit leader array generator is operable for performing an operation of On={αo1}α=1n-1(mod n)={o1, 2o1, . . . , (n−1)o1}(mod n) to generate n−1 orbit leader permutations as an initial permutation is o1=e=[12 . . . n], and transmitting each of the permutations to the flash memory right after it is generated.
The orbit leader array generator further comprises 5 parts: n parallel running input buffers (10), n parallel running positive integer adders (11), n parallel running mod n calculators (12), n parallel running output buffers (13), an n-input single-output switch (14) and an enable signal generator (15). Working principle of each part is described below.
The n parallel running input buffers (10) are formed by n m-bit binary registers, each binary register stores one of n input data as an m-bit binary data, an input and an output of each register are connected to m parallel data lines respectively, and the orbit leader generator starts to work after inputting the initial permutation o1=e=[12 . . . n] into the n parallel running input buffers (10). The n parallel running positive integer adders are operable for converting multiple operations in On={αo1}α=1n-1={o1, 2o1, . . . , (n−1)o1} to accumulating operations on each element of the initial permutation o1=[12 . . . n], namely, mainly performing an operation of {αo1}α=1n-1. Initial identity permutation requires no accumulation and can be transmitted directly to an output buffer, so that calculation of the set {αo1}α=1n-1 needs n−2 accumulations. Each positive integer adder is formed by m′ binary full-adders and an m′-bit B register, with m parallel input data lines and m′ parallel output data lines, and m<m′≤┌log2(n−1)2┐, an input of the binary full-adder is operable for receiving data from the input buffer, another input of the binary full-adder is connected to an output of the B register, and an output of the binary full-adder is connected to an input of the B register. As an enable signal E=1, each adder performs an addition between a last summation result (data in the B register) and an input of a corresponding parallel running input buffer (10), stores a result thereof in the B register and transmits the result to a corresponding parallel running mod n calculator (12); as the enable signal E=0, the n parallel running positive integer adders do not work.
The n parallel running mod n calculators (12) are operable for performing an operation of {αo1}α=1n-1(mod n), namely, performing mod n operations on data from the B register in the n parallel running positive integer adders, each mod n calculator is formed by a two-input single-output general mod n calculator, an m-bit C register and an m-bit D register, with m′ parallel input data lines and m parallel output data lines, an input of the general mod n calculator is connected to the output of the m′-bit B register through m′ parallel input data lines, another input of the general mod n calculator is connected to an output of the m-bit C register through m parallel output data lines, an output of the general mod n calculator is facilitated with m parallel output data lines, the m-bit C register is operable for storing and maintaining an m-bit binary value corresponding to n, the m-bit D register is operable for storing output values of said general mod n calculator, and a data |x| stored in the m-bit D register is output as it is not 0, otherwise a data stored in the m-bit C register is output.
The n parallel running output buffers (13) are formed by n m-bit registers, with the same structure as the n parallel running input buffers (10), operable for storing current orbit leader permutation, and as the (n−1)th buffer of the n parallel running output buffers (13) is prepared with current data, a signal is transmitted the first switch of the n-input single-output switch (14) so that this first switch is on.
The n-input single-output switch (14) is operable for serially transmitting each of the n data from the n parallel running output buffers (13) to a bus. m data lines of each output buffer are connected to an m-paralleled bus by a corresponding turn-on switch, the signal of closing a switch is transmitted to the first switch of the n-input single-output switch (14) as the (n−1) th buffer of the n parallel running output buffers is prepared with current data, and as the n th switch of the n-input single-output switch is on, the final data of a codeword is transmitted to the flash memory by the bus and a high level signal is transmitted to an input of the enable signal generator (15).
The enable signal generator (15) is operable for providing enable signals for the n parallel running positive integer adders (11) and formed by a binary plus 1 counter and a monostable flip-flop, with an input line and an output line which outputs a low level at a normal state, an input of the enable signal generator is connected to an output controlling signal line of the nth switch of the n-input single-output switch (14), an output of the enable signal generator is connected to enable terminals of the n parallel running positive integer adders (11), as the n th switch of the n-input single-output switch (14) is on, the enable signal generator (15) is enabled, the binary plus 1 counter performs an add-one operation, the monostable flip-flop generates a high level impulse with a width of a cp and transmits it to enable terminals of the n parallel running positive integer adders (11) to set E=1, and as the nth switch of the n-input single-output switch (14) is oft the enable signal generator (15) is disabled and E=0 is maintained. As the binary plus 1 counter performs n−1 add-one operations, the enable signal generator (15) outputs a low level.
The flash memory is shown in
In the flash memory (16), each element of a permutation is represented by an m-bit binary data, e.g. the first element of a permutation is represented by an m-bit binary data b1,1, b2,1, . . . , bm-1,1, bm,1, the last element of a permutation is represented by an m-bit binary data b1,n, b2,n, . . . , bm-1,n, bm,n, bi,j is binary 0 or 1, i=0, 1, . . . , m−1, and j=0, 1, . . . , n−1. m-bit binary data of an element of a permutation occupies m memory cells defined as an element storage word, a permutation occupies n element storage words, n−1 orbit leader permutations occupy n(n−1) element storage words, and n(n−1) permutation codewords occupy n2(n−1) element storage words. The flash memory (16) is facilitated with an m-bit parallel data input and an m-bit parallel data output. An m-bit data of an element storage word are input in parallel as Wr=1, an m-bit data of an element storage word are output in parallel as Rd=1, and the flash memory (16) is disabled as Wr=0 and Rd=0.
The cyclic-bidirectional-shift register group is shown in
Process a: input a permutation. As REG-in=0, REG-out=0 and Rd=1, the m parallel switches (18) of the cyclic-left-shift loops are disconnected, the first orbit leader permutation of the flash memory (16) is transmitted to the cyclic-bidirectional-shift register group (17), namely, the cyclic-bidirectional-shift register group performs an left-shift-input operation on m-bit binary in parallel in n times.
Process b: generate a new permutation by cyclic-left-shift. As REG-in=0 and REG-out=1, the m parallel switches (18) of the cyclic-left-shift loops are connected, and the cyclic-bidirectional-shift register group (17) performs a cyclic-left-shift operation on m-bit binary in parallel in n times to generate a new permutation.
Process c: output a permutation. As REG-in=1, REG-out=0 and Wr=1, the m parallel switches (18) of the cyclic-left-shift loops are connected, the cyclic-bidirectional-shift register group (17) performs the following two operations: transmitting a current permutation generated by Process b to the flash memory (16) by the left-shift-output operation on m-bit binary in parallel in n times, and performing a cyclic-left-shift operation on m-bit binary in parallel in n times, so that a permutation generated by Process b may be reserved.
Process d: generate an orbit {(l1)n-1oα}. It is formed by a combination of Process b and Process c with the m parallel switches (18) closed. Process b and Process c work alternately: this is that during an impulse of cp, REG-in=0 and REG-out=1, the cyclic-bidirectional-shift register group (17) performs a cyclic-left-shift operation of m-bit in parallel to generate a new permutation, and during each of the following n impulses of cp, REG-in=1, REG-out=0 and Wr=1, the cyclic-bidirectional-shift register group (17) simultaneously performs a left-shift operation to output a current permutation to the flash memory (16) for storage and a cyclic-left-shift operation to maintain this permutation by m-bit in parallel in n times. Process d is equivalent to performing an operation of (l1)n-1 on an orbit leader permutation oα to generate an orbit {(l1)n-1oα}, and storing n−1 permutations generated by the orbit {(l1)n-1oα} in the flash memory (16).
Process e: generate a code set {(l1)n-1On}. It is formed by a combination of Process a and Process d, and a code set {(l1)n-1On} of a (n,n(n−1),n−1) permutation group code based on coset partition is generated by repeating Process e for n−1 times.
Process b′: generate a new permutation by cyclic-right-shift. As REG-in=1 and REG-out=1, the m parallel switches (18) of the cyclic-left-shift loops are disconnected, and the cyclic-bidirectional-shift register group (17) performs a cyclic-right-shift operation on m-bit in parallel of length n to generate a new permutation.
Process d′: generate an orbit {(rn)n-1oα}. It is formed by a combination of Process b′ and Process c, equivalent to generating an orbit {(rn)n-1oα} of a permutation oα and storing the orbit {(rn)n-1oα} in the flash memory (16).
Process e′: generate a code set {(rn)n-1On}. It is formed by a combination of Process a and Process d′, and a code set {(rn)n-1On} of a (n,n(n−1),n−1) permutation group code based on coset partition is generated by repeating Process e′ for n−1 times.
While preferred embodiments of the invention have been described above, the invention is not limited to disclosure in the embodiments and the accompanying drawings. Any changes or modifications without departing from the spirit of the invention fall within the scope of the invention.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2016 1 0051144 | Jan 2016 | CN | national |
| Entry |
|---|
| A. J. Han Vinck, “Coded Modulation for Power Line Communications,” in AEU Journal, Jan. 2000, p. 45-49. |
| Number | Date | Country | |
|---|---|---|---|
| 20190165814 A1 | May 2019 | US |
| Number | Date | Country | |
|---|---|---|---|
| Parent | 15060111 | Mar 2016 | US |
| Child | 16263947 | US |
