Determination and particular use of error location polynomials

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CPC
H03M13/1525

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HELECTRICITY H03Electronic circuits H03MCODING DECODING CODE CONVERSION IN GENERAL H03M13/00Coding, decoding or code conversion, for error detection or error correction Coding theory basic assumptions Coding bounds Error probability evaluation methods Channel models Simulation or testing of codes

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H03M13/1525Determination and particular use of error location polynomials

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Patents Grantslast 30 patents

Information Patent Grant
Method for encoded diagnostics in a functional safety system
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- Issue date Oct 22, 2024
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- Issue date Nov 21, 2023
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Information Patent Grant
Method for encoded diagnostics in a functional safety system
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- Issue date Oct 17, 2023
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- Kerfegar Khurshed Katrak
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for multi-path mesh network communications
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- Issue date Aug 15, 2023
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Information Patent Grant
Error correction device and method for generating syndromes and par...
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Information Patent Grant
Method for encoded diagnostics in a functional safety system
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Information Patent Grant
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Information Patent Grant
Failure-tolerant error correction layout for memory sub-systems
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Information Patent Grant
ECC decoders having low latency
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Information Patent Grant
Method and devices for a reduced repair and update erasure code
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Method for controlling storage device with aid of error correction...
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Encoding method, encoder, and decoder for dynamic power consumption...
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Methods, systems, and computer-readable media for decoding a cyclic...
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- Issue date Nov 3, 2020
- Chongqing University of Posts and Telecommunications
- Yong Li
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Construction method for (n,n(n-1),n-1) permutation group code based...
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- Issue date Sep 1, 2020
- Huazhong University of Science and Technology
- Li Peng
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Methods, systems and computer-readable media for decoding cyclic code
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- Issue date Aug 11, 2020
- Chongqing University of Posts and Telecommunications
- Yong Li
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Error correction
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Method and decoder to adjust an error locator polynomial based on a...
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RS error correction decoding method
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Information Patent Grant
Reed-Solomon decoders and decoding methods
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- Issue date Oct 8, 2019
- Indian Institute of Science
- Shayan Srinivasa Garani
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Information Patent Grant
Method and associated decoding circuit for decoding an error correc...
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- Issue date Sep 3, 2019
- Silicon Motion Inc.
- Tsung-Chieh Yang
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Multi-bit error correction method and apparatus based on a BCH code...
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- Issue date Mar 26, 2019
- International Business Machines Corporation
- Yufei Li
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Information Patent Grant
Construction method for (n,n(n-1),n-1) permutation group code based...
- Patent number 10,230,397
- Issue date Mar 12, 2019
- Huazhong University of Science and Technology
- Li Peng
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Circuitry and method for decomposable decoder
- Patent number 10,230,399
- Issue date Mar 12, 2019
- Altera Corporation
- Martin Langhammer
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Decoding method, decoding apparatus and decoder
- Patent number 10,187,085
- Issue date Jan 22, 2019
- International Business Machines Corporation
- Cheng Wei Song
- H03 - BASIC ELECTRONIC CIRCUITRY

Patents Applicationslast 30 patents

Information Patent Application
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MEMORY SYSTEM AND CONTROL METHOD OF CONTROLLING NONVOLATILE MEMORY
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METHOD FOR ENCODED DIAGNOSTICS IN A FUNCTIONAL SAFETY SYSTEM
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- Fort Robotics, Inc.
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METHOD FOR ENCODED DIAGNOSTICS IN A FUNCTIONAL SAFETY SYSTEM
- Publication number 20230006697
- Publication date Jan 5, 2023
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- H03 - BASIC ELECTRONIC CIRCUITRY
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FAILURE-TOLERANT ERROR CORRECTION LAYOUT FOR MEMORY SUB-SYSTEMS
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ECC DECODERS HAVING LOW LATENCY
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- Publication date Nov 3, 2022
- SK HYNIX INC.
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- H03 - BASIC ELECTRONIC CIRCUITRY
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SYSTEM AND METHOD FOR MULTI-PATH MESH NETWORK COMMUNICATIONS
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ERROR CORRECTION DEVICE AND METHOD FOR GENERATING SYNDROMES AND PAR...
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ECC DECODERS HAVING LOW LATENCY
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FAILURE-TOLERANT ERROR CORRECTION LAYOUT FOR MEMORY SUB-SYSTEMS
- Publication number 20200177205
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METHOD FOR CONTROLLING STORAGE DEVICE WITH AID OF ERROR CORRECTION...
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- SILICON MOTION INC
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METHOD AND DEVICES FOR A REDUCED REPAIR AND UPDATE ERASURE CODE
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CONSTRUCTION METHOD FOR (n,n(n-1),n-1) PERMUTATION GROUP CODE BASED...
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- HUAZHONG UNIVERSITY OF SCIENCE & TECHNOLOGY
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- Publication date Mar 19, 2015
- RAMBUS INC.
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Determination and particular use of error location polynomials

Industry

Parent Industries

Current Industry

Patents Grantslast 30 patents

Method for encoded diagnostics in a functional safety system

System and method for multi-path mesh network communications

Failure-tolerant error correction layout for memory sub-systems

Memory system and control method of controlling nonvolatile memory

ECC decoders having low latency

Method for encoded diagnostics in a functional safety system

System and method for multi-path mesh network communications

Error correction device and method for generating syndromes and par...

Method for encoded diagnostics in a functional safety system

Processing of data

Failure-tolerant error correction layout for memory sub-systems

ECC decoders having low latency

Error correction of multiple bit errors per codeword

Method and devices for a reduced repair and update erasure code

Gel codeword structure encoding and decoding method, apparatus, and...

Method for controlling storage device with aid of error correction...

Encoding method, encoder, and decoder for dynamic power consumption...

Methods, systems, and computer-readable media for decoding a cyclic...

Construction method for (n,n(n-1),n-1) permutation group code based...

Methods, systems and computer-readable media for decoding cyclic code

Error correction

Method and decoder to adjust an error locator polynomial based on a...

Low-latency decoder for Reed Solomon codes

RS error correction decoding method

Reed-Solomon decoders and decoding methods

Method and associated decoding circuit for decoding an error correc...

Multi-bit error correction method and apparatus based on a BCH code...

Construction method for (n,n(n-1),n-1) permutation group code based...

Circuitry and method for decomposable decoder

Decoding method, decoding apparatus and decoder

Patents Applicationslast 30 patents

LOW GATE-COUNT AND HIGH THROUGHPUT REED-SOLOMON DECODING

SYSTEM AND METHOD FOR MULTI-PATH MESH NETWORK COMMUNICATIONS

MEMORY SYSTEM AND CONTROL METHOD OF CONTROLLING NONVOLATILE MEMORY

METHOD FOR ENCODED DIAGNOSTICS IN A FUNCTIONAL SAFETY SYSTEM

METHOD FOR ENCODED DIAGNOSTICS IN A FUNCTIONAL SAFETY SYSTEM

FAILURE-TOLERANT ERROR CORRECTION LAYOUT FOR MEMORY SUB-SYSTEMS

ECC DECODERS HAVING LOW LATENCY

SYSTEM AND METHOD FOR MULTI-PATH MESH NETWORK COMMUNICATIONS

ERROR CORRECTION DEVICE AND METHOD FOR GENERATING SYNDROMES AND PAR...

ECC DECODERS HAVING LOW LATENCY

FAILURE-TOLERANT ERROR CORRECTION LAYOUT FOR MEMORY SUB-SYSTEMS

METHOD FOR CONTROLLING STORAGE DEVICE WITH AID OF ERROR CORRECTION...

COSET PARTITION BASED CONSTRUCTION METHOD FOR (n,n(n-1),n-1) PERMUT...

METHOD AND DEVICES FOR A REDUCED REPAIR AND UPDATE ERASURE CODE

GEL CODEWORD STRUCTURE ENCODING AND DECODING METHOD, APPARATUS, AND...

ERROR CORRECTION OF MULTIPLE BIT ERRORS PER CODEWORD

METHODS, SYSTEMS AND COMPUTER-READABLE MEDIA FOR ERROR CORRECTION

METHODS, SYSTEMS, AND COMPUTER-READABLE MEDIA FOR DECODING A CYCLIC...

ON-LINE SELF-CHECKING HAMMING ENCODER, DECODER AND ASSOCIATED METHOD

ECC CIRCUIT, STORAGE DEVICE AND MEMORY SYSTEM

CONSTRUCTION METHOD FOR (n,n(n-1),n-1) PERMUTATION GROUP CODE BASED...

METHOD OF SIMILARITY TESTING BY SYNDROMES AND APPARATUS THEREFORE

DECODING METHOD, DECODING APPARATUS AND DECODER

ERROR CORRECTION

CIRCUITRY AND METHOD FOR DECOMPOSABLE DECODER

MULTI-BIT ERROR CORRECTION METHOD AND APPARATUS BASED ON A BCH CODE...

FAULT TOLERANT SYNDROME EXTRACTION AND DECODING IN BACON-SHOR QUANT...

FLEXIBLE PRBS ARCHITECTURE FOR A TRANSCEIVER

DATA PROCESSING BLOCK AND DATA STORAGE DEVICE INCLUDING THE SAME

Memory Module with Integrated Error Correction