Patent Application
20090164831
This invention relates to protection of settings that have been programmed into an integrated circuit device, and more specifically, to protection of one-time programmable default settings of OTP memories of ASICs.
U.S. Pat. No. 7,165,137 refers to a system for booting a microprocessor controlled system wherein a basic interface between the processor and peripheral devices is copied from an application and file storage device into random access memory without usage of the microprocessor or need for a non-volatile code storage device.
According to U.S. Pat. No. 5,454,114 a microcontroller is selectively reset to prevent it from executing programs and instructions for purposes of generating control signals, and is maintained in the reset condition despite initiation of a removal from the reset condition, until the power supplied by the power supply is in a predetermined range and the clock frequency supplied by the clock is stable.
The invention relates to control of OTP default settings, including OTP security protection measures that have been programmed into an OTP Memory block of an ASIC semiconductor chip. The invention provides a time delay, according to which a Chip Logic Block and its internal ASIC or microprocessor, or both, whichever are present, are delayed ftom going to inactive reset, until the OTP Memory and chip at inactive reset are configured to their fully operational modes.
An External Reset device is used to read one-time programmable (OTP) memories with OTP bit (byte) contents in the form of fixed default settings of parameters to control the operation of the OTP memories, such as, electronic serial numbers (ESN), feature controls and preset adjustable constants for complex algorithms. Additional default settings programmed into the OTP memories include security protection measures, such as, write and erase protection and unauthorized access protection. After removal of the External Reset device, the OTP Memory is available for power-up to an operational mode.
Further, after power-up is internally applied to an OTP Memory, the controller of the OTP Memory actively interfaces with a system microprocessor that takes control of system operation. The processor speed can re-boot and take control of system operation faster than the time it takes for the OTP Memory to read out its OTP contents, which includes one-time programmed default settings and programmed security protection measures. Consequently, an interval of time occurs during which the processor can operate the system using incorrectly read default settings, and can subvert the security protection measures. The OTP memory is vulnerable to external control signals that could override the intended purpose of one or more OTP bits. For example, the purpose of an OTP bit that modifies a boot memory map such that an external memory blocked from use can be subverted by external control signals. Thus, protection is desired for protecting the OTP contents until read-out of the OTP contents is completed.
The ASIC chip 100 has a Chip Logic block 106,
Before the OTP Memory block 200 is fully operational, the memory settings can be read-out completely over the internal OTP Data/Controls signals 202, especially during clock driven reset of the ASIC chip 100. Thus, once set, all such memory settings can be protected during the time it takes for the OTP Memory block 200 to complete its read out of such memory settings. An embodiment of the invention provides such protection without a need to invoke or rely upon the power-up reset and re-boot procedures internal to a system microprocessor. According to an embodiment of the invention, the memory settings are protected by a diode-free, OTP and Reset Assert Counter 204. The OTP and Reset Assert Counter 204, being diode-free, reduces the overall cost of construction, speeds up the switching times compared to that of diodes, and reduces power consumption that would be consumed by diodes.
Typically, the ASIC chip 100 is an external device that is part of an electronic system, not shown, under the control of a system microprocessor having an operational speed that attains full power-up and begins executing system commands before the slower speed, OTP Memory block 200 has completed its read-out of the OTP Memory settings. A partially completed read-out of the memory settings is likely to result. Thereby, the read-out memory settings of the OTP Memory block 200 are vulnerable to being incorrect, since they have not fully completed their read-out cycle, and the security protection measures in memory are vulnerable to being rendered ineffective as security protection, since they have not fully completed their read-out cycle. Moreover, the system microprocessor would begin executing error-prone commands which have relied on incorrectly read-out memory settings of the OTP Memory block 200.
Moreover, as disclosed by
In the OTP and Reset Assert Counter 204 the RSTB signal 102 is at ground (LOW state) true active, such that, the RSTB signal 102 at ground true active sets all of the internal circuits in the Delay Counter 206, the OTP Memory block 200 and the Chip Logic block 106, respectively, in an Active Reset mode at LOW. While in the Active Reset mode, the OTP Memory block 200 is in standby mode, and is not reading out the memory settings, including other memory contents thereof. Further, while in Active Reset mode the Delay Counter 206 and the Chip Logic block 106 are in standby mode and are not operational.
During an Active Reset mode, the OTP Memory block 200 is programmed with the memory settings and other memory contents by an external programming apparatus, not shown. At completion of the Active Reset mode the external programming apparatus is removed and the Active Reset mode is terminated.
The External Reset RSTB signal 102 goes HIGH, relative to ground, when the Active Reset mode is terminated, or for example, when set to HIGH under the control of a systems microprocessor of an electronic system of which the ASIC chip 100 is a part. Thus, the Delay Counter 206 goes HIGH and begins the time delay 300. The OTP Memory block 200 goes HIGH to self-initiate a beginning of the read-out process during the time delay 300 and driven by the clock driven, External Reset (RSTB) signal. The read-out process involves a read-out of the memory settings, including other memory contents, which output on the internal OTP Data/Control signal 202. The OTP Memory block 200 completes the read-out of its memory settings during the time delay 300, such that when the read-out of the OTP Memory block 200 is completed and output on the internal OTP Data/Control signal 202, the OTP Memory block 200 has become fully configured during the time delay 300, and the Chip Logic block 106 has become fully configured by the OTP data/control signals during the time delay 300.
During the time delay 300 the OTP Memory block 200 completes the read-out of its memory settings, including other memory contents. Additionally, at the end of the time delay 300, the Delay Counter 206 releases the input Clock signal 104 to provide the Internal Reset clock signal 212 set at HIGH, and to set the Chip Logic block at HIGH with the Internal Reset clock signal 212 set at HIGH, and wherein the Internal Reset clock signal 212 begins clock timing of the Chip Logic block 106 after the Chip Logic block has been fully configured during the time delay 300.
At any time later wherein the RSTB signal 102 is set to ground true active, for example, while under control of the system CPU, the RSTB signal 102 supplied to the Delay Counter 206 immediately sets the Delay Counter 206 to ground, which, in turn, sets the Internal Reset signal 212 to ground and the Chip Logic Block 106 to ground. Further, the RSTB signal 102 supplied to the OTP Memory block 200 immediately sets the OTP Memory block 200 to ground, causing the OTP Memory block 200 to reset and remain in reset mode.
Advantageously, the present invention provides memory read-out protection while attaining a fully configured OTP Memory block 200 and a fully configured Chip Logic block 106 without the use of diodes. According to an embodiment of the invention, the memory settings are protected by a diode-free, OTP and Reset Assert Counter 204. The OTP and Reset Assert Counter 204, being diode-free, reduces the overall cost of construction, speeds up the switching times compared to that of diodes, and reduces power consumption that would be consumed by diodes.
This description of the exemplary embodiments is intended to be read in connection with the accompanying drawings, which are to be considered part of the entire written description. In the description, relative terms such as “lower,” “upper,” “horizontal,” “vertical,”, “above” “below” “up,” “down,” “top” and “bottom” as well as derivative thereof (e.g., “horizontally,” “downwardly,” “upwardly,” etc.) should be construed to refer to the orientation as then described or as shown in the drawing under discussion. These relative terms are for convenience of description and do not require that the apparatus be constructed or operated in a particular orientation. Terms concerning attachments, coupling and the like, such as “connected” and “interconnected,” refer to a relationship wherein structures are secured or attached to one another either directly or indirectly through intervening structures, as well as both movable or rigid attachments or relationships, unless expressly described otherwise.
Although the invention has been described in terms of exemplary embodiments, it is not limited thereto. Rather, the appended claims should be construed broadly, to include other variants and embodiments of the invention, which may be made by those skilled in the art without departing from the scope and range of equivalents of the invention.
