Claims
- 1. A semiconductor memory device, comprising:
- a semiconductor substrate;
- a trench formed in said semiconductor substrate;
- conductive material formed in said trench and insulatively spaced from semiconductor substrate to form a capacitor;
- a transfer gate transistor including source/drain regions formed on a surface of said semiconductor substrate and a control gate insulatively spaced from a channel region between said source/drain regions; and
- a buried strap electrically connecting said capacitor to one of said source/drain regions of said transfer gate transistor, a portion of said buried strap comprising recrystallized silicon.
Parent Case Info
This application is a division of application Ser. No. 08/412,442, filed Mar. 29, 1995, now U.S. Pat. No. 5,543,348.
US Referenced Citations (25)
Non-Patent Literature Citations (1)
Entry |
Nesbit et al., A 0.6 um.sup.2, 256 Mb Trench DRAM Cell With Self-Aligned BuriEd STrap (BEST), IEDM 93-627-630 no date. |
Divisions (1)
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Number |
Date |
Country |
Parent |
412442 |
Mar 1995 |
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