Patent Application
20250239937
This specification describes example implementations of techniques for controlling a power supply, such as a switched-mode power supply.
A switched-mode power supply (SMPS) is a power supply that is configured to switch current to a load on and off in order to produce an output voltage. An example SMPS includes switches, which may be implemented using transistors, that open and close at a relatively high frequency. This operation of the switches connects and disconnects an energy storage system to and from the load in order to switch the current and thereby produce a direct current (DC) output voltage to the load.
An example system includes a switched mode power supply to provide an output voltage. The output voltage includes a predefined voltage and a droop or kick voltage that deviates from the predefined voltage. Control circuitry is configured to control the switched mode power supply based on a first voltage and a second voltage to reduce the droop or kick voltage at least partly. The control circuitry includes first circuitry including digital circuitry configured to obtain the first voltage based on the output voltage, and second circuitry including analog circuitry configured to obtain the second voltage based on the output voltage. The system may include one or more of the following features, either alone or in combination.
The first circuitry may operate at a first speed and the second circuitry may operate at a second speed. The second speed may be greater than the first speed. The first circuitry may include a feedback circuitry and the second circuitry may include feedforward circuitry. The first circuitry may include a proportional-integral-derivative (PID) controller. The PID controller may be configured to obtain the output voltage and to output a third voltage that is based on the output voltage and a reference voltage. The first voltage may be based on the third voltage.
The system may include an inverting summing amplifier configured to sum a version of (e.g., an inversion of) the first voltage and the second voltage to produce a summed voltage. The control circuitry may be configured to control the switched mode power supply using the summed voltage. The second circuitry may include a notch filter to remove undesired switched mode power supply ripple voltage and to output a fourth voltage. The second circuitry may include at least one non-inverting differentiator configured to differentiate the fourth voltage to produce the second voltage. The second voltage may be a version of the fourth voltage having an increased slope. The at least one non-inverting differentiator may include two or more non-inverting differentiators each configured to differentiate the fourth voltage to produce a respective second voltage. Each respective second voltage may be based on the fourth voltage and may have an increased slope relative to the fourth voltage. The inverting summing amplifier may be configured to receive each respective second voltage.
The system may include a non-inverting summing amplifier (e.g., instead of an inverting summing amplifier) that is configured to sum the first voltage and a version of (e.g., an inversion of) the second voltage to produce a summed voltage. The control circuitry may be configured to control the switched mode power supply using this summed voltage. The second circuitry may include a notch filter to remove undesired switched mode power supply ripple voltage and to output a fourth voltage. The second circuitry may include at least one inverting differentiator configured to differentiate the fourth voltage to produce the second voltage. The second voltage may be a version of the fourth voltage having an increased slope. The at least one inverting differentiator may include two or more inverting differentiators each configured to differentiate the fourth voltage to produce a respective second voltage. Each respective second voltage may be based on the fourth voltage and may have an increased slope relative to the fourth voltage. The non-inverting summing amplifier may be configured to receive each respective second voltage.
The control circuitry may be configured to control the switched mode power supply to counteract the droop or kick voltage by 50% or more. The system may be part of automatic test equipment (ATE) configured to test a device under test (DUT). The DUT may be powered based on the output voltage. The system may include a power distribution network that includes one or more cables between the switched mode power supply and the DUT.
An example method includes the following operations: generating an output voltage using a switched mode power supply, where the output voltage includes a predefined voltage and a droop or kick voltage that deviates from the predefined voltage; obtaining a first voltage that is based on the output voltage, where the first voltage is obtained at a first speed; obtaining a second voltage that is based on the output voltage, where the second voltage is obtained at a second speed that is greater than the first speed; and controlling the switched mode power supply based on the first voltage and the second voltage to counteract the droop or kick voltage at least partly. The example method may include one or more of the following features, either alone or in combination.
Controlling the switched mode power supply may include the following operations: generating a summed voltage that is based on the first voltage and the second voltage; and using the summed voltage to control the switched mode power supply. Counteracting the droop or kick voltage may include reducing the droop or kick voltage by 50% or more.
The output voltage may be associated with a device powered by the switched mode power supply. Controlling the switched mode power supply based on the first voltage may be performed using feedback circuitry. Controlling the switched mode power supply based on the second voltage may be performed using feedforward circuitry. The feedback circuitry may be or include digital circuitry and the feedforward circuitry be or include analog circuitry.
Any two or more of the features described in this specification, including in this summary section, may be combined to form implementations not specifically described in this specification.
At least part of the devices, systems, and processes described in this specification may be configured or controlled by executing, on one or more processing devices, instructions that are stored on one or more non-transitory machine-readable storage media. Examples of non-transitory machine-readable storage media include read-only memory, an optical disk drive, memory disk drive, and random access memory. At least part of the devices, systems, and processes described in this specification may be configured or controlled using a computing system comprised of one or more processing devices and memory storing instructions that are executable by the one or more processing devices to perform various control operations. The devices, systems, and processes described in this specification may be configured, for example, through design, construction, composition, arrangement, placement, programming, operation, activation, deactivation, and/or control.
The details of one or more implementations are set forth in the accompanying drawings and the following description. Other features and advantages will be apparent from the description and drawings, and from the claims.
Like reference numerals in different figures indicate like elements.
Some power supplies, such as a switched-mode power supply (SMPS), produce a kick or droop voltage during operation. In an example, an SMPS is configured to produce a steady-state output voltage (VOUT) having a predefined magnitude, such as a direct current (DC) voltage. However, in some SMPSs, the output voltage deviates from the predefined magnitude in either the positive or negative direction, particularly when the SMPS begins operation. A positive deviation is referred to as a kick voltage and a negative deviation is referred to as a droop voltage. An example of a droop voltage 10 is shown in
Nevertheless, the droop or kick voltage can adversely affect operation of a device powered by the SMPS. For example, an electronic device under test (DUT), such as a microprocessor or consumer electronic device, may be intended to operate at the output voltage. A voltage in excess of, or below, the output voltage may affect device operation and/or results of testing performed on the DUT. Accordingly, the example systems and processes described herein are configured to reduce the droop or kick voltage at least partly including, but not limited to, during testing.
An example system includes control circuitry configured to control the SMPS to generate the output voltage. At least initially, the output voltage from the SMPS includes a droop or kick voltage. The control circuitry includes digital circuitry, which may include feedback circuitry, configured to obtain a first voltage based on the output voltage. The control circuitry also includes analog circuitry, which may include feedforward circuitry, configured to obtain a second voltage based on the output voltage. The system uses the first voltage and the second voltage to reduce the magnitude and/or duration of the droop or kick voltage.
For example, the control circuitry controls the SMPS using a combination of the first voltage and the second voltage. In some examples, the analog circuitry is configured to function at a greater speed than the digital circuitry, at least in part because the analog circuitry need not take time to execute instructions to function. The analog circuitry is configured to detect the droop or kick voltage in the output voltage and to generate the second voltage to compensate for—for example, to counteract or reduce, fully or at least partly—the droop or kick voltage at the output of the SMPS. The digital circuitry is also configured to generate the first voltage to compensate for—for example, to counteract or to reduce, fully or at least partly—at least part of the droop or kick voltage not compensated for by the second voltage.
By using analog circuitry to at least partly the control the SMPS, the systems and processes described herein may counteract or reduce at least part of the droop or kick voltage in the output voltage more quickly than in systems and process that use digital control alone. This is advantageous at least because it may reduce the time that a device powered by the SMPS is subjected to droop or kick voltage. This is advantageous at least because it may reduce the magnitude of the droop or kick voltage that a device powered by the SMPS is subjected to.
In this regard, counteracting or reducing the droop or kick voltage may include eliminating the droop or kick voltage entirely, reducing a magnitude of the droop or kick voltage without eliminating the droop or kick voltage entirely, reducing a duration of the droop or kick voltage without eliminating the droop or kick voltage entirely, or reducing a magnitude and a duration of the droop or kick voltage without eliminating the droop or kick voltage entirely. In some implementations, the control circuitry is configured to control the SMPS to counteract the droop or kick voltage by reducing a magnitude and/or duration of the droop or kick voltage 50% or more, 40% or more, 30% or more 25% or more, 20% or more, 10% or more, and so forth.
In this example, DUT 17 is shown as including a capacitor bank 19 and a load 20. Capacitor bank 19 includes one or more capacitors that are to be charged by current from SMPS 16. In some implementations, another energy storage device, such as one or more inductors may be used instead of capacitor bank 19. Capacitor bank 19 provides voltage to the load, which includes operational circuits within DUT 17. In some implementations, control circuitry 15 measure VOUT along a power distribution path 21 that electrically connects capacitor bank 19 to load 20. The droop or kick voltage in the output voltage (VOUT) appears at this location. In some implementations, control circuitry 15 may measure VOUT along a power distribution path 22 that precedes capacitor bank 19 (not shown). This may be done, for example, if the DUT does not include a separate capacitor bank or energy storage device, or one that is externally accessible. The droop or kick voltage in the output voltage appears at this location. In general, the droop or kick voltage in the output voltage may be measured at any location where the droop or kick voltage appears in the output voltage.
System 14 also includes a power distribution network (PDN) 22. PDN 22 may include one or more power cables configured and arranged to transport power—including voltage and current—from SMPS 16 to capacitor bank 19. In some implementations, PDN 22 includes one or more switches, relays, or other active and/or passive electronic devices between SMPS 16 and capacitor bank 19.
Control circuitry 15 includes feedback circuitry 24. Feedback circuitry 24 includes digital circuitry 25 configured to generate a first control signal 26 to control SMPS 16 to reduce the droop or kick voltage. Control circuitry 15 also includes feedforward circuitry 27. Feedforward circuitry 27 includes analog circuitry configured to generate a second control signal 29 to control SMPS 16 to reduce the droop or kick voltage. Operation of digital circuitry 25 is relatively slow for reasons explained above and, in some implementations, will not respond to reduce the droop or kick voltage for one or more milliseconds (ms). Operation of the analog circuitry is relatively fast and, in some implementations, will respond to reduce the droop or kick voltage in a time period measured in single-digit microseconds (μs), such as 1 μs, or less.
In this example, digital circuitry 25 includes a digital microcontroller. The digital microcontroller may include an analog-to-digital converter (ADC) 30 configured to detected VOUT and to convert VOUT into digital form, and a discrete controller 31, such as a proportional-integral-derivative (PID) controller. An example PID controller 31 is configured to repetitively determine an error value (ERROR) 34 as a difference between a predefined voltage value (here, VREF) 35 and a measured value, such as the digitized version of the output voltage, VOUT, 36. VREF may be programmed via software/firmware into the digital controller. PID controller 31 is configured to apply a correction value that is based on proportional, integral, and derivative terms in order to reduce or to minimize the error. In this example, PID controller 31 may measure and process the measured value of VOUT and VREF over time to generate the first voltage-based control signal (VCONTROL) 26. A version of this control signal, VCONTROL, which may be the actual control signal or an inverted version thereof, is combined with a second control signal from feedforward circuitry 27 to control operation of SMPS 16—for example, to control the current output of SMPS 16—so that the droop of kick voltage is reduced.
In some implementations, PID controller 31 may be replaced with a P (proportional) controller, with a PI (proportional-integral) controller, or with any other appropriate type of digital controller.
In this example, feedback circuitry 24 also includes an inverting amplifier 37, such as an operational amplifier, which may be analog circuitry, and which may be configured to invert the control signal, VCONTROL. In this example, the inverting amplifier does not apply a gain to the control signal, VCONTROL, but rather only inverts the control signal, VCONTROL, and hence is labeled “−1”. The inversion is performed in this example because summing amplifier 44 described below inverts signals. This results in a double inversion to generate a signal having the correct polarity to apply to SMPS 16.
Control circuitry 15 also includes feedforward circuitry 27. Circuitry 27 is considered to be feedforward circuitry because circuitry 27 does not compare its input, namely the analog VOUT, to a reference voltage. Rather, the output of circuitry 27 is a second voltage-based control signal, VAMPLIFIED, 29 which is a product of a gain of the feedforward circuitry and its input, namely analog VOUT. In some implementations, a version of this control signal, VAMPLIFIED, is combined with a version of the first control signal, VCONTROL, to control operation of SMPS 16—for example, to control the current output of SMPS 16—so that the droop of kick voltage is reduced. Is some implementations, the feedforward circuitry may over-correct the droop or kick voltage at least initially, but this over-correction may be corrected by feedback circuitry 24.
In this example, the analog circuitry in feedforward circuitry 27 includes a differential sense amplifier 39 to measure the output voltage, VOUT. Feedforward circuitry 27 also includes a passive notch filter 40, which is configured to remove any switching ripple from SMPS 16 in the measured voltage, VOUT. An example notch filter 40 includes a band-stop filter, which is a filter that attenuates frequencies within a specific range while passing other frequencies unaltered. Notch filter 40 outputs a filtered version of VOUT, namely, VOUT_FILTER, 41 in which voltage ripple from SMPS 16 has been eliminated or reduced. In some implementations, VOUT_FILTER includes the droop or kick voltage only.
In this example, feedforward circuitry 27 also includes one or more non-inverting differential operational amplifier(s) 42. A non-inverting differential amplifier outputs a signal based on a rate of change of VOUT, particularly the droop or kick voltage. In this regard, the droop or kick voltage may be relatively shallow which, absent differentiation, could dilute their effect(s) on the control signal, VAMPLIFIED. In this example, non-inverting differential amplifier 42 amplifies the contribution of droop or kick voltage in the control signal, VAMPLIFIED, by determining the slope of the droop or kick voltage through differentiation and using the slope of the drop or kick voltage as, or to generate, VAMPLIFIED. In some implementations, the non-inverting differential amplifier 42 amplifies the droop or kick voltage using a predefined gain that is configured into the non-inverting differential amplifier. The control signal, VAMPLIFIED, thus is or includes an amplified signal that is based on the droop or kick voltage.
In some implementations, feedforward circuitry 27 may include one non-inverting differential amplifier 42. In some implementations, feedforward circuitry 27 may include multiple non-inverting differential amplifiers 42, such as two, three, four, five, or more non-inverting differential amplifiers 42 configured to operate in parallel. This may be because the non-inverting differential amplifiers have a limited slew rate, which can slow operation of the analog circuitry that makes up feedforward circuitry 27. In this regard, the slew rate is the maximum rate of change of a differential amplifier's voltage. By using multiple differential amplifiers in parallel, the effects of this limited slew rate can be mitigated, since each operational amplifier need perform less amplification without a corresponding reduction in the time that the amplification is to be performed. By way of example, each such non-inverting differential amplifier 42 is configured to receive the control signal, VOUT_FILTER, and to output a version of the control signal, VAMPLIFIED. In some implementations, the magnitude of each control signal, VAMPLIFIED may be inversely proportional to the number of non-inverting differential amplifiers 42 in feedforward circuitry 27. For example, if there is one non-inverting differential amplifier 42, then VAMPLIFIED is not attenuated. For example, if there are two non-inverting differential amplifiers 42 operating in parallel, then each non-inverting differential amplifier 42 is configured to output a control signal having a magnitude of VAMPLIFIED/2. For example, if there are three non-inverting differential amplifiers 42 operating in parallel, then each non-inverting differential amplifier 42 is configured to output a control signal having a magnitude of VAMPLIFIED/3; and so forth. VAMPLIFIED, or multiple instances of VAMPLIFIED/2, or multiple instances of VAMPLIFIED/3, and so forth, are output to summing amplifier 44, as described below.
In some implementations, control circuitry 25 includes an inverting summing amplifier 44 that receives an inverted version of the output (the first control signal 26, VCONTROL) of feedback circuitry 24 and the output (the second control signal 27, VAMPLIFIED) of feedforward circuitry, which has not been inverted. Inverting summing amplifier 44 is configured to merge or to combine—for example, to sum—the inverted version of the first control signal, VCONTROL and the second control signal, VAMPLIFIED, and to invert the resulting sum to produce a voltage-based control signal, VCONTROL_NEW. The control signal VCONTROL_NEW is applied to SMPS 16 to control operation of SMPS 16 so that the droop or kick voltage portion of VOUT is reduced.
Referring to
In
In this example, the error value (ERROR 34 of
In implementations where SMPS 16 produces a kick voltage, the signals in
In this regard,
In implementations where SMPS 16 produces a kick voltage, the signals in
Process 67 includes generating (67a) an output voltage, such as a voltage applied to a DUT, using an SMPS 16. The output voltage, such as VOUT, includes a predefined voltage and a droop or kick voltage that deviates from the predefined voltage. Process 67 includes obtaining (67b) a first voltage, such as VCONTROL or an inverted version of VCONTROL, that is based on the output voltage, such as VOUT. The first voltage is obtained using digital feedback circuitry 24 at a first speed, which may be one or more milliseconds or greater. Process 67 obtains (67c) a second voltage, such as VAMPLIFIED or an inverted version of VAMPLIFIED, that is based on the output voltage, such as VOUT. The second voltage is obtained by analog feedforward circuitry 27 at a second speed that is greater than the first speed, where the second speed may be on the order of single-digit microseconds (μs), such as 1 μs, or less. Process 67 includes controlling (67d) the SMPS based on the first voltage and the second voltage to counteract the droop or kick voltage at least partly. Controlling the SMPS may include generating a summed voltage that is based on the first voltage and the second voltage. For example, the summed voltage may be an inverted sum of: VAMPLIFIED and an inverted version of VCONTROL. For example, the summed voltage may be a sum of: VCONTROL and an inverted version of VAMPLIFIED. The summed voltage is a control signal that is applied to the SMPS to control the output of the SMPS to counteract—for example, to reduce the magnitude and/or duration of—the droop or kick voltage in (that is, the droop or kick component of) the output voltage (VOUT).
The control circuitry 15 of
ATE 70 includes a test head 73 and a device interface board (DIB) 74 connected physically and electrically to test head 73. In this example, DIB 74 includes a circuit board that includes mechanical and electrical interfaces at sites 75. One or more DUTs 76 connect to each of those sites for testing by the ATE. DIB 74 may include, among other things, connectors, conductive traces, conductive layers, and circuitry for routing signals between test instruments in the test head 73, DUTs connected to DIB sites, and other circuitry in the ATE. Power, including voltage, may be run, e.g., from one or more SMPSs, via one or more layers in the DIB to DUTs connected to the DIB.
Test head 73 includes multiple test instruments 76a to 76n (where n>3), each of which may be configured, as appropriate, to implement testing and/or other functions. Although only four test instruments are shown, ATE 70 may include any appropriate number of test instruments, including one or more residing outside of test head 73. The test instruments may be hardware devices that may include one or more processing devices and/or other circuitry 77. The test instruments may be configured—for example, programmed—to output test signals to test DUTs held on the DIB. The test signals to test the DUTs may be or include commands, instructions, data, parameters, variables, test patterns, and/or any other information designed to elicit response(s) from the DUT. Each test instrument may have a configuration like that of test instrument 76n, which includes one or more processing devices 77 for executing instructions to generate test signals to send to the DUTs, to communicate with control system 71, and to analyze responses to the test signals. In some implementations, one or more of (for example each of) the test instruments may include an SMPS 16 and control circuitry 15, 55 like that of
In some implementations, test signals to test a DUT may be generated by test program(s) received by ATE 70 from an external system. In an example, a test program may be or include a set of instructions that are executed or interpreted by ATE 70 to produce test signals that the ATE uses to test the DUT.
Test channels 79 are configured between the test head and the DIB to enable communication between the DUTs and the test instruments.
Control system 71 is configured—e.g., programmed—to communicate with test instruments 76a to 76n to direct and/or to control testing of the DUTs. In some implementations, this communication 80 may be over a computer network or via a direct connection such as a computer bus or an optical medium. In some implementations, the computer network may be or include a local area network (LAN) or a wide area network (WAN). The control system may be or include a computing system comprised of one or more processing devices 81 (e.g., microprocessor(s)) and memory 82 for storing instructions to execute to control operation of the ATE and/or testing, and/or one or more test programs to execute and/or to send to the test instruments for execution. Control system 71 may be configured to provide test programs and/or test signals to test instruments 76a to 76n in the test head, which the test instrument(s) use to test the DUT. Control system 71 may also be configured to receive DUT response signals (e.g., measurement data) from the test instrument(s) and to determine whether the corresponding DUT has passed or failed testing.
In some implementations, the control functionality is centralized in processing device(s) 81. In some implementations, all or part of the functionality attributed to control system 71 may also or instead be implemented on a test instrument and/or all or part of the functionality attributed to one or more test instruments may also or instead be implemented on control system 71. For example, the control system may be distributed across processing device(s) 81 and one or more of test instruments 76a to 76n.
In some implementations, the control system may program VREF into PID controller 71. VREF may be changed by the control system, for example, if the control system 71 controls an SMPS 16 to provide a different value of VOUT.
All or part of the systems and processes described herein including but not limited to process 67 and its modifications may be configured and/or controlled at least in part by one or more computers using one or more computer programs tangibly embodied in one or more information carriers, such as in one or more non-transitory machine-readable storage media. A computer program can be written in any form of programming language, including compiled or interpreted languages, and it can be deployed in any form, including as a stand-alone program or as a module, part, subroutine, or other unit suitable for use in a computing environment. A computer program can be deployed to be executed on one computer or on multiple computers at one site or distributed across multiple sites and interconnected.
Actions associated with configuring or controlling the test system and processes described herein can be performed by one or more programmable processors executing one or more computer programs to control or to perform all or some of the operations described herein. All or part of the test systems and processes can be configured or controlled by special purpose logic circuitry, such as, an FPGA (field programmable gate array) and/or an ASIC (application-specific integrated circuit) or embedded microprocessor(s) localized to the instrument hardware.
Processors suitable for the execution of a computer program include, by way of example, both general and special purpose microprocessors, and any one or more processors of any kind of digital computer. Generally, a processor will receive instructions and data from a read-only storage area or a random access storage area or both. Elements of a computer include one or more processors for executing instructions and one or more storage area devices for storing instructions and data. Generally, a computer will also include, or be operatively coupled to receive data from, or transfer data to, or both, one or more machine-readable storage media, such as mass storage devices for storing data, such as magnetic, magneto-optical disks, or optical disks. Non-transitory machine-readable storage media suitable for embodying computer program instructions and data include all forms of non-volatile storage area, including by way of example, semiconductor storage area devices, such as EPROM (erasable programmable read-only memory), EEPROM (electrically erasable programmable read-only memory), and flash storage area devices; magnetic disks, such as internal hard disks or removable disks; magneto-optical disks; and CD-ROM (compact disc read-only memory) and DVD-ROM (digital versatile disc read-only memory).
As used herein, the terms “comprises,” “comprising,” “includes,” “including,” “has,” “having,” “contains,” “containing,” and any variations thereof, are intended to cover a non-exclusive inclusion, such that systems, techniques, apparatus, structures, processes, or other subject matter described or claimed herein that includes, has, or contains an element or list of elements does not include only those elements but can include other elements not expressly listed or inherent to such systems, techniques, apparatus, structures, processes or other subject matter described or claimed herein.
All examples described herein are non-limiting.
In the description and claims provided herein, the adjectives “first”, “second”, “third”, and the like do not designate priority or order unless context suggests otherwise. Instead, these adjectives may be used solely to differentiate the nouns that they modify.
Any mechanical or electrical connection herein may include a direct physical connection or an indirect physical connection that includes one or more intervening components unless context suggests otherwise. A connection between two electrically conductive components includes an electrical connection unless context suggests otherwise. The signals described herein are electrical signals unless context suggests otherwise.
Elements of different implementations described may be combined to form other implementations not specifically set forth previously. Elements may be left out of the systems described previously without adversely affecting their operation or the operation of the system in general. Furthermore, various separate elements may be combined into one or more individual elements to perform the functions described in this specification.
Other implementations not specifically described in this specification are also within the scope of the following claims.
