Patent Application
20230205521
In recent years fused-multiply-add (FMA) units with lower-precision multiplications and higher-precision accumulation have proven useful in machine learning/artificial intelligence applications, most notably in training deep neural networks due to their extreme computational intensity. Compared to classical IEEE-754 32-bit (FP32) and 64-bit (FP64) arithmetic, this reduced precision arithmetic can naturally be sped up disproportional to their shortened width.
Various examples in accordance with the present disclosure will be described with reference to the drawings, in which:
The present disclosure relates to methods, apparatus, systems, and non-transitory computer-readable storage media for converting data elements in response to an instruction.
In contrast to the IEEE 754-standardized 16-bit (FP16) variant, BF16 does not compromise on range when being compared to FP32. FP32 numbers have 8 bits of exponent and 24 bits of mantissa (including the one implicit). BF16 cuts 16 bits from the 24-bit FP32 mantissa to create a 16-bit floating point datatype. In contrast FP16, roughly halves the FP32 mantissa to 10 explicit bits and reduces the exponent to 5 bits to fit the 16-bit datatype envelope.
Although BF16 offers less precision than FP16, it is typically better suited to support deep learning tasks. FP16's range is not enough to accomplish deep learning training out-of-the-box due to its limited range. BF16 does not suffer from this issue and the limited precision may actually help to generalize the learned weights in the neural net training task. In other words, lower precision can be seen as offering a built-in regularization property.
Not all processors have support for all data types. For example, in some examples, the execution circuitry detailed below does not have FP16 and/or BF16 execution support. In other words, the execution circuitry cannot natively work with these formats and the conversion to FP32 allows for the execution circuitry to be able to handle previously unsupported data types. As such, there is not the need to build out support for FP16 and/or BF16 which takes up area and may consume more power. Detailed herein are examples of instructions, and their support, which convert at least one BF16 or FP16 data element of a source into a FP32 data element and store that FP32 data element into one or more data element positions of a destination. There is no known instruction take a BF16 value stored at a memory location and store that value into an upper half of each PS data element of a destination.
An example of a format for a convert a BF16 value from a source into a FP32 value and store that FP32 value in one or more data elements of a destination instruction is VBCSTNEBF162PS DESTINATION, SOURCE. In some examples, VBCSTNEBF162PS is the opcode mnemonic of the instruction. DESTINATION is one or more fields for the packed data destination register operand. SOURCE is one or more fields for a source such as packed data registers and/or memory location. Note that PS in the opcode mnemonic represents single precision or FP32. Additionally, note that a different mnemonic may be used, but VBCSTNEBF162PS is used in this discussion as a shortcut. In some examples, the source memory location is provided using at least R/M field 1746 (and in some examples, using the MOD field 1742) and the destination register is provided using register field 1744.
As shown, the execution of a decoded VBCSTNEBF162PS instruction causes a BF16 data element from a packed data source (shown here as memory) 201 to be read and then broadcast using broadcast circuitry 211 of execution circuitry 213 or memory access circuitry 215 into the upper half of one or more packed FP32 data element of the packed data destination 231 while causing the lower half of each written packed FP32 data element of the packed data destination 231 to be zeroed. This creates a FP32 value having the lower 16 bits of the fraction being zero.
In some examples, the execution of this instruction uses a “round to nearest (even)” rounding mode. In some examples, output denormals are always flushed to zero and input denormals are always treated as zero.
An example of a format for a convert a FP16 value from a source into a FP32 value and store that FP32 value in one or more data elements of a destination instruction is VBCSTNESH2PS DESTINATION, SOURCE. In some examples, VBCSTNESH2PS is the opcode mnemonic of the instruction. DESTINATION is one or more fields for the packed data destination register operand. SOURCE is one or more fields for a source such as packed data registers and/or memory location. Note that PS in the opcode mnemonic represents single precision or FP32 and SH represents half-precision or FP16. Additionally, note that a different mnemonic may be used, but VBCSTNESH2PS is used in this discussion as a shortcut. In some examples, the source memory location is provided using at least R/M field 1746 (and in some examples, using the MOD field 1742) and the destination register is provided using register field 1744.
As shown, the execution of a decoded VBCSTNESH2PS instruction causes a FP16 data element from a packed data source (shown here as memory) 301 to be read, converted using conversion circuitry 310, and then broadcast using broadcast circuitry 311 of execution circuitry 313 or memory access circuitry 315 into one or more data elements of the packed data destination 331.
In some examples, the conversion circuitry 310 performs the conversion according to the following approach:
In some examples, the execution of this instruction uses a “round to nearest (even)” rounding mode. In some examples, output denormals are always flushed to zero and input denormals are always treated as zero.
The instruction 401 is received by decode circuitry 405. For example, the decode circuitry 405 receives this instruction from fetch logic/circuitry. The instruction includes fields for an opcode, first and second sources, and a destination. In some examples, the sources and destination are registers, and in other examples one or more are memory locations. In some examples, the opcode details which arithmetic operation is to be performed.
More detailed examples of at least one instruction format will be detailed later. The decode circuitry 405 decodes the instruction into one or more operations. In some examples, this decoding includes generating a plurality of micro-operations to be performed by execution circuitry (such as execution circuitry 409). The decode circuitry 405 also decodes instruction prefixes.
In some examples, register renaming, register allocation, and/or scheduling circuitry 407 provides functionality for one or more of: 1) renaming logical operand values to physical operand values (e.g., a register alias table in some examples), 2) allocating status bits and flags to the decoded instruction, and 3) scheduling the decoded instruction for execution on execution circuitry out of an instruction pool (e.g., using a reservation station in some examples).
Registers (register file) and/or memory 408 store data as operands of the instruction to be operated on by execution circuitry 409. Exemplary register types include packed data registers, general purpose registers, and floating-point registers.
Execution circuitry 409 executes the decoded instruction according to the opcode. Exemplary detailed execution circuitry is shown in
In some examples, retirement/write back circuitry 411 architecturally commits the destination register into the registers or memory 408 and retires the instruction.
At 501, a single instruction having fields for an opcode, an identification of source operand location, and an identification of destination operand location, wherein the opcode is to indicate execution circuitry and/or memory access circuitry is to convert a single BF16 value from the identified source operand location into a FP32 value and store that FP32 value in one or more data element positions of the identified destination operand is fetched. In some examples, the instruction further includes a field for a writemask. In some examples, the instruction is fetched from an instruction cache.
In some examples, the fetched instruction of the first instruction set is translated into one or more instructions of a second instruction set architecture at 502.
The one or more translated instructions of the second instruction set are decoded at 503. In some examples, the translation and decoding are merged.
Data values associated with the source operand of the decoded instruction(s) is/are retrieved at 505 and the decoded instruction(s) scheduled. For example, when the source operand is a memory operand, the data from the indicated memory location is retrieved.
At 507, the decoded instruction, or decoded instruction(s) of the second instruction set, is/are executed by execution circuitry (hardware) such as that detailed herein. For the VBCSTNEBF162PS instruction, the execution will cause execution circuitry to according to the opcode of the VBCSTNEBF162PS instruction, convert a single BF16 value from the identified source operand location into a FP32 value and store that FP32 value in one or more data element positions of the identified destination.
In some examples, the instruction is committed or retired at 509.
At 801, a single instruction having fields for an opcode, an identification of source operand location, and an identification of destination operand location, wherein the opcode is to indicate execution circuitry and/or memory access circuitry is to convert a single FP16 value from the identified source operand location into a FP32 value and store that FP32 value in one or more data element positions of the identified destination operand is fetched. In some examples, the instruction further includes a field for a writemask. In some examples, the instruction is fetched from an instruction cache.
In some examples, the fetched instruction of the first instruction set is translated into one or more instructions of a second instruction set architecture at 802.
The one or more translated instructions of the second instruction set are decoded at 803. In some examples, the translation and decoding are merged.
Data values associated with the source operand of the decoded instruction(s) is/are retrieved at 805 and the decoded instruction(s) scheduled. For example, when the source operand is a memory operand, the data from the indicated memory location is retrieved.
At 807, the decoded instruction, or decoded instruction(s) of the second instruction set, is/are executed by execution circuitry (hardware) such as that detailed herein. For the VBCSTNESH2PS instruction, the execution will cause execution circuitry to according to the opcode of the VBCSTNESH2PS instruction, convert a single FP16 value from the identified source operand location into a FP32 value and store that FP32 value in one or more data element positions of the identified destination.
In some examples, the instruction is committed or retired at 809.
Detailed below are examples of computer architectures, systems, cores, instruction formats, etc. that support one or more examples detailed above.
Exemplary Computer Architectures
Detailed below are describes of exemplary computer architectures. Other system designs and configurations known in the arts for laptops, desktops, handheld PCs, personal digital assistants, engineering workstations, servers, network devices, network hubs, switches, embedded processors, digital signal processors (DSPs), graphics devices, video game devices, set-top boxes, micro controllers, cell phones, portable media players, handheld devices, and various other electronic devices, are also suitable. In general, a wide variety of systems or electronic devices capable of incorporating a processor and/or other execution logic as disclosed herein are generally suitable.
Processors 1170 and 1180 are shown including integrated memory controller (IMC) units circuitry 1172 and 1182, respectively. Processor 1170 also includes as part of its interconnect controller units point-to-point (P-P) interfaces 1176 and 1178; similarly, second processor 1180 includes P-P interfaces 1186 and 1188. Processors 1170, 1180 may exchange information via the point-to-point (P-P) interconnect 1150 using P-P interface circuits 1178, 1188. IMCs 1172 and 1182 couple the processors 1170, 1180 to respective memories, namely a memory 1132 and a memory 1134, which may be portions of main memory locally attached to the respective processors.
Processors 1170, 1180 may each exchange information with a chipset 1190 via individual P-P interconnects 1152, 1154 using point to point interface circuits 1176, 1194, 1186, 1198. Chipset 1190 may optionally exchange information with a coprocessor 1138 via a high-performance interface 1192. In some examples, the coprocessor 1138 is a special-purpose processor, such as, for example, a high-throughput MIC processor, a network or communication processor, compression engine, graphics processor, GPGPU, embedded processor, or the like.
A shared cache (not shown) may be included in either processor 1170, 1180 or outside of both processors, yet connected with the processors via P-P interconnect, such that either or both processors' local cache information may be stored in the shared cache if a processor is placed into a low power mode.
Chipset 1190 may be coupled to a first interconnect 1116 via an interface 1196. In some examples, first interconnect 1116 may be a Peripheral Component Interconnect (PCI) interconnect, or an interconnect such as a PCI Express interconnect or another I/O interconnect. In some examples, one of the interconnects couples to a power control unit (PCU) 1117, which may include circuitry, software, and/or firmware to perform power management operations with regard to the processors 1170, 1180 and/or co-processor 1138. PCU 1117 provides control information to a voltage regulator to cause the voltage regulator to generate the appropriate regulated voltage. PCU 1117 also provides control information to control the operating voltage generated. In various examples, PCU 1117 may include a variety of power management logic units (circuitry) to perform hardware-based power management. Such power management may be wholly processor controlled (e.g., by various processor hardware, and which may be triggered by workload and/or power, thermal or other processor constraints) and/or the power management may be performed responsive to external sources (such as a platform or power management source or system software).
PCU 1117 is illustrated as being present as logic separate from the processor 1170 and/or processor 1180. In other cases, PCU 1117 may execute on a given one or more of cores (not shown) of processor 1170 or 1180. In some cases, PCU 1117 may be implemented as a microcontroller (dedicated or general-purpose) or other control logic configured to execute its own dedicated power management code, sometimes referred to as P-code. In yet other examples, power management operations to be performed by PCU 1117 may be implemented externally to a processor, such as by way of a separate power management integrated circuit (PMIC) or another component external to the processor. In yet other examples, power management operations to be performed by PCU 1117 may be implemented within BIOS or other system software.
Various I/O devices 1114 may be coupled to first interconnect 1116, along with an interconnect (bus) bridge 1118 which couples first interconnect 1116 to a second interconnect 1120. In some examples, one or more additional processor(s) 1115, such as coprocessors, high-throughput MIC processors, GPGPU's, accelerators (such as, e.g., graphics accelerators or digital signal processing (DSP) units), field programmable gate arrays (FPGAs), or any other processor, are coupled to first interconnect 1116. In some examples, second interconnect 1120 may be a low pin count (LPC) interconnect. Various devices may be coupled to second interconnect 1120 including, for example, a keyboard and/or mouse 1122, communication devices 1127 and a storage unit circuitry 1128. Storage unit circuitry 1128 may be a disk drive or other mass storage device which may include instructions/code and data 1130, in some examples. Further, an audio I/O 1124 may be coupled to second interconnect 1120. Note that other architectures than the point-to-point architecture described above are possible. For example, instead of the point-to-point architecture, a system such as multiprocessor system 1100 may implement a multi-drop interconnect or other such architecture.
Exemplary Core Architectures, Processors, and Computer Architectures
Processor cores may be implemented in different ways, for different purposes, and in different processors. For instance, implementations of such cores may include: 1) a general purpose in-order core intended for general-purpose computing; 2) a high-performance general purpose out-of-order core intended for general-purpose computing; 3) a special purpose core intended primarily for graphics and/or scientific (throughput) computing. Implementations of different processors may include: 1) a CPU including one or more general purpose in-order cores intended for general-purpose computing and/or one or more general purpose out-of-order cores intended for general-purpose computing; and 2) a coprocessor including one or more special purpose cores intended primarily for graphics and/or scientific (throughput). Such different processors lead to different computer system architectures, which may include: 1) the coprocessor on a separate chip from the CPU; 2) the coprocessor on a separate die in the same package as a CPU; 3) the coprocessor on the same die as a CPU (in which case, such a coprocessor is sometimes referred to as special purpose logic, such as integrated graphics and/or scientific (throughput) logic, or as special purpose cores); and 4) a system on a chip that may include on the same die as the described CPU (sometimes referred to as the application core(s) or application processor(s)), the above described coprocessor, and additional functionality. Exemplary core architectures are described next, followed by descriptions of exemplary processors and computer architectures.
Thus, different implementations of the processor 1200 may include: 1) a CPU with the special purpose logic 1208 being integrated graphics and/or scientific (throughput) logic (which may include one or more cores, not shown), and the cores 1202(A)-(N) being one or more general purpose cores (e.g., general purpose in-order cores, general purpose out-of-order cores, or a combination of the two); 2) a coprocessor with the cores 1202(A)-(N) being a large number of special purpose cores intended primarily for graphics and/or scientific (throughput); and 3) a coprocessor with the cores 1202(A)-(N) being a large number of general purpose in-order cores. Thus, the processor 1200 may be a general-purpose processor, coprocessor or special-purpose processor, such as, for example, a network or communication processor, compression engine, graphics processor, GPGPU (general purpose graphics processing unit circuitry), a high-throughput many integrated core (MIC) coprocessor (including 30 or more cores), embedded processor, or the like. The processor may be implemented on one or more chips. The processor 1200 may be a part of and/or may be implemented on one or more substrates using any of a number of process technologies, such as, for example, BiCMOS, CMOS, or NMOS.
A memory hierarchy includes one or more levels of cache unit(s) circuitry 1204(A)-(N) within the cores 1202(A)-(N), a set of one or more shared cache units circuitry 1206, and external memory (not shown) coupled to the set of integrated memory controller units circuitry 1214. The set of one or more shared cache units circuitry 1206 may include one or more mid-level caches, such as level 2 (L2), level 3 (L3), level 4 (L4), or other levels of cache, such as a last level cache (LLC), and/or combinations thereof. While in some examples ring-based interconnect network circuitry 1212 interconnects the special purpose logic 1208 (e.g., integrated graphics logic), the set of shared cache units circuitry 1206, and the system agent unit circuitry 1210, alternative examples use any number of well-known techniques for interconnecting such units. In some examples, coherency is maintained between one or more of the shared cache units circuitry 1206 and cores 1202(A)-(N).
In some examples, one or more of the cores 1202(A)-(N) are capable of multi-threading. The system agent unit circuitry 1210 includes those components coordinating and operating cores 1202(A)-(N). The system agent unit circuitry 1210 may include, for example, power control unit (PCU) circuitry and/or display unit circuitry (not shown). The PCU may be or may include logic and components needed for regulating the power state of the cores 1202(A)-(N) and/or the special purpose logic 1208 (e.g., integrated graphics logic). The display unit circuitry is for driving one or more externally connected displays.
The cores 1202(A)-(N) may be homogenous or heterogeneous in terms of architecture instruction set; that is, two or more of the cores 1202(A)-(N) may be capable of executing the same instruction set, while other cores may be capable of executing only a subset of that instruction set or a different instruction set.
Exemplary Core Architectures
In-Order and Out-of-Order Core Block Diagram
In
By way of example, the exemplary register renaming, out-of-order issue/execution core architecture may implement the pipeline 1300 as follows: 1) the instruction fetch 1338 performs the fetch and length decoding stages 1302 and 1304; 2) the decode unit circuitry 1340 performs the decode stage 1306; 3) the rename/allocator unit circuitry 1352 performs the allocation stage 1308 and renaming stage 1310; 4) the scheduler unit(s) circuitry 1356 performs the schedule stage 1312; 5) the physical register file(s) unit(s) circuitry 1358 and the memory unit circuitry 1370 perform the register read/memory read stage 1314; the execution cluster 1360 perform the execute stage 1316; 6) the memory unit circuitry 1370 and the physical register file(s) unit(s) circuitry 1358 perform the write back/memory write stage 1318; 7) various units (unit circuitry) may be involved in the exception handling stage 1322; and 8) the retirement unit circuitry 1354 and the physical register file(s) unit(s) circuitry 1358 perform the commit stage 1324.
The front end unit circuitry 1330 may include branch prediction unit circuitry 1332 coupled to an instruction cache unit circuitry 1334, which is coupled to an instruction translation lookaside buffer (TLB) 1336, which is coupled to instruction fetch unit circuitry 1338, which is coupled to decode unit circuitry 1340. In one example, the instruction cache unit circuitry 1334 is included in the memory unit circuitry 1370 rather than the front-end unit circuitry 1330. The decode unit circuitry 1340 (or decoder) may decode instructions, and generate as an output one or more micro-operations, micro-code entry points, microinstructions, other instructions, or other control signals, which are decoded from, or which otherwise reflect, or are derived from, the original instructions. The decode unit circuitry 1340 may further include an address generation unit circuitry (AGU, not shown). In one example, the AGU generates an LSU address using forwarded register ports, and may further perform branch forwarding (e.g., immediate offset branch forwarding, LR register branch forwarding, etc.). The decode unit circuitry 1340 may be implemented using various different mechanisms. Examples of suitable mechanisms include, but are not limited to, look-up tables, hardware implementations, programmable logic arrays (PLAs), microcode read only memories (ROMs), etc. In one example, the core 1390 includes a microcode ROM (not shown) or other medium that stores microcode for certain macroinstructions (e.g., in decode unit circuitry 1340 or otherwise within the front end unit circuitry 1330). In one example, the decode unit circuitry 1340 includes a micro-operation (micro-op) or operation cache (not shown) to hold/cache decoded operations, micro-tags, or micro-operations generated during the decode or other stages of the processor pipeline 1300. The decode unit circuitry 1340 may be coupled to rename/allocator unit circuitry 1352 in the execution engine unit circuitry 1350.
The execution engine circuitry 1350 includes the rename/allocator unit circuitry 1352 coupled to a retirement unit circuitry 1354 and a set of one or more scheduler(s) circuitry 1356. The scheduler(s) circuitry 1356 represents any number of different schedulers, including reservations stations, central instruction window, etc. In some examples, the scheduler(s) circuitry 1356 can include arithmetic logic unit (ALU) scheduler/scheduling circuitry, ALU queues, arithmetic generation unit (AGU) scheduler/scheduling circuitry, AGU queues, etc. The scheduler(s) circuitry 1356 is coupled to the physical register file(s) circuitry 1358. Each of the physical register file(s) circuitry 1358 represents one or more physical register files, different ones of which store one or more different data types, such as scalar integer, scalar floating-point, packed integer, packed floating-point, vector integer, vector floating-point, status (e.g., an instruction pointer that is the address of the next instruction to be executed), etc. In one example, the physical register file(s) unit circuitry 1358 includes vector registers unit circuitry, writemask registers unit circuitry, and scalar register unit circuitry. These register units may provide architectural vector registers, vector mask registers, general-purpose registers, etc. The physical register file(s) unit(s) circuitry 1358 is overlapped by the retirement unit circuitry 1354 (also known as a retire queue or a retirement queue) to illustrate various ways in which register renaming and out-of-order execution may be implemented (e.g., using a reorder buffer(s) (ROB(s)) and a retirement register file(s); using a future file(s), a history buffer(s), and a retirement register file(s); using a register maps and a pool of registers; etc.). The retirement unit circuitry 1354 and the physical register file(s) circuitry 1358 are coupled to the execution cluster(s) 1360. The execution cluster(s) 1360 includes a set of one or more execution units circuitry 1362 and a set of one or more memory access circuitry 1364. The execution units circuitry 1362 may perform various arithmetic, logic, floating-point or other types of operations (e.g., shifts, addition, subtraction, multiplication) and on various types of data (e.g., scalar floating-point, packed integer, packed floating-point, vector integer, vector floating-point). While some examples may include a number of execution units or execution unit circuitry dedicated to specific functions or sets of functions, other examples may include only one execution unit circuitry or multiple execution units/execution unit circuitry that all perform all functions. The scheduler(s) circuitry 1356, physical register file(s) unit(s) circuitry 1358, and execution cluster(s) 1360 are shown as being possibly plural because certain examples create separate pipelines for certain types of data/operations (e.g., a scalar integer pipeline, a scalar floating-point/packed integer/packed floating-point/vector integer/vector floating-point pipeline, and/or a memory access pipeline that each have their own scheduler circuitry, physical register file(s) unit circuitry, and/or execution cluster—and in the case of a separate memory access pipeline, certain examples are implemented in which only the execution cluster of this pipeline has the memory access unit(s) circuitry 1364). It should also be understood that where separate pipelines are used, one or more of these pipelines may be out-of-order issue/execution and the rest in-order.
In some examples, the execution engine unit circuitry 1350 may perform load store unit (LSU) address/data pipelining to an Advanced Microcontroller Bus (AHB) interface (not shown), and address phase and writeback, data phase load, store, and branches.
The set of memory access circuitry 1364 is coupled to the memory unit circuitry 1370, which includes data TLB unit circuitry 1372 coupled to a data cache circuitry 1374 coupled to a level 2 (L2) cache circuitry 1376. In one exemplary example, the memory access units circuitry 1364 may include a load unit circuitry, a store address unit circuit, and a store data unit circuitry, each of which is coupled to the data TLB circuitry 1372 in the memory unit circuitry 1370. The instruction cache circuitry 1334 is further coupled to a level 2 (L2) cache unit circuitry 1376 in the memory unit circuitry 1370. In one example, the instruction cache 1334 and the data cache 1374 are combined into a single instruction and data cache (not shown) in L2 cache unit circuitry 1376, a level 3 (L3) cache unit circuitry (not shown), and/or main memory. The L2 cache unit circuitry 1376 is coupled to one or more other levels of cache and eventually to a main memory.
The core 1390 may support one or more instructions sets (e.g., the x86 instruction set (with some extensions that have been added with newer versions); the MIPS instruction set; the ARM instruction set (with optional additional extensions such as NEON)), including the instruction(s) described herein. In one example, the core 1390 includes logic to support a packed data instruction set extension (e.g., AVX1, AVX2), thereby allowing the operations used by many multimedia applications to be performed using packed data.
Exemplary Execution Unit(s) Circuitry
Exemplary Register Architecture
In some examples, the register architecture 1500 includes writemask/predicate registers 1515. For example, in some examples, there are 8 writemask/predicate registers (sometimes called k0 through k7) that are each 16-bit, 32-bit, 64-bit, or 128-bit in size. Writemask/predicate registers 1515 may allow for merging (e.g., allowing any set of elements in the destination to be protected from updates during the execution of any operation) and/or zeroing (e.g., zeroing vector masks allow any set of elements in the destination to be zeroed during the execution of any operation). In some examples, each data element position in a given writemask/predicate register 1515 corresponds to a data element position of the destination. In other examples, the writemask/predicate registers 1515 are scalable and consists of a set number of enable bits for a given vector element (e.g., 8 enable bits per 64-bit vector element).
The register architecture 1500 includes a plurality of general-purpose registers 1525. These registers may be 16-bit, 32-bit, 64-bit, etc. and can be used for scalar operations. In some examples, these registers are referenced by the names RAX, RBX, RCX, RDX, RBP, RSI, RDI, RSP, and R8 through R15.
In some examples, the register architecture 1500 includes scalar floating-point register 1545 which is used for scalar floating-point operations on 32/64/80-bit floating-point data using the x87 instruction set extension or as MMX registers to perform operations on 64-bit packed integer data, as well as to hold operands for some operations performed between the MMX and XMM registers.
One or more flag registers 1540 (e.g., EFLAGS, RFLAGS, etc.) store status and control information for arithmetic, compare, and system operations. For example, the one or more flag registers 1540 may store condition code information such as carry, parity, auxiliary carry, zero, sign, and overflow. In some examples, the one or more flag registers 1540 are called program status and control registers.
Segment registers 1520 contain segment points for use in accessing memory. In some examples, these registers are referenced by the names CS, DS, SS, ES, FS, and GS.
Machine specific registers (MSRs) 1535 control and report on processor performance. Most MSRs 1535 handle system-related functions and are not accessible to an application program. Machine check registers 1560 consist of control, status, and error reporting MSRs that are used to detect and report on hardware errors.
One or more instruction pointer register(s) 1530 store an instruction pointer value. Control register(s) 1555 (e.g., CR0-CR4) determine the operating mode of a processor (e.g., processor 1170, 1180, 1138, 1115, and/or 1200) and the characteristics of a currently executing task. Debug registers 1550 control and allow for the monitoring of a processor or core's debugging operations.
Memory management registers 1565 specify the locations of data structures used in protected mode memory management. These registers may include a GDTR, IDRT, task register, and a LDTR register.
Alternative examples may use wider or narrower registers. Additionally, alternative examples may use more, less, or different register files and registers.
Instruction Sets
An instruction set architecture (ISA) may include one or more instruction formats. A given instruction format may define various fields (e.g., number of bits, location of bits) to specify, among other things, the operation to be performed (e.g., opcode) and the operand(s) on which that operation is to be performed and/or other data field(s) (e.g., mask). Some instruction formats are further broken down though the definition of instruction templates (or sub-formats). For example, the instruction templates of a given instruction format may be defined to have different subsets of the instruction format's fields (the included fields are typically in the same order, but at least some have different bit positions because there are less fields included) and/or defined to have a given field interpreted differently. Thus, each instruction of an ISA is expressed using a given instruction format (and, if defined, in a given one of the instruction templates of that instruction format) and includes fields for specifying the operation and the operands. For example, an exemplary ADD instruction has a specific opcode and an instruction format that includes an opcode field to specify that opcode and operand fields to select operands (source1/destination and source2); and an occurrence of this ADD instruction in an instruction stream will have specific contents in the operand fields that select specific operands.
Exemplary Instruction Formats
Examples of the instruction(s) described herein may be embodied in different formats. Additionally, exemplary systems, architectures, and pipelines are detailed below. Examples of the instruction(s) may be executed on such systems, architectures, and pipelines, but are not limited to those detailed.
The prefix(es) field(s) 1601, when used, modifies an instruction. In some examples, one or more prefixes are used to repeat string instructions (e.g., 0xF0, 0xF2, 0xF3, etc.), to provide section overrides (e.g., 0x2E, 0x36, 0x3E, 0x26, 0x64, 0x65, 0x2E, 0x3E, etc.), to perform bus lock operations, and/or to change operand (e.g., 0x66) and address sizes (e.g., 0x67). Certain instructions require a mandatory prefix (e.g., 0x66, 0xF2, 0xF3, etc.). Certain of these prefixes may be considered “legacy” prefixes. Other prefixes, one or more examples of which are detailed herein, indicate, and/or provide further capability, such as specifying particular registers, etc. The other prefixes typically follow the “legacy” prefixes.
The opcode field 1603 is used to at least partially define the operation to be performed upon a decoding of the instruction. In some examples, a primary opcode encoded in the opcode field 1603 is 1, 2, or 3 bytes in length. In other examples, a primary opcode can be a different length. An additional 3-bit opcode field is sometimes encoded in another field.
The addressing field 1605 is used to address one or more operands of the instruction, such as a location in memory or one or more registers.
The content of the MOD field 1742 distinguishes between memory access and non-memory access modes. In some examples, when the MOD field 1742 has a value of b11, a register-direct addressing mode is utilized, and otherwise register-indirect addressing is used.
The register field 1744 may encode either the destination register operand or a source register operand, or may encode an opcode extension and not be used to encode any instruction operand. The content of register index field 1744, directly or through address generation, specifies the locations of a source or destination operand (either in a register or in memory). In some examples, the register field 1744 is supplemented with an additional bit from a prefix (e.g., prefix 1601) to allow for greater addressing.
The R/M field 1746 may be used to encode an instruction operand that references a memory address, or may be used to encode either the destination register operand or a source register operand. Note the R/M field 1746 may be combined with the MOD field 1742 to dictate an addressing mode in some examples.
The SIB byte 1704 includes a scale field 1752, an index field 1754, and a base field 1756 to be used in the generation of an address. The scale field 1752 indicates scaling factor. The index field 1754 specifies an index register to use. In some examples, the index field 1754 is supplemented with an additional bit from a prefix (e.g., prefix 1601) to allow for greater addressing. The base field 1756 specifies a base register to use. In some examples, the base field 1756 is supplemented with an additional bit from a prefix (e.g., prefix 1601) to allow for greater addressing. In practice, the content of the scale field 1752 allows for the scaling of the content of the index field 1754 for memory address generation (e.g., for address generation that uses 2scale*index+base).
Some addressing forms utilize a displacement value to generate a memory address. For example, a memory address may be generated according to 2scale*index+base+displacement, index*scale+displacement, r/m+displacement, instruction pointer (RIP/EIP)+displacement, register+displacement, etc. The displacement may be a 1-byte, 2-byte, 4-byte, etc. value. In some examples, a displacement field 1607 provides this value. Additionally, in some examples, a displacement factor usage is encoded in the MOD field of the addressing field 1605 that indicates a compressed displacement scheme for which a displacement value is calculated by multiplying disp8 in conjunction with a scaling factor N that is determined based on the vector length, the value of a b bit, and the input element size of the instruction. The displacement value is stored in the displacement field 1607.
In some examples, an immediate field 1609 specifies an immediate for the instruction. An immediate may be encoded as a 1-byte value, a 2-byte value, a 4-byte value, etc.
Instructions using the first prefix 1601(A) may specify up to three registers using 3-bit fields depending on the format: 1) using the reg field 1744 and the R/M field 1746 of the Mod R/M byte 1702; 2) using the Mod R/M byte 1702 with the SIB byte 1704 including using the reg field 1744 and the base field 1756 and index field 1754; or 3) using the register field of an opcode.
In the first prefix 1601(A), bit positions 7:4 are set as 0100. Bit position 3 (W) can be used to determine the operand size, but may not solely determine operand width. As such, when W=0, the operand size is determined by a code segment descriptor (CS.D) and when W=1, the operand size is 64-bit.
Note that the addition of another bit allows for 16 (24) registers to be addressed, whereas the MOD R/M reg field 1744 and MOD R/M R/M field 1746 alone can each only address 8 registers.
In the first prefix 1601(A), bit position 2 (R) may an extension of the MOD R/M reg field 1744 and may be used to modify the ModR/M reg field 1744 when that field encodes a general purpose register, a 64-bit packed data register (e.g., a SSE register), or a control or debug register. R is ignored when Mod R/M byte 1702 specifies other registers or defines an extended opcode.
Bit position 1 (X) X bit may modify the SIB byte index field 1754.
Bit position B (B) B may modify the base in the Mod R/M R/M field 1746 or the SIB byte base field 1756; or it may modify the opcode register field used for accessing general purpose registers (e.g., general purpose registers 1525).
In some examples, the second prefix 1601(B) comes in two forms—a two-byte form and a three-byte form. The two-byte second prefix 1601(B) is used mainly for 128-bit, scalar, and some 256-bit instructions; while the three-byte second prefix 1601(B) provides a compact replacement of the first prefix 1601(A) and 3-byte opcode instructions.
Instructions that use this prefix may use the Mod R/M R/M field 1746 to encode the instruction operand that references a memory address or encode either the destination register operand or a source register operand.
Instructions that use this prefix may use the Mod R/M reg field 1744 to encode either the destination register operand or a source register operand, be treated as an opcode extension and not used to encode any instruction operand.
For instruction syntax that support four operands, vvvv, the Mod R/M R/M field 1746 and the Mod R/M reg field 1744 encode three of the four operands. Bits[7:4] of the immediate 1609 are then used to encode the third source register operand.
Bit[7] of byte 22017 is used similar to W of the first prefix 1601(A) including helping to determine promotable operand sizes. Bit[2] is used to dictate the length (L) of the vector (where a value of 0 is a scalar or 128-bit vector and a value of 1 is a 256-bit vector). Bits[1:0] provide opcode extensionality equivalent to some legacy prefixes (e.g., 00=no prefix, 01=66H, 10=F3H, and 11=F2H). Bits[6:3], shown as vvvv, may be used to: 1) encode the first source register operand, specified in inverted (1s complement) form and valid for instructions with 2 or more source operands; 2) encode the destination register operand, specified in 1s complement form for certain vector shifts; or 3) not encode any operand, the field is reserved and should contain a certain value, such as 1111b.
Instructions that use this prefix may use the Mod R/M R/M field 1746 to encode the instruction operand that references a memory address or encode either the destination register operand or a source register operand.
Instructions that use this prefix may use the Mod R/M reg field 1744 to encode either the destination register operand or a source register operand, be treated as an opcode extension and not used to encode any instruction operand.
For instruction syntax that support four operands, vvvv, the Mod R/M R/M field 1746, and the Mod R/M reg field 1744 encode three of the four operands. Bits[7:4] of the immediate 1609 are then used to encode the third source register operand.
The third prefix 1601(C) can encode 32 vector registers (e.g., 128-bit, 256-bit, and 512-bit registers) in 64-bit mode. In some examples, instructions that utilize a writemask/opmask (see discussion of registers in a previous figure, such as
The third prefix 1601(C) may encode functionality that is specific to instruction classes (e.g., a packed instruction with “load+op” semantic can support embedded broadcast functionality, a floating-point instruction with rounding semantic can support static rounding functionality, a floating-point instruction with non-rounding arithmetic semantic can support “suppress all exceptions” functionality, etc.).
The first byte of the third prefix 1601(C) is a format field 2111 that has a value, in one example, of 62H. Subsequent bytes are referred to as payload bytes 2115-2119 and collectively form a 24-bit value of P[23:0] providing specific capability in the form of one or more fields (detailed herein).
In some examples, P[1:0] of payload byte 2119 are identical to the low two mmmmm bits. P[3:2] are reserved in some examples. Bit P[4] (R′) allows access to the high 16 vector register set when combined with P[7] and the ModR/M reg field 1744. P[6] can also provide access to a high 16 vector register when SIB-type addressing is not needed. P[7:5] consist of an R, X, and B which are operand specifier modifier bits for vector register, general purpose register, memory addressing and allow access to the next set of 8 registers beyond the low 8 registers when combined with the ModR/M register field 1744 and ModR/M R/M field 1746. P[9:8] provide opcode extensionality equivalent to some legacy prefixes (e.g., 00=no prefix, 01=66H, 10=F3H, and 11=F2H). P[10] in some examples is a fixed value of 1. P[14:11], shown as vvvv, may be used to: 1) encode the first source register operand, specified in inverted (1s complement) form and valid for instructions with 2 or more source operands; 2) encode the destination register operand, specified in 1s complement form for certain vector shifts; or 3) not encode any operand, the field is reserved and should contain a certain value, such as 1111b.
P[15] is similar to W of the first prefix 1601(A) and second prefix 1611(B) and may serve as an opcode extension bit or operand size promotion.
P[18:16] specify the index of a register in the opmask (writemask) registers (e.g., writemask/predicate registers 1515). In one example, the specific value aaa=000 has a special behavior implying no opmask is used for the particular instruction (this may be implemented in a variety of ways including the use of a opmask hardwired to all ones or hardware that bypasses the masking hardware). When merging, vector masks allow any set of elements in the destination to be protected from updates during the execution of any operation (specified by the base operation and the augmentation operation); in other one example, preserving the old value of each element of the destination where the corresponding mask bit has a 0. In contrast, when zeroing vector masks allow any set of elements in the destination to be zeroed during the execution of any operation (specified by the base operation and the augmentation operation); in one example, an element of the destination is set to 0 when the corresponding mask bit has a 0 value. A subset of this functionality is the ability to control the vector length of the operation being performed (that is, the span of elements being modified, from the first to the last one); however, it is not necessary that the elements that are modified be consecutive. Thus, the opmask field allows for partial vector operations, including loads, stores, arithmetic, logical, etc. While examples are described in which the opmask field's content selects one of a number of opmask registers that contains the opmask to be used (and thus the opmask field's content indirectly identifies that masking to be performed), alternative examples instead or additional allow the mask write field's content to directly specify the masking to be performed.
P[19] can be combined with P[14:11] to encode a second source vector register in a non-destructive source syntax which can access an upper 16 vector registers using P[19]. P[20] encodes multiple functionalities, which differs across different classes of instructions and can affect the meaning of the vector length/rounding control specifier field (P[22:21]). P[23] indicates support for merging-writemasking (e.g., when set to 0) or support for zeroing and merging-writemasking (e.g., when set to 1).
Exemplary examples of encoding of registers in instructions using the third prefix 1601(C) are detailed in the following tables.
Program code may be applied to input instructions to perform the functions described herein and generate output information. The output information may be applied to one or more output devices, in known fashion. For purposes of this application, a processing system includes any system that has a processor, such as, for example, a digital signal processor (DSP), a microcontroller, an application specific integrated circuit (ASIC), or a microprocessor.
The program code may be implemented in a high-level procedural or object-oriented programming language to communicate with a processing system. The program code may also be implemented in assembly or machine language, if desired. In fact, the mechanisms described herein are not limited in scope to any particular programming language. In any case, the language may be a compiled or interpreted language.
Examples of the mechanisms disclosed herein may be implemented in hardware, software, firmware, or a combination of such implementation approaches. Examples may be implemented as computer programs or program code executing on programmable systems comprising at least one processor, a storage system (including volatile and non-volatile memory and/or storage elements), at least one input device, and at least one output device.
One or more aspects of at least one example may be implemented by representative instructions stored on a machine-readable medium which represents various logic within the processor, which when read by a machine causes the machine to fabricate logic to perform the techniques described herein. Such representations, known as “IP cores” may be stored on a tangible, machine readable medium and supplied to various customers or manufacturing facilities to load into the fabrication machines that actually make the logic or processor.
Such machine-readable storage media may include, without limitation, non-transitory, tangible arrangements of articles manufactured or formed by a machine or device, including storage media such as hard disks, any other type of disk including floppy disks, optical disks, compact disk read-only memories (CD-ROMs), compact disk rewritables (CD-RWs), and magneto-optical disks, semiconductor devices such as read-only memories (ROMs), random access memories (RAMs) such as dynamic random access memories (DRAMs), static random access memories (SRAMs), erasable programmable read-only memories (EPROMs), flash memories, electrically erasable programmable read-only memories (EEPROMs), phase change memory (PCM), magnetic or optical cards, or any other type of media suitable for storing electronic instructions.
Accordingly, examples also include non-transitory, tangible machine-readable media containing instructions or containing design data, such as Hardware Description Language (HDL), which defines structures, circuits, apparatuses, processors and/or system features described herein. Such examples may also be referred to as program products.
Emulation (Including Binary Translation, Code Morphing, Etc.)
In some cases, an instruction converter may be used to convert an instruction from a source instruction set to a target instruction set. For example, the instruction converter may translate (e.g., using static binary translation, dynamic binary translation including dynamic compilation), morph, emulate, or otherwise convert an instruction to one or more other instructions to be processed by the core. The instruction converter may be implemented in software, hardware, firmware, or a combination thereof. The instruction converter may be on processor, off processor, or part on and part off processor.
References to “one example,” “an example,” etc., indicate that the example described may include a particular feature, structure, or characteristic, but every example may not necessarily include the particular feature, structure, or characteristic. Moreover, such phrases are not necessarily referring to the same example. Further, when a particular feature, structure, or characteristic is described in connection with an example, it is submitted that it is within the knowledge of one skilled in the art to affect such feature, structure, or characteristic in connection with other examples whether or not explicitly described.
Examples include, but are not limited to:
Moreover, in the various examples described above, unless specifically noted otherwise, disjunctive language such as the phrase “at least one of A, B, or C” is intended to be understood to mean either A, B, or C, or any combination thereof (e.g., A, B, and/or C). As such, disjunctive language is not intended to, nor should it be understood to, imply that a given example requires at least one of A, at least one of B, or at least one of C to each be present.
The specification and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense. It will, however, be evident that various modifications and changes may be made thereunto without departing from the broader spirit and scope of the disclosure as set forth in the claims.
