CONVERSION INSTRUCTIONS

BACKGROUND

In recent years fused-multiply-add (FMA) units with lower-precision multiplications and higher-precision accumulation have proven useful in machine learning/artificial intelligence applications, most notably in training deep neural networks due to their extreme computational intensity. Compared to classical IEEE-754 32-bit (FP32) and 64-bit (FP64) arithmetic, this reduced precision arithmetic can naturally be sped up disproportional to their shortened width.

BRIEF DESCRIPTION OF DRAWINGS

Various examples in accordance with the present disclosure will be described with reference to the drawings, in which:

FIG. 1 illustrates different floating point representation formats.

FIG. 3 illustrates an example of method to process a VCVTNEEBF162PS instruction.

FIG. 4 illustrates examples of instruction encodings for the VCVTNEEBF162PS instruction.

FIG. 5 illustrates examples of instruction pseudocode for the VCVTNEEBF162PS instruction.

FIG. 7 illustrates an example of method to process a VCVTNEOBF162PS instruction.

FIG. 8 illustrates examples of instruction encodings for the VCVTNEOBF162PS instruction.

FIG. 9 illustrates examples of instruction pseudocode for the VCVTNEOBF162PS instruction.

FIG. 11 illustrates an example of method to process a VCVTNEEPH2PS instruction.

FIG. 12 illustrates examples of instruction encodings for the VCVTNEEPH2PS instruction.

FIG. 13 illustrates examples of instruction pseudocode for the VCVTNEEPH2PS instruction.

FIG. 15 illustrates an example of method to process a VCVTNEOPH2PS instruction.

FIG. 16 illustrates examples of instruction encodings for the VCVTNEOPH2PS instruction.

FIG. 17 illustrates examples of instruction pseudocode for the VCVTNEOPH2PS instruction.

FIG. 18 illustrates examples of hardware to process an instruction such as a any of the above detailed instructions.

FIG. 19 illustrates examples of an exemplary system.

FIG. 20 illustrates a block diagram of examples of a processor that may have more than one core, may have an integrated memory controller, and may have integrated graphics.

FIG. 21(A) is a block diagram illustrating both an exemplary in-order pipeline and an exemplary register renaming, out-of-order issue/execution pipeline according to examples.

FIG. 21(B) is a block diagram illustrating both an exemplary example of an in-order architecture core and an exemplary register renaming, out-of-order issue/execution architecture core to be included in a processor according to examples.

FIG. 22 illustrates examples of execution unit(s) circuitry, such as execution unit(s) circuitry of FIG. 21(B).

FIG. 23 is a block diagram of a register architecture according to some examples.

FIG. 24 illustrates examples of an instruction format.

FIG. 25 illustrates examples of an addressing field.

FIG. 26 illustrates examples of a first prefix.

FIGS. 27(A)-(D) illustrate examples of how the R, X, and B fields of the first prefix 2401(A) are used.

FIGS. 28(A)-(B) illustrate examples of a second prefix.

FIG. 29 illustrates examples of a third prefix.

DETAILED DESCRIPTION

The present disclosure relates to methods, apparatus, systems, and non-transitory computer-readable storage media for data element conversion.

FIG. 1 illustrates different floating point representation formats. In this illustration, the formats are in little endian format, however, in some examples, a big endian format is used. The FP32 format 101 has a sign bit (S), an 8-bit exponent, and a 23-bit fraction (a 24-bit mantissa that uses an implicit bit). The FP16 format 103 has a sign bit (S), a 5-bit exponent, and a 10-bit fraction. The BF16 format 105 has a sign bit (S), an 8-bit exponent, and a 7-bit fraction.

In contrast to the IEEE 754-standardized 16-bit (FP16) variant, BF16 does not compromise on range when being compared to FP32. FP32 numbers have 8 bits of exponent and 24 bits of mantissa (including the one implicit). BF16 cuts 16 bits from the 24-bit FP32 mantissa to create a 16-bit floating point datatype. In contrast FP16, roughly halves the FP32 mantissa to 10 explicit bits and reduces the exponent to 5 bits to fit the 16-bit datatype envelope.

Although BF16 offers less precision than FP16, it is typically better suited to support deep learning tasks. FP16's range is not enough to accomplish deep learning training out-of-the-box due to its limited range. BF16 does not suffer from this issue and the limited precision may actually help to generalize the learned weights in the neural net training task. In other words, lower precision can be seen as offering a built-in regularization property.

Not all processors have support for all data types. For example, in some examples, the execution circuitry detailed below does not have FP16 and/or BF16 execution support. In other words, the execution circuitry cannot natively work with these formats and the conversion to FP32 allows for the execution circuitry to be able to handle previously unsupported data types. As such, there is not the need to build out support for FP16 and/or BF16 which takes up area and may consume more power. Detailed herein are examples of instructions, and their support, which convert odd BF16 or FP16 data element of a source into a FP32 data element and store that FP32 data element into one or more data element positions of a destination. Detailed herein are examples of instructions, and their support, which convert even BF16 or FP16 data element of a source into a FP32 data element and store that FP32 data element into one or more data element positions of a destination.

FIG. 2(A) illustrates an exemplary execution of single decoded instruction to convert BF16 values stored in even data element positions from a source into a FP32 values and store the FP32 values into data element positions of a destination. Note that in some examples, this single instruction of a first instruction set architecture is converted into one or more instructions of a second, different instruction set architecture, however, the result will be the same.

An example of a format for an instruction to convert BF16 values stored in even data element positions from a source into a FP32 values and store the FP32 values into data element positions of a destination is VCVTNEEBF162PS DESTINATION, SOURCE. In some examples, VCVTNEEBF162PS is the opcode mnemonic of the instruction. DESTINATION is one or more fields used to indicate a packed data destination register operand. SOURCE is one or more fields used to indicate a first source such as packed data registers and/or memory location. Note that PS in the opcode mnemonic represents single precision or FP32. Additionally, note that a different mnemonic may be used, but VCVTNEEBF162PS is used in this discussion as a shortcut. In some examples, the source location is provided using at least R/M field 2546 (and in some examples, using the MOD field 2542) and the destination register is provided using register field 2544.

As shown, the execution of a decoded VCVTNEEBF162PS instruction causes a conversion of BF16 values stored in even data element positions from source 201 into a FP32 values by conversion circuitry 211 of execution circuitry 213 or memory access circuitry 215 and storage of the FP32 values into data element positions of a destination 231. Note that this illustration shows individual BF16 values in the source 201 and the destination 231 notation shows which BF16 data element the FP32 value was converted from. For example, SRC1[FP32[2]] indicates that that the BF16[2] value was converted. In some examples, the conversion to FP32 is to append 16 trailing zeros to BF16 value.

In some examples, the execution of this instruction uses a “round to nearest (even)” rounding mode. In some examples, output denormals are always flushed to zero and input denormals are always treated as zero.

FIG. 2(B) illustrates an exemplary execution of single decoded instruction to convert BF16 values stored in even data element positions from a source into a FP32 values and store the FP32 values into data element positions of a destination. In this example, BF16 values are stored in the lower 16 bits of a 32-bit data element and the 32-bit data element position of the source is the data element position for which the converted FP32 value is to be stored. Note that in some examples, this single instruction of a first instruction set architecture is converted into one or more instructions of a second, different instruction set architecture, however, the result will be the same.

As shown, the execution of a decoded VCVTNEEBF162PS instruction causes a conversion of BF16 values stored in even data element positions from source 201 into a FP32 values by conversion circuitry 211 of execution circuitry 213 or memory access circuitry 215 and storage of the FP32 values into data element positions of a destination 231. Note that this illustration shows individual BF16 values in the source 201 and the destination 231 notation shows which BF16 data element the FP32 value was converted from. In some examples, the conversion to FP32 is to append 16 trailing zeros to BF16 value.

FIG. 3 illustrates an example of method to process a VCVTNEEBF162PS instruction. In some examples, a processor core as shown in FIG. 21(B), a pipeline as detailed below, etc. performs this method. In some examples, a processor core works with an emulation layer, or includes a binary translation circuit, to execute one or more instructions of a second, different instruction set architecture (ISA) to perform the operation(s) of the VCVTNEEBF162PS instruction.

At 301, a single instruction having fields for an opcode, an identification of a source operand, and an identification of destination operand, wherein the opcode is to indicate execution circuitry and/or memory access circuitry is to convert even BF16 values from the identified source operand into FP32 values and store the FP32 values in data element positions of the identified destination operand. The identification of operands may be to a register and/or a memory location.

In some examples, the fetched instruction of the first instruction set is translated into one or more instructions of a second instruction set architecture at 302.

The one or more translated instructions of the second instruction set are decoded at 303. In some examples, the translation and decoding are merged.

Data values associated with the source operand of the decoded instruction(s) is/are retrieved at 305 and the decoded instruction(s) scheduled. For example, when the source operand is a memory operand, the data from the indicated memory location is retrieved.

At 307, the decoded instruction, or decoded instruction(s) of the second instruction set, is/are executed by execution circuitry (hardware) such as that detailed herein. For the VCVTNEEBF162PS instruction, the execution will cause execution circuitry to according to the opcode of the VCVTNEEBF162PS instruction, convert even BF16 values from the identified source operand into FP32 values and store the FP32 values in data element positions of the identified destination operand.

In some examples, the instruction is committed or retired at 309.

FIG. 4 illustrates examples of instruction encodings for the VCVTNEEBF162PS instruction.

FIG. 5 illustrates examples of instruction pseudocode for the VCVTNEEBF162PS instruction.

FIG. 6(A) illustrates an exemplary execution of single decoded instruction to convert BF16 values stored in odd data element positions from a source into a FP32 values and store the FP32 values into data element positions of a destination. Note that in some examples, this single instruction of a first instruction set architecture is converted into one or more instructions of a second, different instruction set architecture, however, the result will be the same.

An example of a format for an instruction to convert BF16 values stored in odd data element positions from a source into a FP32 values and store the FP32 values into data element positions of a destination is VCVTNEOBF162PS DESTINATION, SOURCE. In some examples, VCVTNEOBF162PS is the opcode mnemonic of the instruction. DESTINATION is one or more fields used to indicate a packed data destination register operand. SOURCE is one or more fields used to indicate a first source such as packed data registers and/or memory location. Note that PS in the opcode mnemonic represents single precision or FP32. Additionally, note that a different mnemonic may be used, but VCVTNEOBF162PS is used in this discussion as a shortcut. In some examples, the source location is provided using at least R/M field 2546 (and in some examples, using the MOD field 2542) and the destination register is provided using register field 2544.

As shown, the execution of a decoded VCVTNEOBF162PS instruction causes a conversion of BF16 values stored in odd data element positions from source 601 into a FP32 values by conversion circuitry 611 of execution circuitry 613 or memory access circuitry 615 and storage of the FP32 values into data element positions of a destination 631. Note that this illustration shows individual BF16 values in the source 601 and the destination 631 notation shows which BF16 data element the FP32 value was converted from. For example, SRC1[FP32[3]] indicates that that the BF16[3] value was converted. In some examples, the conversion to FP32 is to append 16 trailing zeros to BF16 value.

In some examples, the execution of this instruction uses a “round to nearest (odd)” rounding mode. In some examples, output denormals are always flushed to zero and input denormals are always treated as zero.

FIG. 6(B) illustrates an exemplary execution of single decoded instruction to convert BF16 values stored in odd data element positions from a source into a FP32 values and store the FP32 values into data element positions of a destination. In this example, BF16 values are stored in the upper 16 bits of a 32-bit data element and the 32-bit data element position of the source is the data element position for which the converted FP32 value is to be stored. Note that in some examples, this single instruction of a first instruction set architecture is converted into one or more instructions of a second, different instruction set architecture, however, the result will be the same.

FIG. 7 illustrates an example of method to process a VCVTNEOBF162PS instruction. In some examples, a processor core as shown in FIG. 21(B), a pipeline as detailed below, etc. performs this method. In some examples, a processor core works with an emulation layer, or includes a binary translation circuit, to execute one or more instructions of a second, different instruction set architecture (ISA) to perform the operation(s) of the VCVTNEOBF162PS instruction.

At 701, a single instruction having fields for an opcode, an identification of a source operand, and an identification of destination operand, wherein the opcode is to indicate execution circuitry and/or memory access circuitry is to convert odd BF16 values from the identified source operand into FP32 values and store the FP32 values in data element positions of the identified destination operand. The identification of operands may be to a register and/or a memory location.

In some examples, the fetched instruction of the first instruction set is translated into one or more instructions of a second instruction set architecture at 702.

The one or more translated instructions of the second instruction set are decoded at 703. In some examples, the translation and decoding are merged.

Data values associated with the source operand of the decoded instruction(s) is/are retrieved at 705 and the decoded instruction(s) scheduled. For example, when the source operand is a memory operand, the data from the indicated memory location is retrieved.

At 707, the decoded instruction, or decoded instruction(s) of the second instruction set, is/are executed by execution circuitry (hardware) such as that detailed herein. For the VCVTNEOBF162PS instruction, the execution will cause execution circuitry to according to the opcode of the VCVTNEOBF162PS instruction, convert odd BF16 values from the identified source operand into FP32 values and store the FP32 values in data element positions of the identified destination operand.

In some examples, the instruction is committed or retired at 709.

FIG. 8 illustrates examples of instruction encodings for the VCVTNEOBF162PS instruction.

FIG. 9 illustrates examples of instruction pseudocode for the VCVTNEOBF162PS instruction.

FIG. 10(A) illustrates an exemplary execution of single decoded instruction to convert FP16 values stored in even data element positions from a source into a FP32 values and store the FP32 values into data element positions of a destination. Note that in some examples, this single instruction of a first instruction set architecture is converted into one or more instructions of a second, different instruction set architecture, however, the result will be the same.

An example of a format for an instruction to convert FP16 values stored in even data element positions from a source into a FP32 values and store the FP32 values into data element positions of a destination is VCVTNEEPH2PS DESTINATION, SOURCE. In some examples, VCVTNEEPH2PS is the opcode mnemonic of the instruction. DESTINATION is one or more fields used to indicate a packed data destination register operand. SOURCE is one or more fields used to indicate a first source such as packed data registers and/or memory location. Note that PS in the opcode mnemonic represents single precision or FP32. Additionally, note that a different mnemonic may be used, but VCVTNEEPH2PS is used in this discussion as a shortcut. In some examples, the source location is provided using at least R/M field 2546 (and in some examples, using the MOD field 2542) and the destination register is provided using register field 2544.

As shown, the execution of a decoded VCVTNEEPH2PS instruction causes a conversion of FP16 values stored in even data element positions from source 1001 into a FP32 values by conversion circuitry 1011 of execution circuitry 1013 or memory access circuitry 1015 and storage of the FP32 values into data element positions of a destination 1031. Note that this illustration shows individual FP16 values in the source 1001 and the destination 1031 notation shows which FP16 data element the FP32 value was converted from. For example, SRC1[FP32[2]] indicates that that the FP16[2] value was converted. In some examples, the conversion to FP32 is to append 16 trailing zeros to FP16 value.

FIG. 10(B) illustrates an exemplary execution of single decoded instruction to convert FP16 values stored in even data element positions from a source into a FP32 values and store the FP32 values into data element positions of a destination. In this example, FP16 values are stored in the lower 16 bits of a 32-bit data element and the 32-bit data element position of the source is the data element position for which the converted FP32 value is to be stored. Note that in some examples, this single instruction of a first instruction set architecture is converted into one or more instructions of a second, different instruction set architecture, however, the result will be the same.

FIG. 11 illustrates an example of method to process a VCVTNEEPH2PS instruction. In some examples, a processor core as shown in FIG. 21(B), a pipeline as detailed below, etc. performs this method. In some examples, a processor core works with an emulation layer, or includes a binary translation circuit, to execute one or more instructions of a second, different instruction set architecture (ISA) to perform the operation(s) of the VCVTNEEPH2PS instruction.

At 1101, a single instruction having fields for an opcode, an identification of a source operand, and an identification of destination operand, wherein the opcode is to indicate execution circuitry and/or memory access circuitry is to convert even FP16 values from the identified source operand into FP32 values and store the FP32 values in data element positions of the identified destination operand. The identification of operands may be to a register and/or a memory location.

In some examples, the fetched instruction of the first instruction set is translated into one or more instructions of a second instruction set architecture at 1102.

The one or more translated instructions of the second instruction set are decoded at 1103. In some examples, the translation and decoding are merged.

Data values associated with the source operand of the decoded instruction(s) is/are retrieved at 1105 and the decoded instruction(s) scheduled. For example, when the source operand is a memory operand, the data from the indicated memory location is retrieved.

At 1107, the decoded instruction, or decoded instruction(s) of the second instruction set, is/are executed by execution circuitry (hardware) such as that detailed herein. For the VCVTNEEPH2PS instruction, the execution will cause execution circuitry to according to the opcode of the VCVTNEEPH2PS instruction, convert even FP16 values from the identified source operand into FP32 values and store the FP32 values in data element positions of the identified destination operand.

In some examples, the instruction is committed or retired at 1109.

FIG. 12 illustrates examples of instruction encodings for the VCVTNEEPH2PS instruction.

FIG. 13 illustrates examples of instruction pseudocode for the VCVTNEEPH2PS instruction.

FIG. 14(A) illustrates an exemplary execution of single decoded instruction to convert FP16 values stored in odd data element positions from a source into a FP32 values and store the FP32 values into data element positions of a destination. Note that in some examples, this single instruction of a first instruction set architecture is converted into one or more instructions of a second, different instruction set architecture, however, the result will be the same.

An example of a format for an instruction to convert FP16 values stored in odd data element positions from a source into a FP32 values and store the FP32 values into data element positions of a destination is VCVTNEOPH2PS DESTINATION, SOURCE. In some examples, VCVTNEOPH2PS is the opcode mnemonic of the instruction. DESTINATION is one or more fields used to indicate a packed data destination register operand. SOURCE is one or more fields used to indicate a first source such as packed data registers and/or memory location. Note that PS in the opcode mnemonic represents single precision or FP32. Additionally, note that a different mnemonic may be used, but VCVTNEOPH2PS is used in this discussion as a shortcut. In some examples, the source location is provided using at least R/M field 2546 (and in some examples, using the MOD field 2542) and the destination register is provided using register field 2544.

As shown, the execution of a decoded VCVTNEOPH2PS instruction causes a conversion of FP16 values stored in odd data element positions from source 1401 into a FP32 values by conversion circuitry 1411 of execution circuitry 1413 or memory access circuitry 1415 and storage of the FP32 values into data element positions of a destination 1431. Note that this illustration shows individual FP16 values in the source 1401 and the destination 1431 notation shows which FP16 data element the FP32 value was converted from. For example, SRC1[FP32[3]] indicates that that the FP16[3] value was converted.

FIG. 14(B) illustrates an exemplary execution of single decoded instruction to convert FP16 values stored in odd data element positions from a source into a FP32 values and store the FP32 values into data element positions of a destination. In this example, FP16 values are stored in the upper 16 bits of a 32-bit data element and the 32-bit data element position of the source is the data element position for which the converted FP32 value is to be stored. Note that in some examples, this single instruction of a first instruction set architecture is converted into one or more instructions of a second, different instruction set architecture, however, the result will be the same.

An example of a format for an instruction to convert FP16 values stored in odd data element positions from a source into a FP32 values and store the FP16 values into data element positions of a destination is VCVTNEOPH2PS DESTINATION, SOURCE. In some examples, VCVTNEOPH2PS is the opcode mnemonic of the instruction. DESTINATION is one or more fields used to indicate a packed data destination register operand. SOURCE is one or more fields used to indicate a first source such as packed data registers and/or memory location. Note that PS in the opcode mnemonic represents single precision or FP32. Additionally, note that a different mnemonic may be used, but VCVTNEOPH2PS is used in this discussion as a shortcut. In some examples, the source location is provided using at least R/M field 2546 (and in some examples, using the MOD field 2542) and the destination register is provided using register field 2544.

FIG. 15 illustrates an example of method to process a VCVTNEOPH2PS instruction. In some examples, a processor core as shown in FIG. 21(B), a pipeline as detailed below, etc. performs this method. In some examples, a processor core works with an emulation layer, or includes a binary translation circuit, to execute one or more instructions of a second, different instruction set architecture (ISA) to perform the operation(s) of the VCVTNEOPH2PS instruction.

At 1501, a single instruction having fields for an opcode, an identification of a source operand, and an identification of destination operand, wherein the opcode is to indicate execution circuitry and/or memory access circuitry is to convert odd FP16 values from the identified source operand into FP32 values and store the FP32 values in data element positions of the identified destination operand. The identification of operands may be to a register and/or a memory location.

In some examples, the fetched instruction of the first instruction set is translated into one or more instructions of a second instruction set architecture at 1502.

The one or more translated instructions of the second instruction set are decoded at 1503. In some examples, the translation and decoding are merged.

Data values associated with the source operand of the decoded instruction(s) is/are retrieved at 1505 and the decoded instruction(s) scheduled. For example, when the source operand is a memory operand, the data from the indicated memory location is retrieved.

At 1507, the decoded instruction, or decoded instruction(s) of the second instruction set, is/are executed by execution circuitry (hardware) such as that detailed herein. For the VCVTNEOPH2PS instruction, the execution will cause execution circuitry to according to the opcode of the VCVTNEOPH2PS instruction, convert odd FP16 values from the identified source operand into FP32 values and store the FP32 values in data element positions of the identified destination operand.

In some examples, the instruction is committed or retired at 1509.

FIG. 16 illustrates examples of instruction encodings for the VCVTNEOPH2PS instruction.

FIG. 17 illustrates examples of instruction pseudocode for the VCVTNEOPH2PS instruction.

FIG. 18 illustrates examples of hardware to process an instruction such as a any of the above detailed instructions. As illustrated, storage 1803 stores one or more of the above detailed instructions to be executed.

The instruction 1801 is received by decode circuitry 1805. For example, the decode circuitry 1805 receives this instruction from fetch logic/circuitry. The instruction includes fields for an opcode, first and/or second source(s), and a destination. In some examples, the source(s) and destination are registers, and in other examples one or more are memory locations.

More detailed examples of at least one instruction format will be detailed later. The decode circuitry 1805 decodes the instruction into one or more operations. In some examples, this decoding includes generating a plurality of micro-operations to be performed by execution circuitry (such as execution circuitry 1809). The decode circuitry 1805 also decodes instruction prefixes.

In some examples, register renaming, register allocation, and/or scheduling circuitry 1807 provides functionality for one or more of: 1) renaming logical operand values to physical operand values (e.g., a register alias table in some examples), 2) allocating status bits and flags to the decoded instruction, and 3) scheduling the decoded instruction for execution on execution circuitry out of an instruction pool (e.g., using a reservation station in some examples).

Registers (register file) and/or memory 1808 store data as operands of the instruction to be operated on by execution circuitry 1809. Exemplary register types include packed data registers, general purpose registers, and floating-point registers.

Execution circuitry 1809 executes the decoded instruction according to the opcode. Exemplary detailed execution circuitry is shown in FIGS. 2, 18, 21, etc.

In some examples, retirement/write back circuitry 1811 architecturally commits the destination register into the registers or memory 1808 and retires the instruction.

Detailed below are examples of computer architectures, systems, cores, instruction formats, etc. that support one or more examples detailed above.

Exemplary Computer Architectures

Detailed below are describes of exemplary computer architectures. Other system designs and configurations known in the arts for laptops, desktops, handheld PCs, personal digital assistants, engineering workstations, servers, network devices, network hubs, switches, embedded processors, digital signal processors (DSPs), graphics devices, video game devices, set-top boxes, micro controllers, cell phones, portable media players, hand held devices, and various other electronic devices, are also suitable. In general, a huge variety of systems or electronic devices capable of incorporating a processor and/or other execution logic as disclosed herein are generally suitable.

FIG. 19 illustrates examples of an exemplary system. Multiprocessor system 1900 is a point-to-point interconnect system and includes a plurality of processors including a first processor 1970 and a second processor 1980 coupled via a point-to-point interconnect 1950. In some examples, the first processor 1970 and the second processor 1980 are homogeneous. In some examples, first processor 1970 and the second processor 1980 are heterogenous.

Processors 1970 and 1980 are shown including integrated memory controller (IMC) units circuitry 1972 and 1982, respectively. Processor 1970 also includes as part of its interconnect controller units point-to-point (P-P) interfaces 1976 and 1978; similarly, second processor 1980 includes P-P interfaces 1986 and 1988. Processors 1970, 1980 may exchange information via the point-to-point (P-P) interconnect 1950 using P-P interface circuits 1978, 1988. IMCs 1972 and 1982 couple the processors 1970, 1980 to respective memories, namely a memory 1932 and a memory 1934, which may be portions of main memory locally attached to the respective processors.

Processors 1970, 1980 may each exchange information with a chipset 1990 via individual P-P interconnects 1952, 1954 using point to point interface circuits 1976, 1994, 1986, 1998. Chipset 1990 may optionally exchange information with a coprocessor 1938 via a high-performance interface 1992. In some examples, the coprocessor 1938 is a special-purpose processor, such as, for example, a high-throughput MIC processor, a network or communication processor, compression engine, graphics processor, GPGPU, embedded processor, or the like.

A shared cache (not shown) may be included in either processor 1970, 1980 or outside of both processors, yet connected with the processors via P-P interconnect, such that either or both processors' local cache information may be stored in the shared cache if a processor is placed into a low power mode.

Chipset 1990 may be coupled to a first interconnect 1916 via an interface 1996. In some examples, first interconnect 1916 may be a Peripheral Component Interconnect (PCI) interconnect, or an interconnect such as a PCI Express interconnect or another I/O interconnect. In some examples, one of the interconnects couples to a power control unit (PCU) 1917, which may include circuitry, software, and/or firmware to perform power management operations with regard to the processors 1970, 1980 and/or co-processor 1938. PCU 1917 provides control information to a voltage regulator to cause the voltage regulator to generate the appropriate regulated voltage. PCU 1917 also provides control information to control the operating voltage generated. In various examples, PCU 1917 may include a variety of power management logic units (circuitry) to perform hardware-based power management. Such power management may be wholly processor controlled (e.g., by various processor hardware, and which may be triggered by workload and/or power, thermal or other processor constraints) and/or the power management may be performed responsive to external sources (such as a platform or power management source or system software).

PCU 1917 is illustrated as being present as logic separate from the processor 1970 and/or processor 1980. In other cases, PCU 1917 may execute on a given one or more of cores (not shown) of processor 1970 or 1980. In some cases, PCU 1917 may be implemented as a microcontroller (dedicated or general-purpose) or other control logic configured to execute its own dedicated power management code, sometimes referred to as P-code. In yet other examples, power management operations to be performed by PCU 1917 may be implemented externally to a processor, such as by way of a separate power management integrated circuit (PMIC) or another component external to the processor. In yet other examples, power management operations to be performed by PCU 1917 may be implemented within BIOS or other system software.

Various I/O devices 1914 may be coupled to first interconnect 1916, along with an interconnect (bus) bridge 1918 which couples first interconnect 1916 to a second interconnect 1920. In some examples, one or more additional processor(s) 1915, such as coprocessors, high-throughput MIC processors, GPGPU's, accelerators (such as, e.g., graphics accelerators or digital signal processing (DSP) units), field programmable gate arrays (FPGAs), or any other processor, are coupled to first interconnect 1916. In some examples, second interconnect 1920 may be a low pin count (LPC) interconnect. Various devices may be coupled to second interconnect 1920 including, for example, a keyboard and/or mouse 1922, communication devices 1927 and a storage unit circuitry 1928. Storage unit circuitry 1928 may be a disk drive or other mass storage device which may include instructions/code and data 1930, in some examples. Further, an audio I/O 1924 may be coupled to second interconnect 1920. Note that other architectures than the point-to-point architecture described above are possible. For example, instead of the point-to-point architecture, a system such as multiprocessor system 1900 may implement a multi-drop interconnect or other such architecture.

Exemplary Core Architectures, Processors, and Computer Architectures

Processor cores may be implemented in different ways, for different purposes, and in different processors. For instance, implementations of such cores may include: 1) a general purpose in-order core intended for general-purpose computing; 2) a high performance general purpose out-of-order core intended for general-purpose computing; 3) a special purpose core intended primarily for graphics and/or scientific (throughput) computing. Implementations of different processors may include: 1) a CPU including one or more general purpose in-order cores intended for general-purpose computing and/or one or more general purpose out-of-order cores intended for general-purpose computing; and 2) a coprocessor including one or more special purpose cores intended primarily for graphics and/or scientific (throughput). Such different processors lead to different computer system architectures, which may include: 1) the coprocessor on a separate chip from the CPU; 2) the coprocessor on a separate die in the same package as a CPU; 3) the coprocessor on the same die as a CPU (in which case, such a coprocessor is sometimes referred to as special purpose logic, such as integrated graphics and/or scientific (throughput) logic, or as special purpose cores); and 4) a system on a chip that may include on the same die as the described CPU (sometimes referred to as the application core(s) or application processor(s)), the above described coprocessor, and additional functionality. Exemplary core architectures are described next, followed by descriptions of exemplary processors and computer architectures.

FIG. 20 illustrates a block diagram of examples of a processor 2000 that may have more than one core, may have an integrated memory controller, and may have integrated graphics. The solid lined boxes illustrate a processor 2000 with a single core 2002A, a system agent 2010, a set of one or more interconnect controller units circuitry 2016, while the optional addition of the dashed lined boxes illustrates an alternative processor 2000 with multiple cores 2002(A)-(N), a set of one or more integrated memory controller unit(s) circuitry 2014 in the system agent unit circuitry 2010, and special purpose logic 2008, as well as a set of one or more interconnect controller units circuitry 2016. Note that the processor 2000 may be one of the processors 1970 or 1980, or co-processor 1938 or 1915 of FIG. 19.

Thus, different implementations of the processor 2000 may include: 1) a CPU with the special purpose logic 2008 being integrated graphics and/or scientific (throughput) logic (which may include one or more cores, not shown), and the cores 2002(A)-(N) being one or more general purpose cores (e.g., general purpose in-order cores, general purpose out-of-order cores, or a combination of the two); 2) a coprocessor with the cores 2002(A)-(N) being a large number of special purpose cores intended primarily for graphics and/or scientific (throughput); and 3) a coprocessor with the cores 2002(A)-(N) being a large number of general purpose in-order cores. Thus, the processor 2000 may be a general-purpose processor, coprocessor or special-purpose processor, such as, for example, a network or communication processor, compression engine, graphics processor, GPGPU (general purpose graphics processing unit circuitry), a high-throughput many integrated core (MIC) coprocessor (including 30 or more cores), embedded processor, or the like. The processor may be implemented on one or more chips. The processor 2000 may be a part of and/or may be implemented on one or more substrates using any of a number of process technologies, such as, for example, BiCMOS, CMOS, or NMOS.

A memory hierarchy includes one or more levels of cache unit(s) circuitry 2004(A)-(N) within the cores 2002(A)-(N), a set of one or more shared cache units circuitry 2006, and external memory (not shown) coupled to the set of integrated memory controller units circuitry 2014. The set of one or more shared cache units circuitry 2006 may include one or more mid-level caches, such as level 2 (L2), level 3 (L3), level 4 (L4), or other levels of cache, such as a last level cache (LLC), and/or combinations thereof. While in some examples ring-based interconnect network circuitry 2012 interconnects the special purpose logic 2008 (e.g., integrated graphics logic), the set of shared cache units circuitry 2006, and the system agent unit circuitry 2010, alternative examples use any number of well-known techniques for interconnecting such units. In some examples, coherency is maintained between one or more of the shared cache units circuitry 2006 and cores 2002(A)-(N).

In some examples, one or more of the cores 2002(A)-(N) are capable of multi-threading. The system agent unit circuitry 2010 includes those components coordinating and operating cores 2002(A)-(N). The system agent unit circuitry 2010 may include, for example, power control unit (PCU) circuitry and/or display unit circuitry (not shown). The PCU may be or may include logic and components needed for regulating the power state of the cores 2002(A)-(N) and/or the special purpose logic 2008 (e.g., integrated graphics logic). The display unit circuitry is for driving one or more externally connected displays.

The cores 2002(A)-(N) may be homogenous or heterogeneous in terms of architecture instruction set; that is, two or more of the cores 2002(A)-(N) may be capable of executing the same instruction set, while other cores may be capable of executing only a subset of that instruction set or a different instruction set.

Exemplary Core Architectures
In-Order and Out-of-Order Core Block Diagram

FIG. 21(A) is a block diagram illustrating both an exemplary in-order pipeline and an exemplary register renaming, out-of-order issue/execution pipeline according to examples. FIG. 21(B) is a block diagram illustrating both an exemplary example of an in-order architecture core and an exemplary register renaming, out-of-order issue/execution architecture core to be included in a processor according to examples. The solid lined boxes in FIGS. 21(A)-(B) illustrate the in-order pipeline and in-order core, while the optional addition of the dashed lined boxes illustrates the register renaming, out-of-order issue/execution pipeline and core. Given that the in-order aspect is a subset of the out-of-order aspect, the out-of-order aspect will be described.

In FIG. 21(A), a processor pipeline 2100 includes a fetch stage 2102, an optional length decode stage 2104, a decode stage 2106, an optional allocation stage 2108, an optional renaming stage 2110, a scheduling (also known as a dispatch or issue) stage 2112, an optional register read/memory read stage 2114, an execute stage 2116, a write back/memory write stage 2118, an optional exception handling stage 2122, and an optional commit stage 2124. One or more operations can be performed in each of these processor pipeline stages. For example, during the fetch stage 2102, one or more instructions are fetched from instruction memory, during the decode stage 2106, the one or more fetched instructions may be decoded, addresses (e.g., load store unit (LSU) addresses) using forwarded register ports may be generated, and branch forwarding (e.g., immediate offset or an link register (LR)) may be performed. In one example, the decode stage 2106 and the register read/memory read stage 2114 may be combined into one pipeline stage. In one example, during the execute stage 2116, the decoded instructions may be executed, LSU address/data pipelining to an Advanced Microcontroller Bus (AHB) interface may be performed, multiply and add operations may be performed, arithmetic operations with branch results may be performed, etc.

By way of example, the exemplary register renaming, out-of-order issue/execution core architecture may implement the pipeline 2100 as follows: 1) the instruction fetch 2138 performs the fetch and length decoding stages 2102 and 2104; 2) the decode unit circuitry 2140 performs the decode stage 2106; 3) the rename/allocator unit circuitry 2152 performs the allocation stage 2108 and renaming stage 2110; 4) the scheduler unit(s) circuitry 2156 performs the schedule stage 2112; 5) the physical register file(s) unit(s) circuitry 2158 and the memory unit circuitry 2170 perform the register read/memory read stage 2114; the execution cluster 2160 perform the execute stage 2116; 6) the memory unit circuitry 2170 and the physical register file(s) unit(s) circuitry 2158 perform the write back/memory write stage 2118; 7) various units (unit circuitry) may be involved in the exception handling stage 2122; and 8) the retirement unit circuitry 2154 and the physical register file(s) unit(s) circuitry 2158 perform the commit stage 2124.

FIG. 21(B) shows processor core 2190 including front-end unit circuitry 2130 coupled to an execution engine unit circuitry 2150, and both are coupled to a memory unit circuitry 2170. The core 2190 may be a reduced instruction set computing (RISC) core, a complex instruction set computing (CISC) core, a very long instruction word (VLIW) core, or a hybrid or alternative core type. As yet another option, the core 2190 may be a special-purpose core, such as, for example, a network or communication core, compression engine, coprocessor core, general purpose computing graphics processing unit (GPGPU) core, graphics core, or the like.

The front end unit circuitry 2130 may include branch prediction unit circuitry 2132 coupled to an instruction cache unit circuitry 2134, which is coupled to an instruction translation lookaside buffer (TLB) 2136, which is coupled to instruction fetch unit circuitry 2138, which is coupled to decode unit circuitry 2140. In one example, the instruction cache unit circuitry 2134 is included in the memory unit circuitry 2170 rather than the front-end unit circuitry 2130. The decode unit circuitry 2140 (or decoder) may decode instructions, and generate as an output one or more micro-operations, micro-code entry points, microinstructions, other instructions, or other control signals, which are decoded from, or which otherwise reflect, or are derived from, the original instructions. The decode unit circuitry 2140 may further include an address generation unit circuitry (AGU, not shown). In one example, the AGU generates an LSU address using forwarded register ports, and may further perform branch forwarding (e.g., immediate offset branch forwarding, LR register branch forwarding, etc.). The decode unit circuitry 2140 may be implemented using various different mechanisms. Examples of suitable mechanisms include, but are not limited to, look-up tables, hardware implementations, programmable logic arrays (PLAs), microcode read only memories (ROMs), etc. In one example, the core 2190 includes a microcode ROM (not shown) or other medium that stores microcode for certain macroinstructions (e.g., in decode unit circuitry 2140 or otherwise within the front end unit circuitry 2130). In one example, the decode unit circuitry 2140 includes a micro-operation (micro-op) or operation cache (not shown) to hold/cache decoded operations, micro-tags, or micro-operations generated during the decode or other stages of the processor pipeline 2100. The decode unit circuitry 2140 may be coupled to rename/allocator unit circuitry 2152 in the execution engine unit circuitry 2150.

The execution engine circuitry 2150 includes the rename/allocator unit circuitry 2152 coupled to a retirement unit circuitry 2154 and a set of one or more scheduler(s) circuitry 2156. The scheduler(s) circuitry 2156 represents any number of different schedulers, including reservations stations, central instruction window, etc. In some examples, the scheduler(s) circuitry 2156 can include arithmetic logic unit (ALU) scheduler/scheduling circuitry, ALU queues, arithmetic generation unit (AGU) scheduler/scheduling circuitry, AGU queues, etc. The scheduler(s) circuitry 2156 is coupled to the physical register file(s) circuitry 2158. Each of the physical register file(s) circuitry 2158 represents one or more physical register files, different ones of which store one or more different data types, such as scalar integer, scalar floating-point, packed integer, packed floating-point, vector integer, vector floating-point, status (e.g., an instruction pointer that is the address of the next instruction to be executed), etc. In one example, the physical register file(s) unit circuitry 2158 includes vector registers unit circuitry, writemask registers unit circuitry, and scalar register unit circuitry. These register units may provide architectural vector registers, vector mask registers, general-purpose registers, etc. The physical register file(s) unit(s) circuitry 2158 is overlapped by the retirement unit circuitry 2154 (also known as a retire queue or a retirement queue) to illustrate various ways in which register renaming and out-of-order execution may be implemented (e.g., using a reorder buffer(s) (ROB(s)) and a retirement register file(s); using a future file(s), a history buffer(s), and a retirement register file(s); using a register maps and a pool of registers; etc.). The retirement unit circuitry 2154 and the physical register file(s) circuitry 2158 are coupled to the execution cluster(s) 2160. The execution cluster(s) 2160 includes a set of one or more execution units circuitry 2162 and a set of one or more memory access circuitry 2164. The execution units circuitry 2162 may perform various arithmetic, logic, floating-point or other types of operations (e.g., shifts, addition, subtraction, multiplication) and on various types of data (e.g., scalar floating-point, packed integer, packed floating-point, vector integer, vector floating-point). While some examples may include a number of execution units or execution unit circuitry dedicated to specific functions or sets of functions, other examples may include only one execution unit circuitry or multiple execution units/execution unit circuitry that all perform all functions. The scheduler(s) circuitry 2156, physical register file(s) unit(s) circuitry 2158, and execution cluster(s) 2160 are shown as being possibly plural because certain examples create separate pipelines for certain types of data/operations (e.g., a scalar integer pipeline, a scalar floating-point/packed integer/packed floating-point/vector integer/vector floating-point pipeline, and/or a memory access pipeline that each have their own scheduler circuitry, physical register file(s) unit circuitry, and/or execution cluster—and in the case of a separate memory access pipeline, certain examples are implemented in which only the execution cluster of this pipeline has the memory access unit(s) circuitry 2164). It should also be understood that where separate pipelines are used, one or more of these pipelines may be out-of-order issue/execution and the rest in-order.

In some examples, the execution engine unit circuitry 2150 may perform load store unit (LSU) address/data pipelining to an Advanced Microcontroller Bus (AHB) interface (not shown), and address phase and writeback, data phase load, store, and branches.

The set of memory access circuitry 2164 is coupled to the memory unit circuitry 2170, which includes data TLB unit circuitry 2172 coupled to a data cache circuitry 2174 coupled to a level 2 (L2) cache circuitry 2176. In one exemplary example, the memory access units circuitry 2164 may include a load unit circuitry, a store address unit circuit, and a store data unit circuitry, each of which is coupled to the data TLB circuitry 2172 in the memory unit circuitry 2170. The instruction cache circuitry 2134 is further coupled to a level 2 (L2) cache unit circuitry 2176 in the memory unit circuitry 2170. In one example, the instruction cache 2134 and the data cache 2174 are combined into a single instruction and data cache (not shown) in L2 cache unit circuitry 2176, a level 3 (L3) cache unit circuitry (not shown), and/or main memory. The L2 cache unit circuitry 2176 is coupled to one or more other levels of cache and eventually to a main memory.

The core 2190 may support one or more instructions sets (e.g., the x86 instruction set (with some extensions that have been added with newer versions); the MIPS instruction set; the ARM instruction set (with optional additional extensions such as NEON)), including the instruction(s) described herein. In one example, the core 2190 includes logic to support a packed data instruction set extension (e.g., AVX1, AVX2), thereby allowing the operations used by many multimedia applications to be performed using packed data.

Exemplary Execution Unit(s) Circuitry

FIG. 22 illustrates examples of execution unit(s) circuitry, such as execution unit(s) circuitry 2162 of FIG. 21(B). As illustrated, execution unit(s) circuitry 2162 may include one or more ALU circuits 2201, vector/SIMD unit circuits 2203, load/store unit circuits 2205, and/or branch/jump unit circuits 2207. ALU circuits 2201 perform integer arithmetic and/or Boolean operations. Vector/SIMD unit circuits 2203 perform vector/SIMD operations on packed data (such as SIMD/vector registers). Load/store unit circuits 2205 execute load and store instructions to load data from memory into registers or store from registers to memory. Load/store unit circuits 2205 may also generate addresses. Branch/jump unit circuits 2207 cause a branch or jump to a memory address depending on the instruction. Floating-point unit (FPU) circuits 2209 perform floating-point arithmetic. The width of the execution unit(s) circuitry 2162 varies depending upon the example and can range from 16-bit to 1,024-bit. In some examples, two or more smaller execution units are logically combined to form a larger execution unit (e.g., two 128-bit execution units are logically combined to form a 256-bit execution unit).

Exemplary Register Architecture

FIG. 23 is a block diagram of a register architecture 2300 according to some examples. As illustrated, there are vector/SIMD registers 2310 that vary from 128-bit to 1,024 bits width. In some examples, the vector/SIMD registers 2310 are physically 512-bits and, depending upon the mapping, only some of the lower bits are used. For example, in some examples, the vector/SIMD registers 2310 are ZMM registers which are 512 bits: the lower 256 bits are used for YMM registers and the lower 128 bits are used for XMM registers. As such, there is an overlay of registers. In some examples, a vector length field selects between a maximum length and one or more other shorter lengths, where each such shorter length is half the length of the preceding length. Scalar operations are operations performed on the lowest order data element position in a ZMM/YMM/XMM register; the higher order data element positions are either left the same as they were prior to the instruction or zeroed depending on the example.

In some examples, the register architecture 2300 includes writemask/predicate registers 2315. For example, in some examples, there are 8 writemask/predicate registers (sometimes called k0 through k7) that are each 16-bit, 32-bit, 64-bit, or 128-bit in size. Writemask/predicate registers 2315 may allow for merging (e.g., allowing any set of elements in the destination to be protected from updates during the execution of any operation) and/or zeroing (e.g., zeroing vector masks allow any set of elements in the destination to be zeroed during the execution of any operation). In some examples, each data element position in a given writemask/predicate register 2315 corresponds to a data element position of the destination. In other examples, the writemask/predicate registers 2315 are scalable and consists of a set number of enable bits for a given vector element (e.g., 8 enable bits per 64-bit vector element).

The register architecture 2300 includes a plurality of general-purpose registers 2325. These registers may be 16-bit, 32-bit, 64-bit, etc. and can be used for scalar operations. In some examples, these registers are referenced by the names RAX, RBX, RCX, RDX, RBP, RSI, RDI, RSP, and R8 through R15.

In some examples, the register architecture 2300 includes scalar floating-point register 2345 which is used for scalar floating-point operations on 32/64/80-bit floating-point data using the x87 instruction set extension or as MMX registers to perform operations on 64-bit packed integer data, as well as to hold operands for some operations performed between the MMX and XMM registers.

One or more flag registers 2340 (e.g., EFLAGS, RFLAGS, etc.) store status and control information for arithmetic, compare, and system operations. For example, the one or more flag registers 2340 may store condition code information such as carry, parity, auxiliary carry, zero, sign, and overflow. In some examples, the one or more flag registers 2340 are called program status and control registers.

Segment registers 2320 contain segment points for use in accessing memory. In some examples, these registers are referenced by the names CS, DS, SS, ES, FS, and GS.

Machine specific registers (MSRs) 2335 control and report on processor performance. Most MSRs 2335 handle system-related functions and are not accessible to an application program. Machine check registers 2360 consist of control, status, and error reporting MSRs that are used to detect and report on hardware errors.

One or more instruction pointer register(s) 2330 store an instruction pointer value. Control register(s) 2355 (e.g., CR0-CR4) determine the operating mode of a processor (e.g., processor 1970, 1980, 1938, 1915, and/or 2000) and the characteristics of a currently executing task. Debug registers 2350 control and allow for the monitoring of a processor or core's debugging operations.

Memory management registers 2365 specify the locations of data structures used in protected mode memory management. These registers may include a GDTR, IDRT, task register, and a LDTR register.

Alternative examples may use wider or narrower registers. Additionally, alternative examples may use more, less, or different register files and registers.

Instruction Sets

An instruction set architecture (ISA) may include one or more instruction formats. A given instruction format may define various fields (e.g., number of bits, location of bits) to specify, among other things, the operation to be performed (e.g., opcode) and the operand(s) on which that operation is to be performed and/or other data field(s) (e.g., mask). Some instruction formats are further broken down though the definition of instruction templates (or sub-formats). For example, the instruction templates of a given instruction format may be defined to have different subsets of the instruction format's fields (the included fields are typically in the same order, but at least some have different bit positions because there are less fields included) and/or defined to have a given field interpreted differently. Thus, each instruction of an ISA is expressed using a given instruction format (and, if defined, in a given one of the instruction templates of that instruction format) and includes fields for specifying the operation and the operands. For example, an exemplary ADD instruction has a specific opcode and an instruction format that includes an opcode field to specify that opcode and operand fields to select operands (source1/destination and source2); and an occurrence of this ADD instruction in an instruction stream will have specific contents in the operand fields that select specific operands.

Exemplary Instruction Formats

Examples of the instruction(s) described herein may be embodied in different formats. Additionally, exemplary systems, architectures, and pipelines are detailed below. Examples of the instruction(s) may be executed on such systems, architectures, and pipelines, but are not limited to those detailed.

FIG. 24 illustrates examples of an instruction format. As illustrated, an instruction may include multiple components including, but not limited to, one or more fields for: one or more prefixes 2401, an opcode 2403, addressing information 2405 (e.g., register identifiers, memory addressing information, etc.), a displacement value 2407, and/or an immediate 2409. Note that some instructions utilize some or all of the fields of the format whereas others may only use the field for the opcode 2403. In some examples, the order illustrated is the order in which these fields are to be encoded, however, it should be appreciated that in other examples these fields may be encoded in a different order, combined, etc.

The prefix(es) field(s) 2401, when used, modifies an instruction. In some examples, one or more prefixes are used to repeat string instructions (e.g., 0xF0, 0xF2, 0xF3, etc.), to provide section overrides (e.g., 0x2E, 0x36, 0x3E, 0x26, 0x64, 0x65, 0x2E, 0x3E, etc.), to perform bus lock operations, and/or to change operand (e.g., 0x66) and address sizes (e.g., 0x67). Certain instructions require a mandatory prefix (e.g., 0x66, 0xF2, 0xF3, etc.). Certain of these prefixes may be considered “legacy” prefixes. Other prefixes, one or more examples of which are detailed herein, indicate, and/or provide further capability, such as specifying particular registers, etc. The other prefixes typically follow the “legacy” prefixes.

The opcode field 2403 is used to at least partially define the operation to be performed upon a decoding of the instruction. In some examples, a primary opcode encoded in the opcode field 2403 is 1, 2, or 3 bytes in length. In other examples, a primary opcode can be a different length. An additional 3-bit opcode field is sometimes encoded in another field.

The addressing field 2405 is used to address one or more operands of the instruction, such as a location in memory or one or more registers. FIG. 25 illustrates examples of the addressing field 2405. In this illustration, an optional ModR/M byte 2502 and an optional Scale, Index, Base (SIB) byte 2504 are shown. The ModR/M byte 2502 and the SIB byte 2504 are used to encode up to two operands of an instruction, each of which is a direct register or effective memory address. Note that each of these fields are optional in that not all instructions include one or more of these fields. The MOD R/M byte 2502 includes a MOD field 2542, a register field 2544, and R/M field 2546.

The content of the MOD field 2542 distinguishes between memory access and non-memory access modes. In some examples, when the MOD field 2542 has a value of b11, a register-direct addressing mode is utilized, and otherwise register-indirect addressing is used.

The register field 2544 may encode either the destination register operand or a source register operand, or may encode an opcode extension and not be used to encode any instruction operand. The content of register index field 2544, directly or through address generation, specifies the locations of a source or destination operand (either in a register or in memory). In some examples, the register field 2544 is supplemented with an additional bit from a prefix (e.g., prefix 2401) to allow for greater addressing.

The R/M field 2546 may be used to encode an instruction operand that references a memory address, or may be used to encode either the destination register operand or a source register operand. Note the R/M field 2546 may be combined with the MOD field 2542 to dictate an addressing mode in some examples.

The SIB byte 2504 includes a scale field 2552, an index field 2554, and a base field 2556 to be used in the generation of an address. The scale field 2552 indicates scaling factor. The index field 2554 specifies an index register to use. In some examples, the index field 2554 is supplemented with an additional bit from a prefix (e.g., prefix 2401) to allow for greater addressing. The base field 2556 specifies a base register to use. In some examples, the base field 2556 is supplemented with an additional bit from a prefix (e.g., prefix 2401) to allow for greater addressing. In practice, the content of the scale field 2552 allows for the scaling of the content of the index field 2554 for memory address generation (e.g., for address generation that uses 2^scale*index+base).

Some addressing forms utilize a displacement value to generate a memory address. For example, a memory address may be generated according to 2^scale*index+base+displacement, index*scale+displacement, r/m+displacement, instruction pointer (RIP/EIP)+displacement, register+displacement, etc. The displacement may be a 1-byte, 2-byte, 4-byte, etc. value. In some examples, a displacement field 2407 provides this value. Additionally, in some examples, a displacement factor usage is encoded in the MOD field of the addressing field 2405 that indicates a compressed displacement scheme for which a displacement value is calculated by multiplying disp8 in conjunction with a scaling factor N that is determined based on the vector length, the value of a b bit, and the input element size of the instruction. The displacement value is stored in the displacement field 2407.

In some examples, an immediate field 2409 specifies an immediate for the instruction. An immediate may be encoded as a 1-byte value, a 2-byte value, a 4-byte value, etc.

FIG. 26 illustrates examples of a first prefix 2401(A). In some examples, the first prefix 2401(A) is an example of a REX prefix. Instructions that use this prefix may specify general purpose registers, 64-bit packed data registers (e.g., single instruction, multiple data (SIMD) registers or vector registers), and/or control registers and debug registers (e.g., CR8-CR15 and DR8-DR15).

Instructions using the first prefix 2401(A) may specify up to three registers using 3-bit fields depending on the format: 1) using the reg field 2544 and the R/M field 2546 of the Mod R/M byte 2502; 2) using the Mod R/M byte 2502 with the SIB byte 2504 including using the reg field 2544 and the base field 2556 and index field 2554; or 3) using the register field of an opcode.

In the first prefix 2401(A), bit positions 7:4 are set as 0100. Bit position 3 (W) can be used to determine the operand size, but may not solely determine operand width. As such, when W=0, the operand size is determined by a code segment descriptor (CS.D) and when W=1, the operand size is 64-bit.

Note that the addition of another bit allows for 16 (2⁴) registers to be addressed, whereas the MOD R/M reg field 2544 and MOD R/M R/M field 2546 alone can each only address 8 registers.

In the first prefix 2401(A), bit position 2 (R) may an extension of the MOD R/M reg field 2544 and may be used to modify the ModR/M reg field 2544 when that field encodes a general purpose register, a 64-bit packed data register (e.g., a SSE register), or a control or debug register. R is ignored when Mod R/M byte 2502 specifies other registers or defines an extended opcode.

Bit position 1 (X) X bit may modify the SIB byte index field 2554.

Bit position B (B) B may modify the base in the Mod R/M R/M field 2546 or the SIB byte base field 2556; or it may modify the opcode register field used for accessing general purpose registers (e.g., general purpose registers 2325).

FIGS. 27(A)-(D) illustrate examples of how the R, X, and B fields of the first prefix 2401(A) are used. FIG. 27(A) illustrates R and B from the first prefix 2401(A) being used to extend the reg field 2544 and R/M field 2546 of the MOD R/M byte 2502 when the SIB byte 2504 is not used for memory addressing. FIG. 27(B) illustrates R and B from the first prefix 2401(A) being used to extend the reg field 2544 and R/M field 2546 of the MOD R/M byte 2502 when the SIB byte 2504 is not used (register-register addressing). FIG. 27(C) illustrates R, X, and B from the first prefix 2401(A) being used to extend the reg field 2544 of the MOD R/M byte 2502 and the index field 2554 and base field 2556 when the SIB byte 2504 being used for memory addressing. FIG. 27(D) illustrates B from the first prefix 2401(A) being used to extend the reg field 2544 of the MOD R/M byte 2502 when a register is encoded in the opcode 2403.

FIGS. 28(A)-(B) illustrate examples of a second prefix 2401(B). In some examples, the second prefix 2401(B) is an example of a VEX prefix. The second prefix 2401(B) encoding allows instructions to have more than two operands, and allows SIMD vector registers (e.g., vector/SIMD registers 2310) to be longer than 64-bits (e.g., 128-bit and 256-bit). The use of the second prefix 2401(B) provides for three-operand (or more) syntax. For example, previous two-operand instructions performed operations such as A=A+B, which overwrites a source operand. The use of the second prefix 2401(B) enables operands to perform nondestructive operations such as A=B+C.

In some examples, the second prefix 2401(B) comes in two forms—a two-byte form and a three-byte form. The two-byte second prefix 2401(B) is used mainly for 128-bit, scalar, and some 256-bit instructions; while the three-byte second prefix 2401(B) provides a compact replacement of the first prefix 2401(A) and 3-byte opcode instructions.

FIG. 28(A) illustrates examples of a two-byte form of the second prefix 2401(B). In one example, a format field 2801 (byte 0 2803) contains the value CSH. In one example, byte 1 2805 includes a “R” value in bit[7]. This value is the complement of the same value of the first prefix 2401(A). Bit[2] is used to dictate the length (L) of the vector (where a value of 0 is a scalar or 128-bit vector and a value of 1 is a 256-bit vector). Bits[1:0] provide opcode extensionality equivalent to some legacy prefixes (e.g., 00=no prefix, 01=66H, 10=F3H, and 11=F2H). Bits[6:3] shown as vvvv may be used to: 1) encode the first source register operand, specified in inverted (1s complement) form and valid for instructions with 2 or more source operands; 2) encode the destination register operand, specified in 1s complement form for certain vector shifts; or 3) not encode any operand, the field is reserved and should contain a certain value, such as 1111b.

Instructions that use this prefix may use the Mod R/M R/M field 2546 to encode the instruction operand that references a memory address or encode either the destination register operand or a source register operand.

Instructions that use this prefix may use the Mod R/M reg field 2544 to encode either the destination register operand or a source register operand, be treated as an opcode extension and not used to encode any instruction operand.

For instruction syntax that support four operands, vvvv, the Mod R/M R/M field 2546 and the Mod R/M reg field 2544 encode three of the four operands. Bits[7:4] of the immediate 2409 are then used to encode the third source register operand.

FIG. 28(B) illustrates examples of a three-byte form of the second prefix 2401(B). in one example, a format field 2811 (byte 0 2813) contains the value C4H. Byte 1 2815 includes in bits[7:5] “R,” “X,” and “B” which are the complements of the same values of the first prefix 2401(A). Bits[4:0] of byte 1 2815 (shown as mmmmm) include content to encode, as need, one or more implied leading opcode bytes. For example, 00001 implies a 0FH leading opcode, 00010 implies a 0F38H leading opcode, 00011 implies a leading 0F3AH opcode, etc.

Bit[7] of byte 2 2817 is used similar to W of the first prefix 2401(A) including helping to determine promotable operand sizes. Bit[2] is used to dictate the length (L) of the vector (where a value of 0 is a scalar or 128-bit vector and a value of 1 is a 256-bit vector). Bits[1:0] provide opcode extensionality equivalent to some legacy prefixes (e.g., 00=no prefix, 01=66H, 10=F3H, and 11=F2H). Bits[6:3], shown as vvvv, may be used to: 1) encode the first source register operand, specified in inverted (1s complement) form and valid for instructions with 2 or more source operands; 2) encode the destination register operand, specified in 1s complement form for certain vector shifts; or 3) not encode any operand, the field is reserved and should contain a certain value, such as 1111b.

For instruction syntax that support four operands, vvvv, the Mod R/M R/M field 2546, and the Mod R/M reg field 2544 encode three of the four operands. Bits[7:4] of the immediate 2409 are then used to encode the third source register operand.

FIG. 29 illustrates examples of a third prefix 2401(C). In some examples, the first prefix 2401(A) is an example of an EVEX prefix. The third prefix 2401(C) is a four-byte prefix.

The third prefix 2401(C) can encode 32 vector registers (e.g., 128-bit, 256-bit, and 512-bit registers) in 64-bit mode. In some examples, instructions that utilize a writemask/opmask (see discussion of registers in a previous figure, such as FIG. 23) or predication utilize this prefix. Opmask register allow for conditional processing or selection control. Opmask instructions, whose source/destination operands are opmask registers and treat the content of an opmask register as a single value, are encoded using the second prefix 2401(B).

The third prefix 2401(C) may encode functionality that is specific to instruction classes (e.g., a packed instruction with “load+op” semantic can support embedded broadcast functionality, a floating-point instruction with rounding semantic can support static rounding functionality, a floating-point instruction with non-rounding arithmetic semantic can support “suppress all exceptions” functionality, etc.).

The first byte of the third prefix 2401(C) is a format field 2911 that has a value, in one example, of 62H. Subsequent bytes are referred to as payload bytes 2915-2919 and collectively form a 24-bit value of P[23:0] providing specific capability in the form of one or more fields (detailed herein).

In some examples, P[1:0] of payload byte 2919 are identical to the low two mmmmm bits. P[3:2] are reserved in some examples. Bit P[4] (R′) allows access to the high 16 vector register set when combined with P[7] and the ModR/M reg field 2544. P[6] can also provide access to a high 16 vector register when SIB-type addressing is not needed. P[7:5] consist of an R, X, and B which are operand specifier modifier bits for vector register, general purpose register, memory addressing and allow access to the next set of 8 registers beyond the low 8 registers when combined with the ModR/M register field 2544 and ModR/M R/M field 2546. P[9:8] provide opcode extensionality equivalent to some legacy prefixes (e.g., 00=no prefix, 01=66H, 10=F3H, and 11=F2H). P[10] in some examples is a fixed value of 1. P[14:11], shown as vvvv, may be used to: 1) encode the first source register operand, specified in inverted (1s complement) form and valid for instructions with 2 or more source operands; 2) encode the destination register operand, specified in 1s complement form for certain vector shifts; or 3) not encode any operand, the field is reserved and should contain a certain value, such as 1111b.

P[15] is similar to W of the first prefix 2401(A) and second prefix 2411(B) and may serve as an opcode extension bit or operand size promotion.

P[18:16] specify the index of a register in the opmask (writemask) registers (e.g., writemask/predicate registers 2315). In one example, the specific value aaa=000 has a special behavior implying no opmask is used for the particular instruction (this may be implemented in a variety of ways including the use of a opmask hardwired to all ones or hardware that bypasses the masking hardware). When merging, vector masks allow any set of elements in the destination to be protected from updates during the execution of any operation (specified by the base operation and the augmentation operation); in other one example, preserving the old value of each element of the destination where the corresponding mask bit has a 0. In contrast, when zeroing vector masks allow any set of elements in the destination to be zeroed during the execution of any operation (specified by the base operation and the augmentation operation); in one example, an element of the destination is set to 0 when the corresponding mask bit has a 0 value. A subset of this functionality is the ability to control the vector length of the operation being performed (that is, the span of elements being modified, from the first to the last one); however, it is not necessary that the elements that are modified be consecutive. Thus, the opmask field allows for partial vector operations, including loads, stores, arithmetic, logical, etc. While examples are described in which the opmask field's content selects one of a number of opmask registers that contains the opmask to be used (and thus the opmask field's content indirectly identifies that masking to be performed), alternative examples instead or additional allow the mask write field's content to directly specify the masking to be performed.

P[19] can be combined with P[14:11] to encode a second source vector register in a non-destructive source syntax which can access an upper 16 vector registers using P[19]. P[20] encodes multiple functionalities, which differs across different classes of instructions and can affect the meaning of the vector length/rounding control specifier field (P[22:21]). P[23] indicates support for merging-writemasking (e.g., when set to 0) or support for zeroing and merging-writemasking (e.g., when set to 1).

Exemplary examples of encoding of registers in instructions using the third prefix 2401(C) are detailed in the following tables.

TABLE 1

32-Register Support in 64-bit Mode

4
3
[2:0]
REG. TYPE
COMMON USAGES

REG
R′
R
ModR/M
GPR, Vector
Destination or Source

reg

VVVV
V′
vvvv
GPR, Vector
2nd Source or Destination

RM
X
B
ModR/M
GPR, Vector
1st Source or Destination

R/M

BASE
0
B
ModR/M
GPR
Memory addressing

R/M

INDEX
0
X
SIB.index
GPR
Memory addressing

VIDX
V′
X
SIB.index
Vector
VSIB memory addressing

TABLE 2

Encoding Register Specifiers in 32-bit Mode

[2:0]
REG. TYPE
COMMON USAGES

REG
ModR/M reg
GPR, Vector
Destination or Source

VVVV
vvvv
GPR, Vector
2^ndSource or Destination

RM
ModR/M R/M
GPR, Vector
1^stSource or Destination

BASE
ModR/M R/M
GPR
Memory addressing

INDEX
SIB.index
GPR
Memory addressing

VIDX
SIB.index
Vector
VSIB memory addressing

TABLE 3

Opmask Register Specifier Encoding

[2:0]
REG. TYPE
COMMON USAGES

REG
ModR/M Reg
k0-k7
Source

VVVV
vvvv
k0-k7
2^ndSource

RM
ModR/M R/M
k0-7
1^stSource

{k1]
aaa
k0¹-k7
Opmask

Program code may be applied to input instructions to perform the functions described herein and generate output information. The output information may be applied to one or more output devices, in known fashion. For purposes of this application, a processing system includes any system that has a processor, such as, for example, a digital signal processor (DSP), a microcontroller, an application specific integrated circuit (ASIC), or a microprocessor.

The program code may be implemented in a high-level procedural or object-oriented programming language to communicate with a processing system. The program code may also be implemented in assembly or machine language, if desired. In fact, the mechanisms described herein are not limited in scope to any particular programming language. In any case, the language may be a compiled or interpreted language.

Examples of the mechanisms disclosed herein may be implemented in hardware, software, firmware, or a combination of such implementation approaches. Examples may be implemented as computer programs or program code executing on programmable systems comprising at least one processor, a storage system (including volatile and non-volatile memory and/or storage elements), at least one input device, and at least one output device.

One or more aspects of at least one example may be implemented by representative instructions stored on a machine-readable medium which represents various logic within the processor, which when read by a machine causes the machine to fabricate logic to perform the techniques described herein. Such representations, known as “IP cores” may be stored on a tangible, machine readable medium and supplied to various customers or manufacturing facilities to load into the fabrication machines that actually make the logic or processor.

Such machine-readable storage media may include, without limitation, non-transitory, tangible arrangements of articles manufactured or formed by a machine or device, including storage media such as hard disks, any other type of disk including floppy disks, optical disks, compact disk read-only memories (CD-ROMs), compact disk rewritables (CD-RWs), and magneto-optical disks, semiconductor devices such as read-only memories (ROMs), random access memories (RAMs) such as dynamic random access memories (DRAMs), static random access memories (SRAMs), erasable programmable read-only memories (EPROMs), flash memories, electrically erasable programmable read-only memories (EEPROMs), phase change memory (PCM), magnetic or optical cards, or any other type of media suitable for storing electronic instructions.

Accordingly, examples also include non-transitory, tangible machine-readable media containing instructions or containing design data, such as Hardware Description Language (HDL), which defines structures, circuits, apparatuses, processors and/or system features described herein. Such examples may also be referred to as program products.

Emulation (Including Binary Translation, Code Morphing, Etc.)

In some cases, an instruction converter may be used to convert an instruction from a source instruction set to a target instruction set. For example, the instruction converter may translate (e.g., using static binary translation, dynamic binary translation including dynamic compilation), morph, emulate, or otherwise convert an instruction to one or more other instructions to be processed by the core. The instruction converter may be implemented in software, hardware, firmware, or a combination thereof. The instruction converter may be on processor, off processor, or part on and part off processor.

FIG. 30 illustrates a block diagram contrasting the use of a software instruction converter to convert binary instructions in a source instruction set to binary instructions in a target instruction set according to examples. In the illustrated example, the instruction converter is a software instruction converter, although alternatively the instruction converter may be implemented in software, firmware, hardware, or various combinations thereof. FIG. 30 shows a program in a high-level language 3002 may be compiled using a first ISA compiler 3004 to generate first ISA binary code 3006 that may be natively executed by a processor with at least one first instruction set core 3016. The processor with at least one first ISA instruction set core 3016 represents any processor that can perform substantially the same functions as an Intel® processor with at least one first ISA instruction set core by compatibly executing or otherwise processing (1) a substantial portion of the instruction set of the first ISA instruction set core or (2) object code versions of applications or other software targeted to run on an Intel processor with at least one first ISA instruction set core, in order to achieve substantially the same result as a processor with at least one first ISA instruction set core. The first ISA compiler 3004 represents a compiler that is operable to generate first ISA binary code 3006 (e.g., object code) that can, with or without additional linkage processing, be executed on the processor with at least one first ISA instruction set core 3016. Similarly, FIG. 30 shows the program in the high-level language 3002 may be compiled using an alternative instruction set compiler 3008 to generate alternative instruction set binary code 3010 that may be natively executed by a processor without a first ISA instruction set core 3014. The instruction converter 3012 is used to convert the first ISA binary code 3006 into code that may be natively executed by the processor without a first ISA instruction set core 3014. This converted code is not likely to be the same as the alternative instruction set binary code 3010 because an instruction converter capable of this is difficult to make; however, the converted code will accomplish the general operation and be made up of instructions from the alternative instruction set. Thus, the instruction converter 3012 represents software, firmware, hardware, or a combination thereof that, through emulation, simulation or any other process, allows a processor or other electronic device that does not have a first ISA instruction set processor or core to execute the first ISA binary code 3006.

References to “one example,” “an example,” etc., indicate that the example described may include a particular feature, structure, or characteristic, but every example may not necessarily include the particular feature, structure, or characteristic. Moreover, such phrases are not necessarily referring to the same example. Further, when a particular feature, structure, or characteristic is described in connection with an example, it is submitted that it is within the knowledge of one skilled in the art to affect such feature, structure, or characteristic in connection with other examples whether or not explicitly described.

Examples include, but are not limited to:

1. An apparatus comprising:

- decoder circuitry to decode a single instruction, the single instruction to include fields for an opcode, an identification of a source operand, and an identification of destination operand, wherein the opcode is to indicate instruction processing circuitry is to convert odd 16-bit floating point values from the identified source operand into 32-bit floating point values and store the 32-bit floating point values in data element positions of the identified destination operand; and instruction processing circuitry to execute the decoded instruction according to the opcode.
  
  2. The apparatus of example 1, wherein the field for the identifier of the first source operand is to identify a vector register.
  
  3. The apparatus of example 1, wherein the field for the identifier of the first source operand is to identify a memory location.
  
  4. The apparatus of any of examples 1-3, wherein the 16-bit floating point values are BF16 values.
  
  5. The apparatus of example 4, wherein instruction processing circuitry is to convert the BF16 values to 32-bit floating point values by appending sixteen zeros to each of the BF16 values.
  
  6. The apparatus of any of examples 1-3, wherein the 16-bit floating point values are FP16 values.
  
  7. A method comprising:
- translating a single instruction of a first instruction set into one or more instructions of a second instruction set, the single instruction to include fields for an opcode, an identification of a source operand, and an identification of destination operand, wherein the opcode is to indicate instruction processing circuitry is to convert odd 16-bit floating point values from the identified source operand into 32-bit floating point values and store the 32-bit floating point values in data element positions of the identified destination operand
- decoding a one or more instructions of the second set; and
- executing the decoded one or more instructions of the second set according to the opcode of the single instruction of the first instruction set.
  
  8. The method of example 7, wherein the field for the identifier of the first source operand is to identify a vector register.
  
  9. The method of example 7, wherein the field for the identifier of the first source operand is to identify a memory location.
  
  10. The method of any of examples 7-9, wherein the 16-bit floating point values are BF16 values.
  
  11. The method of example 10, wherein converting the BF16 values to 32-bit floating point values comprises appending sixteen zeros to each of the BF16 values.
  
  12. The method of any of examples 7-9, wherein the 16-bit floating point values are FP16 values.
  
  13. A system comprising:
- memory to store an instance of a single instruction, the single instruction to include fields for an opcode, an identification of a source operand, and an identification of destination operand, wherein the opcode is to indicate instruction processing circuitry is to convert odd 16-bit floating point values from the identified source operand into 32-bit floating point values and store the 32-bit floating point values in data element positions of the identified destination operand
- decoder circuitry to decode instance of the single instruction; and
- instruction processing circuitry to execute the decoded instance of the single instruction according to the opcode.
  
  14. The system of example 13, wherein the field for the identifier of the first source operand is to identify a vector register.
  
  15. The system of example 13, wherein the field for the identifier of the first source operand is to identify a memory location.
  
  16. The system of any of examples 13-15, wherein the 16-bit floating point values are BF16 values.
  
  17. The system of example 16, wherein instruction processing circuitry is to convert the BF16 values to 32-bit floating point values by appending sixteen zeros to each of the BF16 values.
  
  18. The system of any of examples 13-15, wherein the 16-bit floating point values are FP16 values.

Moreover, in the various examples described above, unless specifically noted otherwise, disjunctive language such as the phrase “at least one of A, B, or C” is intended to be understood to mean either A, B, or C, or any combination thereof (e.g., A, B, and/or C). As such, disjunctive language is not intended to, nor should it be understood to, imply that a given example requires at least one of A, at least one of B, or at least one of C to each be present.

The specification and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense. It will, however, be evident that various modifications and changes may be made thereunto without departing from the broader spirit and scope of the disclosure as set forth in the claims.

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