Patent Application
20140128004
In an embodiment, an apparatus includes a determiner, converter, adapter, and modifier. The determiner is configured to generate a representation of a difference between a first frequency at which a first signal is sampled and a second frequency at which a second signal is sampled, and the converter is configured to generate a second sample of the first signal at a second time in response to the representation and a first sample of the first signal at a first time. The adapter is configured to generate a sample of a modifier signal in response to the second sample of the first signal, and the modifier is configured to generate a modified sample of the second signal in response to a sample of the second signal and the sample of the modifier signal.
For example, such an apparatus may be able to reduce the magnitude of an echo signal in a device having an audio pickup (e.g., a microphone) near an audio output (e.g., a speaker); examples of such devices include a hands-free voice-communication device (e.g., a speaker phone) and a computer with an onboard microphone and speaker. The apparatus may be faster, less complex, and may include fewer components than other echo-reducing or echo-cancelling apparatuses.
a is a plot of a signal of
b is another plot of the signal of
The system 10 includes first and second voice units 12a and 12b, which allow callers 14a and 14b to communicate with one another via electrical cables 16a and 16b and a network 18, such as, e.g., a local-area network (LAN) and the internet. Alternatively, the cables 16a and 16b may be optical cables, or the cables may be omitted such that the units 12a and 12b wirelessly communicate with the network 18.
The unit 12a includes a microphone 20a for receiving the voice of the caller 14a, and includes a speaker 22a for broadcasting the voice of the other caller 14b. In detail, while the caller 14a is speaking, he/she generates an acoustic voice signal 24a, and the microphone 20a receives a portion of this acoustic voice signal and converts this portion into a corresponding electrical signal. The unit 12a processes this electrical signal, for example, as described below in conjunction with
Likewise, the unit 12b includes a microphone 20b for receiving the voice of the caller 14b, and includes a speaker 22b for broadcasting the voice of the other caller 14a. In detail, while the caller 14b is speaking, he/she generates an acoustic voice signal 24b, and the microphone 20b receives a portion of this acoustic voice signal and converts this portion into a corresponding electrical signal. The unit 12b processes this electrical signal, for example, as described below in conjunction with
Unfortunately, a potential problem with the system 10 is that it may generate an “echo” on either end of the call, and such an echo may reduce the quality of the acoustic voice signal 26 broadcast by either of the speakers 22, even to the point where the words spoken by one caller 14 are unintelligible to the other caller. Furthermore, even if the words spoken by one caller 14 are intelligible to the other caller, the reduced quality of the perceived voice signal may frustrate and fatigue the other caller.
Still referring to
Fortunately, the voice units 12a and 12b include echo-cancellation circuitry to reduce or eliminate such an echo, and, therefore, to improve the quality of the acoustic voice signals 26 emanating from the speakers 22. Embodiments of echo-cancellation circuits and techniques are described below in conjunction with
Still referring to
When describing the circuit 30 of the voice unit 12a, one may refer to the unit 12a as the “near-end” unit, and he/she may refer to the unit 12b as the “far end” unit; conversely, when describing the circuit of the voice unit 12b, one may refer to the unit 12b as the “near-end” unit, and he/she may refer to the unit 12a as the “far end” unit.
Still referring to
Similarly, the near-end unit 12a transmits to the far-end unit 12b an echo-cancelled digital signal ea(k′), which is formed by a stream of samples that occur at a sample rate fy, and in which “k′” is the sample index. Ideally, the signal ea(k) represents a modification of the acoustic signal received by the microphone 20a, where this modified acoustic signal lacks any echo component da(t) of the acoustic speaker signal 26a from the speaker 22a. Ideally, by removing from ea(k) all of the echo component da(t) of the acoustic speaker signal 26a, the echo “loop” described above in conjunction with
Still referring to
The D/A converter 32 converts the digital electronic signal xa(k) into an analog speaker-drive signal xa(t) at approximately the frequency fx, which is the frequency at which the samples occur in the signal xa(k). The circuit 30 may derive the clock signal CLOCK_fx for the D/A converter 32 from the signal xa(k) in a conventional manner so that the frequency of CLOCK_fx accurately tracks the sample frequency fx.
The A/D converter 32 converts the analog electronic signal ya(t) from the microphone 20a into a digital electronic signal ya(k′) at the sample frequency fy in response to a clock signal CLOCK_fy. As discussed above, while the speaker 22a is generating the acoustic speaker signal 26a, the signal ya(k′) typically does include an echo component da(k′) that corresponds to the echo component da(t) of the acoustic speaker signal 26a as discussed below.
The buffer 36 buffers the samples of the signal ya(k′), and provides these buffered samples to the combiner 40 at the sample frequency fy.
The echo adapter 38 generates from the digital electronic signal xa(k) a digital echo-cancellation signal (more generally a modifier signal) {circumflex over (d)}a(k), which is an estimate of the echo component da(k′) of ya(k′), where da(k′) results from the echo component da(t) of the acoustic speaker signal 26a; that is da(k′) is the result of da(t) effectively propagating through the microphone 20a, the A/D converter 34, and the buffer 36. For example, the adapter 38 may be a conventional finite-impulse-response (FIR) filter with tap weights wa(k). Because embodiments of the adapter 38 are known, the details of the adapter are not described in detail.
And the combiner 40 generates the echo-cancelled signal (more generally the modified signal) ea(k′) in response to the signals ya(k′) and {circumflex over (d)}a(k). For example, as shown in
Still referring to
The echo adapter 38 converts samples of the digital signal xa(k) from the far-end voice unit 12b (
The D/A converter 32 converts the samples of the digital signal xa(k) into the analog speaker-drive signal xa(t) at the sample frequency fx.
The speaker 22a converts the analog signal xa(t) into the acoustic speaker signal 26a.
The microphone 20a picks up the analog echo component da(t) from the acoustic speaker signal 26a (that is, the portion of the acoustic speaker signal 26a that the microphone 20a picks up is the analog echo component da(t)), a voice component sa(t) from the acoustic voice signal 24a generated by the caller 14a (
The A/D converter 34 converts the analog microphone signal ya(t) into the digital microphone signal ya(k′) at the sampling frequency fy, and the buffer 36 buffers the samples of ya(k′).
The combiner 40 combines the digital microphone signal ya(k′) with the digital echo-estimation component {circumflex over (d)}a(k) to generate the echo-cancelled signal ea(k′). As discussed above, if the magnitudes of the samples of {circumflex over (d)}a(k) equal the magnitudes of the components da(k′) of the corresponding samples of ya(k′), then the echo component da(k′) is completely removed from the signal ea(k′) such that the caller 14b (
And the voice unit 12a provides the echo-cancelled signal ea(k′) to the far-end unit 12a via the cables 16a and 16b and the network 18 (
But if the samples k′ do not occur at the same frequency as the samples k (i.e., if fx≠fy), then the samples of {circumflex over (d)}a(k) may not be temporally aligned with the echo components da(k′); therefore, the level of echo cancellation (and noise cancellation if applicable) provided by {circumflex over (d)}a(k) when fx≠fy may be reduced as compared to the level of echo cancellation when fx=fy.
Although the D/A converter 32 and the ND converter 34 may be disposed on the same integrated circuit, and their clocks CLOCK_fx and CLOCK_fy may be generated from the same master clock, it has been found that the frequencies fx and fy of these clocks may be slightly different due to, e.g., clock skew and parasitic capacitances and inductances. For example, a sample-frequency ratio r is given by the following equation:
r=f
x
/f
y (1)
Ideally, r would equal one, but in actuality, it has been found that r may vary approximately between, e.g., 0.9999 and 1.0001, in some applications.
From equation (1) one may derive the following equation:
rT
x
=T
y (2)
where Tx=1/fx and Ty=1/fy.
From equation (2), one may derive the following equations:
x
a(k)=xac(t=kTx) (3)
y
a(k′)=ya(t=k′Ty) (4)
x
a(k′)=xac(t=rkTx)=xac(t=(fx/fy)kTx)=xac(t=(Ty/Tx)kTx)=xac(t=kTy)=xa(rk) (5)
where xac is an actual, or theoretical, analog signal that is sampled at the frequency fx to generate the digital signal xa(k). Equation (5) indicates that one may temporally align the samples of ya(k′) and samples of xac(t), and thus align the samples of ya(k′) and {circumflex over (d)}a, if he/she generates samples k′ of xac(t) according to the following equation:
x
a(k′)=xac(rkTx)=xa(rk) (6)
And if r=1, then equation (6) reduces to:
x
a(k′)=xa(k) (7)
as expected.
But because the signal xac(t) may be unavailable at the voice unit 12a (e.g., because xa(k) is effectively generated from xac(t) by the voice unit 12b), another way to generate xa(k′) is to interpolate xa(k′) from xa(k) by interpolating samples k′ at sample times tk′ from the samples k at sample times tk.
A technique for interpolating xa(k′) from xa(k) per equations (6) and (7) is to use circuitry that implements a Least-Mean-Square (LMS) approach to estimate the ratio r, and to up sample xa(k), to convert the up-sampled xa(k) into {circumflex over (x)}ac(t), which is an estimate of xac(t), and to sample {circumflex over (x)}ac(t) at sample times rkTx to generate xa(k′).
But such circuitry is often relatively complex, includes a relatively large number of components, occupies a relatively large area, and consumes a relatively large amount of power.
The circuit 50 is similar to the circuit 30 of
The detector 52 receives the signals xa(k) and ya(k′), detects whether the acoustic speaker signal 26a from the speaker 22a is present (i.e., nonzero) and whether the acoustic voice signal 24a from the caller 14a (
The sample-rate converter 54, which is further described below in conjunction with
And the sample-frequency-ratio estimator 56, which is further described below in conjunction with
In operation, the detector 52 determines whether the acoustic signals 24a and 26a are present, and provides this information to the sample-frequency-ratio estimator 56 via the signal CALLER_ACTIVITY_LEVEL.
The sample-rate converter 54 converts the samples of xa(k) into respective samples of xa(k′) in response to the value for r provided by the sample-frequency-ratio estimator 56, and the echo adapter 38 generates the estimated echo signal {circumflex over (d)}a(k′) (which also may include an estimate of the noise per above) in response to xa(k′), such that samples of {circumflex over (d)}a(k′), ya(k′), and ea(k′) are approximately temporally aligned.
The sample-frequency-ratio estimator 56 updates r every cycle of CLOCK_fx if the detector 52 indicates that the acoustic speaker signal 26a is present and that the acoustic voice signal 24a (
Still referring to
Referring to
At step 64, the estimator 56 determines, in response to the signal CALLER_ACTIVITY_LEVEL received from the detector 52, whether there is any far-end activity, i.e., whether the far-end caller 14b (
At step 66, the estimator 56 (
P=e
a(k′)·(ya(k′+1)−ya(k′−1)) (8)
where the sign (“+” or “−”) of P indicates whether the frequency ratio r=fx/fy is too high or too low.
Referring to
a is a plot of the signal ya(t), and of the samples ya(k′+1), ya(k′−1), and ya(k′) of ya(t), and a sample of {circumflex over (d)}a(k′), of
Because the estimator 56 updates r only if there is far-end activity but no near-end activity, and assuming that the noise component na(t) received by the microphone 20a (
y
a(t)≈da(t) (9)
Therefore, assuming that the echo adapter 58 accurately estimates the estimated echo component {circumflex over (d)}a(k′) of ya(k′), and if the value of r is accurate, then the following expressions are also true:
{circumflex over (d)}
a(k′)≈ya(k′), and (10)
e
a(k′)≈0 (11)
But if {circumflex over (d)}a(k′)>ya(k′) as shown in
b is a plot of the signal ya(t), of the samples ya(k′+1), ya(k′−1), and ya(k′) of ya(t), and a sample of {circumflex over (d)}a(k′), of
Because, in this example, {circumflex over (d)}a(k′)<ya(k′), this means that {circumflex over (d)}a(k′) leads ya(k′), and, therefore, that the value of r is too large. So in this condition, ea(k′) has a positive value, but the difference ya(k′+1)−ya(k′−1) has a negative value, such that P is negative. Furthermore, one can show that whenever {circumflex over (d)}a(k′) leads ya(k′), P is negative. Therefore, a negative value for P indicates that value of r is too large and needs to be decreased.
Referring again to
At step 70, the estimator 56 increases r in response to P being positive. For example, the estimator 56 may increase r by incrementing r by an arbitrary constant δ, which, in an embodiment, has an initial value of 1×10−8, according to the following equation:
r(k+1)=r(k)+δ (12)
After increasing r, the estimator 56 proceeds to step 78.
At step 72, because P is not positive, the estimator 56 determines whether P is less than zero, i.e., whether P is negative. If P is negative, then the estimator 56 proceeds to step 74 to decrease r. But if P is not negative (i.e., P=0), then the estimator proceeds to step 76.
At step 74, the estimator 56 decreases r. For example, the estimator 56 may decrease r by decrementing r by δ according to the following equation:
r(k+1)=r(k)−δ (13)
After decreasing r, the estimator 56 proceeds to step 78.
At step 76, because P is neither positive or negative, i.e., P=0, the estimator 56 maintains rat its present value according to the following equation:
r(k+1)=r(k) (14)
Next, at step 78, the estimator 56 determines whether the current value of r, r(k+1), is greater than or equal to a maximum value max_r, which may be any value that is suitable for the application. For example, max_r may approximately equal 1.0001. If r(k+1) is greater than or equal to max_r, then the estimator 56 proceeds to step 80 to limit r. But if r(k+1) is not greater than or equal to max_r, then the estimator 56 proceeds to step 82.
At step 80, the estimator 56 sets r(k+1)=max_r, and then proceeds to step 86. That is, the estimator 56 limits the current value of r to be no higher than max_r.
At step 82, the estimator 56 determines whether r(k+1) is less than or equal to a minimum value min_r, which may be any value that is suitable for the application. For example, min_r may approximately equal 0.9999. If r(k+1) is less than or equal to min_r, then the estimator 56 proceeds to step 84 to limit r. But if r(k+1) is not less than or equal to min_r, then the estimator 56 proceeds to step 86.
At step 84, the estimator 56 sets r(k+1)=min_r, and then proceeds to step 86. That is, the estimator 56 limits the current value of r to be no lower than min_r.
Next, at steps 86 and 88, the estimator 56 determines if it is time to update δ, and if so, determines if δ is to be updated. For example, the estimator 56 may reduce the constant δ every U samples k as long as δ is greater than a minimum value min_δ. U and δ may have any values, such as approximately 50,000 and 1×10−10, respectively, that are suitable for the application. Periodically reducing δ may allow the estimator 56 to converge to a relatively precise value of r.
More specifically, at step 86, the estimator 56 determines whether it is time to update δ. The estimator 56 may do this by determining that it is time to update δ if Mod(k,U)=0. Therefore, if Mod(k,U)=0, then the estimator 56 proceeds to step 88. But if Mod(k,U)≠0, then the estimator returns to step 62 without modifying δ.
At step 88, the estimator 56 determines whether δ>min_δ. If δ>min_δ, then the estimator 56 proceeds to step 90. But if δ≦min_δ, then the estimator 56 returns to step 62 without modifying δ.
At step 90, the estimator 56 updates δ. For example, the estimator may decreases 5, and may do so by setting δ=δ/10.
Then, at step 92, the estimator 56 (
Therefore, in summary, the estimator 56 updates r only when there is far-end activity and no near-end activity, and does so in a way that causes r to converge to an accurate value over a number of samples k. Furthermore, the embodiment of the r-updating algorithm represented by the flow diagram 60 may be suited for a voice unit 12 where the sample frequencies fx and fy are relatively stable, or vary relatively slowly over time.
Still referring to
The sample-rate converter 54 includes an input node 100 for receiving samples of the signal xa(k), an output node 102 for providing samples of the signal xa(k′), two conversion paths 104a and 104b, and a switch 106 for coupling a selected one of the paths to the output node in response to a control signal PATH_SELECT. The output node 102 is coupled to an input node of the echo adapter 38 of
The conversion path 104a includes a programmable delay circuit 108a and a filter, such as a fractional-delay IIR filter, 110a for interpolating samples of xa(k) from corresponding samples of xa(k). The filter 110a may be clocked by the signal CLOCK_fx. An embodiment of the filter 110a is further described below in conjunction with
Similarly, the conversion path 104b includes a programmable delay circuit 108b and a filter, such as a fractional-delay IIR filter, 110b for interpolating samples of xa(k′) from corresponding samples of xa(k). The filter 110b may be clocked by the signal CLOCK_fx. An embodiment of the filter 110b is further described below in conjunction with
In operation, during first periods that each may be, for example, 500 samples k long, the control signal PATH_SELECT has a value, e.g., a logic 0, that causes the switch 106 to couple the conversion path 104a to the output node 102.
Therefore, during these first periods, the conversion path 104a generates samples of xa(k′) while the sample-rate converter 54 updates one or more parameters of the conversion path 104b. Such parameters, and the updating thereof, are further described below in conjunction with
Similarly, during second periods that each may be, for example, 500 samples k long, and that alternate with the first periods, the control signal PATH_SELECT has a value, e.g., a logic 1, that causes the switch 106 to couple the conversion path 104b to the output node 102.
Therefore, during these second periods, the conversion path 104b generates samples of xa(k′) while the sample-rate converter 54 updates one or more parameters of the conversion path 104a. Such parameters, and the updating thereof, are further described below in conjunction with
Consequently, by including two conversion paths 104a and 104b, the sample-rate converter 54 can update one of the paths while the other path is generating samples of xa(k′) such that the periodic updating of the paths introduces little or no delay to the generating of xa(k′).
Still referring to
The filter 110a includes an input node 120 for receiving delayed samples of xa(k) from the delay circuit 108a, an output node 122 for providing samples of xa(k), summers 1241-124n, one-sample delay circuits 1262-126n, first multipliers 1282-128n having respective first constant multiplying coefficients −a2-−an, and second multipliers 1301-130n having respective second constant multiplying coefficients b1-bn; n can be any value that is suitable for the interpolation accuracy specified for a particular application.
In operation, the sample-converter 54 (
Each summer 1242-124n receives on a first input node 1322-132n a respective value −a2·xa(k′)−−an·xa(k′), receives on a second input node 1342-134n a respective value b2·xa(k)−bn·xa(k), receives (except for the summer 124n) on a third input node 1362-136n-1 the output of a respective delay circuit 1263-126n, and adds these received values together to generate the respective summer output Z2(k)-Zn(k).
And the summer 1241 receives on a first input node 1341 a value b1·xa(k), receives on a second input node 1361 the output of the delay circuit 1262, and adds these received values together to generate samples of xa(k′).
Still referring to
Referring to
THIS_INSTANT=r(k)·(k−1) (15)
For example, if r(k)=1.000001 and k=678, then THIS_INSTANT would equal 677.000677. Therefore, the filters 110a and 110b use THIS_INSTANT to effectively translate the samples k of xa(k) taken at sample times tk into samples k′ of xa(k′) taken at sample times tk′.
Then, at step 154, the converter 54 determines whether it is time to update either of the filters 110a and 110b. For example, the converter 54 may make this determination by solving the following expressions:
Mod(k,K1) (16)
Mod(k,K2) (17)
where it is time to update the filter 110a if Mod(k, K1)=0 and Mod(k, K2)≠0, and where it is time to update the filter 110b if Mod(k, K1)=Mod(k, K2)=0. For example, if K1=500 and K2=1000, then the converter 54 updates the filter 110a, and activates the filter 110b to generate the samples of xa(k′) via the switch 106 (
Still referring to step 154, if the converter 54 determines that t is time to update one of the filters 110a and 110b, then the converter proceeds to step 156; otherwise, the converter 54 returns to step 152.
At step 156, the converter 54 determines a DELAY between the previously determined current time instant THIS_INSTANT and the previous sample time k−1, for example, according to the following equation:
DELAY=(k−1)−THIS_INSTANT 18)
Next, at step 158, the converter 54 determines a fractional portion FRACTIONAL_DELAY of the DELAY, for example, according to the following equation:
FRACTIONAL_DELAY=DELAY−floor(DELAY) (19)
where the operator floor(arg) rounds its argument (here DELAY) to the greatest integer that is less than the argument. For example, floor(2.3)=2, and floor(−2.3)=3.
Then, at step 160, the converter 54 determines an integer portion INTEGER_DELAY of the DELAY, for example, according to the following equation:
INTEGER_DELAY=DELAY−FRACTIONAL_DELAY (20)
Next, at step 162, the converter 54 determines whether it is time to update the filter 110a or the filter 110b per expressions (16) and (17) as described above. If it is time to update the filter 110a, then the converter 54 proceeds to steps 164 and 166; but if it is time to update the filter 110b, then the converter proceeds to steps 168 and 170.
At step 164, the converter 54, generates a value (e.g., logic 1) of PATH_SELECT (
Next, at step 166, the converter 54 updates the delay of the delay block 108a, and updates the coefficients and sets the initial conditions of the filter 110a.
For example, the converter 54 may update the delay BLOCK_DELAY of the block 108a according to the following equation:
BLOCK_DELAY=INTEGER_DELAY−2 (21)
That is, in terms of a z transform, BLOCK_DELAY=z−|INTEGER
To determine the coefficients −a2, −a3, . . . , −an={right arrow over (a)} and b1, b2, b3, . . . , bn={right arrow over (b)}, the converter 54 may first determine a value C according to the following equation:
C=floor((2+FRACTIONAL_DELAY)·100) (22)
Then, the converter 54 may determine the coefficients {right arrow over (a)} and {right arrow over (b)} according to the following equation:
[{right arrow over (a)},{right arrow over (b)}]=compute_bspline(C,M,p) (23)
where the operator compute_bspline(arg) is described in, e.g., Table I, equation (18), and the Appendix of Olkkonen et al., “Fractional Delay Filter Based on the B-Spline Transform,” IEEE Signal Processing Letters, Vol. 14, No. 2, February 2007, pp. 97-100, which was previously incorporated by reference, and M and p may be any suitable values such as 100 and 4, respectively (note that p is distinguished from the product P, which is described above in conjunction with
Next, the converter 54 may determine the initial values for the outputs z2(k), z3(k), . . . , zn(k)={right arrow over (z)} of the summers 1242-124n according to the following equation:
{right arrow over (z)}=zeros(1,(length({right arrow over (a)})−1)) (24)
where the operator length(arg) returns the length of its vector argument (here the vector {right arrow over (a)} having a length of n−1), and the operator zeros(arg) returns a matrix of all zeros having the dimensions of its argument (here a 1×length(arg)−1 row vector).
Still referring to step 166, the converter 54 may store the determined values for {right arrow over (a)} and {right arrow over (b)} for the filter 110a in a memory on board, or external to, the converter. Furthermore, the converter 54 may effectively store the determined value for BLOCK-DELAY in the configuration of the delay block 108a of
Conversely, if, at step 162, the converter 54 determines that it is time to update the filter 110b, then, at step 168, the converter 54 generates a value (e.g., logic 0) of PATH_SELECT (
Then, at step 170, the converter 54 updates the delay of the delay block 108b, and updates the coefficients and sets the initial conditions of the filter 110b.
For example, the converter 54 may update the delay BLOCK_DELAY of the block 108b according to equation (21) above.
To determine the coefficients −a2, −a3, . . . , −an={right arrow over (a)} and b1, b2, b3, . . . . , bn={right arrow over (b)} of the filter 110b, the converter 54 may first determine the value C according equation (22) above.
Then, the converter 54 may determine the coefficients d and b for the filter 110b according to equation (23) above.
Next, the converter 54 may determine the initial values for the outputs z2(k), z3(k), . . . , zn(k)={right arrow over (z)} of the summers 1242-124n of the filter 110b according to equation (24) above.
Still referring to step 170, the converter 54 may store the determined values of {right arrow over (a)} and {right arrow over (b)}, for the filter 110b in a memory on board, or external to, the converter, Furthermore, the converter 54 may effectively store the determined value for BLOCK-DELAY in the configuration of the delay block 108b of
Then, at step 172, the converter 54 determines whether there are any more samples k of xa(k) to process. If the converter 54 determines that there are more samples k of xa(k) to process, then the converter returns to step 152. But if the converter 54 determines that there are no more samples k of xa(k) to process, then the converter may halt the operation and updating of the filters 110a and 110b.
Still referring to FIGS. 3 and 6-8, alternate embodiments of the converter 54 are contemplated. For example, one or more components of the converter 54, such as the conversion paths 104a and 104b, may be implemented in software, hardware, firmware, or a combination of two or more of software, hardware, and firmware. When a component is implemented in software, the function of the component may be performed by a computing apparatus such as a microprocessor or microcontroller executing instructions.
The circuit 180 is similar to the circuit 50 of
The algorithm of
P=e
a(k′)·({circumflex over (d)}a(k′+1)−{circumflex over (d)}a(k′−1)) (25)
instead of equation (8), and in step 92, the estimator determines whether there are more samples of {circumflex over (d)}a(k′), not ya(k′), to process. P in equation (25) indicates whether r is too high or too low for reasons similar to those discussed above in conjunction with
From the foregoing it will be appreciated that, although specific embodiments have been described herein for purposes of illustration, various modifications may be made without deviating from the spirit and scope of the disclosure. Furthermore, where an alternative is disclosed for a particular embodiment, this alternative may also apply to other embodiments even if not specifically stated. Moreover, the components described above may be disposed on a single or multiple IC dies to form one or more ICs, these one or more ICs may be coupled to one or more other ICs. In addition, any described component or operation may be implemented/performed in hardware, software, or a combination of hardware and software. Furthermore, one or more components of a described apparatus or system may have been omitted from the description for clarity or another reason. Moreover, one or more components of a described apparatus or system that have been included in the description may be omitted from the apparatus or system.
