BRIEF DESCRIPTION OF THE DRAWINGS
FIGS. 1-4 are schematic drawings illustrating a conventional via-first copper damascene process.
FIGS. 5-8 are schematic drawings illustrating a first preferred embodiment provided by the invention.
FIG. 9 is a drawing illustrating normalized results of a voltage ramp dielectric breakdown (VRDB) test for conventional damascene structure and that provided by the present invention.
FIG. 10 is a drawing illustrating normalized results of a VRDB test for copper damascene structures provided by the present invention with different procedure parameters.
FIG. 11 is a schematic drawing illustrating a second and a third preferred embodiment.
FIG. 12 is a flowchart according to the copper damascene process provided by the invention.
DETAILED DESCRIPTION
Please refer to FIGS. 5-8, which are schematic drawings illustrating a first preferred embodiment provided by the invention. As shown in FIG. 5, a substrate 200 having a plurality of function devices thereon is provided first (not shown). Then, a cap layer 210, a stacked dielectric layer 220, and a stop layer 228 composed of silicon nitride are sequentially formed on the substrate 200. The stacked dielectric layer 220 comprises a first dielectric layer 222, an etching stop layer 224, and a second dielectric layer 226. The first and second dielectric layers 222 and 226 comprise low dielectric constant (low-k) materials with its dielectric constant lower than 3.5; those dielectric layer also comprises carbon-doped oxide (CDO) or porogen, but are not limited to this. The stacked dielectric layer 220 is formed on the substrate 200 by plasma enhanced chemical vapor disposition (PECVD) method or spin-on coating (SOC) method. Then, at least a via hole 232 and a trench 234 are formed in the cap layer 210, the stacked dielectric layer 220, and the stop layer 228 by a trench-first, via-first, or partial-via-first dual damascene process. Next, a diffusion barrier layer 250 is formed on bottom and sidewalls of the via hole 232 and the trench 234. After forming the diffusion barrier layer 250, a copper metal layer filling the via hole 232 and the trench 234 is formed on the substrate 200 by seed layer and electroplating process.
Please refer to FIG. 6. A CMP process is performed to remove surplus copper and the diffusion barrier layer 250 to form a copper damascene structure 230 and another CMP process is performed to remove the stop layer 228 to make the copper damascene structure 230 coplanar with the stacked dielectric layer 220. Additionally, the stop layer 228 can be kept on the stacked dielectric layer 220 instead of being removed. Please refer to FIG. 6 again. Because the organic materials added in the CMP process for protecting the pattern of the copper damascene structure 230 are not easily removed and often remains on the surface of the substrate 200, a heat treatment is performed to remove those impurities 272 left after the CMP process.
The heat treatment provided in the first preferred embodiment can be performed in a furnace, a rapid thermal processing (RTP) chamber, a hot-plate, a PECVD chamber, or a sub-atmospheric chemical vapor deposition (SACVD) chamber. The heat treatment is performed at a temperature in a range of 200-600° C., preferably about 250-450° C.; and it is performed in a duration of 1-600 seconds, preferably about 10-20 seconds. In addition, the heat treatment is performed under an operational pressure in a range of 1.0-760 Torr. The operational pressure is provided by an oxidant gas, a nitrogen, or an insert gas with a flow rate from 100 to about 10,000 standard cubic centimeters per minute (sccm). Furthermore, to completely remove the impurities 272, the heat treatment is performed in cycles, depending on amounts of the impurities 272 and demands for the wafer.
Please refer to FIG. 7. After removing the impurities 272, a reduction plasma treatment with ammonia-containing or hydrogen-containing plasma is performed to reduce the copper oxide 270 formed in the CMP process. Additionally, the heat treatment and the reduction plasma treatment are performed in-situ or ex-situ.
Please refer to FIG. 8. Then a SiN or SiC layer 260 is formed on surfaces of the copper damascene structure 230 and the stacked dielectric layer 220. The SiN or SiC layer 260 not only the protects the copper damascene structure 230 and the stacked dielectric layer 220, but also prevent the copper atom from diffusing along the interface between the copper damascene structure 230 and the surrounding dielectric material.
Please refer to FIG. 9, which is a drawing illustrating normalized results of a voltage ramp dielectric breakdown (VRDB) test for conventional damascene structures and that provided by the present invention. As shown in FIG. 9. No. 1-4 wafers have copper damascene structures provided by conventional processes, and the VRDB results of No. 1-4 wafers are normalized as 100%; No. 5-6 wafers have copper damascene structures provided by the copper damascene process according to the present invention. The heat treatment provided in this preferred embodiment is performed about 5 seconds. As shown in FIG. 9, the VRDB results of No. 5-6 wafers indicate that the breakdown voltage of the copper damascene structure provided by the copper damascene process of the present invention is substantially improved about 140%.
Please refer to FIG. 10, which is a drawing illustrating normalized results of a VRDB test for copper damascene structures provided by the present invention with different procedure parameters. As shown in FIG. 10, No. 1-3 wafers have the copper damascene processes with the heat treatment for 5 seconds, No. 4-6 wafers have the copper damascene processes with the heat treatment for 15 seconds, and No. 7-9 wafers No. 4-6 wafers have the copper damascene processes with the heat treatment for 25 seconds. According to FIG. 10, the VRDB results of No. 1-3 wafers are normalized as 100% while the VRDB results of No. 4-9 wafers achieve 150%, even 200%. To sum up, the VRDB results indicate that copper damascene structures can be effectively improved under heat treatment for at least 15 seconds.
As mentioned above, electrical problems such as reduced breakdown voltage of dielectric layer caused by diffusion of copper atoms, and malfunction of copper damascene structure caused by unreduced copper oxide due to remaining impurities in the conventional copper damascene process are avoided by the present invention and the reliability of the copper damascene structures are effectively improved.
The present invention herein provides a second preferred embodiment. Please refer to FIG. 11, which is a schematic drawing illustrating the second preferred embodiment. Because the steps before CMP process and after the reduction plasma treatment are similar to the steps in the first preferred embodiment, those steps are omitted in the second preferred embodiment. As shown in FIG. 11, to remove the impurities left after the CMP process, the second preferred embodiment herein provides an oxidation plasma treatment after the CMP process. The oxidation plasma treatment comprises an oxidant-containing plasma which can remove the organic materials added for protecting the pattern of the dual damascene structure 230. The oxidation plasma treatment and the reduction plasma treatment can be performed in the same chamber, or in different chambers.
A third preferred embodiment is provided by the present invention herein. Because the steps before CMP and after the reduction plasma treatment are similar to steps in the first preferred embodiment, those steps are omitted in the third preferred embodiment. Please refer to FIG. 11 again. To remove the impurities left after the CMP process, the third preferred embodiment provides a UV treatment after the CMP process. The UV treatment and the reduction plasma treatment are performed in-situ or ex-situ.
Please refer to FIG. 12, which is a flowchart according to the copper damascene process provided by the invention. The steps are summarized below:
Step 300: providing a substrate having a plurality of function devices within;
Step 310: forming a cap layer, a stacked dielectric layer, and a stop layer sequentially on the substrate. The stacked dielectric layer comprises a first dielectric layer, an etching stop layer, and a second dielectric layer;
Step 320: forming at least a via hole and a trench in the cap layer, the stacked layer, and the stop layer by PEP processes;
Step 330: forming a diffusion barrier layer on bottom and sidewalls of the via hole and the trench and forming a copper layer filling the via hole and the trench;
Step 340: performing a CMP process to remove surplus copper to form a copper damascene structure;
Step 350: performing a heat treatment to remove impurities remaining after CMP process;
Step 352: performing an oxidation plasma treatment to remove impurities remaining after CMP process;
Step 354: performing a UV treatment to remove impurities remaining after CMP process;
Step 360: performing a reduction plasma treatment to reduce copper oxide formed in CMP process.
In the flowchart described above, step 350, step 352, and step 354 are alternative steps.
The object of present invention is achieved by alternatively performing a heat treatment, an oxidation plasma treatment, or a UV treatment which remove residuals generated in the copper damascene process after forming copper damascene structure. Therefore the reduction plasma treatment performed later can reduce copper oxide completely and improve the reliability of the copper damascene structure.
Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.
Patent Application
20080026579
