Patent Application
20230395675
The present disclosure relates to semiconductor structures and, more particularly, to a cross couple design for high density standard cells and methods of manufacture.
As technology scales, the importance of logic scaling also grows. However, traditional approaches to scaling of standard cells (e.g., the building blocks of logic design) are not effective due to lithographic limitations. Cross-coupling techniques have been implemented to mitigate the effects of such lithographic limitations to provide continued scaling of standard cells. For example, a cross couple may be implemented by inserting a dummy polysilicon gate, which causes an area bloat, or by using a sub-ground rule special construct in a middle of the line (MOL). However, complex layout designs such as the cross couple are also becoming increasingly difficult to enable as technology scales.
In an aspect of the disclosure, a structure comprises: a first contact connected in a cross couple circuit to at least two gate structures; and a second contact connected to the first contact at a location which is devoid of any via connections.
In an aspect of the disclosure, a structure comprises: a first gate line; a second gate line separated from and diagonally positioned from the first gate line; a contact that connects to both the first gate line and the second gate line, on a first wiring layer; and a wiring structure connecting to the contact and active regions of the first gate line and the second gate line.
In an aspect of the disclosure, a method comprises: forming a first contact connected in a cross couple circuit to at least two gate structures; and forming a second contact to the first contact at a location which is devoid of any via connections.
The present disclosure is described in the detailed description which follows, in reference to the noted plurality of drawings by way of non-limiting examples of exemplary embodiments of the present disclosure.
The present disclosure relates to semiconductor structures and, more particularly, to a cross couple design for high density standard cells and methods of manufacture. In embodiments, two adjacent gates may be cut into segments, with a diagonal contact connected to two segments, and a horizontal co-planar contact connected to the diagonal gate contact on a same level as the diagonal contact. Advantageously, logic area scaling is improved, and no additional mask adders are required in comparison to known circuit layouts.
In contrast to known circuits, the present disclosure includes an additional diagonal contact added to directly connect polysilicon gate segments on a single mask layer. Further, an additional horizontal contact may be used for a middle of line (MOL) connection to the diagonal contact in a standard cell. Thus, in contrast to known circuits, the present disclosure improves logic area scaling, does not require any additional mask adders, and improves MOL congestion.
In more specific embodiments of the present disclosure, a structure includes: a first gate contact connected to at least two gate segments in a cross couple circuit, and a second MOL contact connected to the first gate contact at a contact point of the cross couple circuit. In further aspects, a logic gate circuit includes: a first set of polysilicon gate lines connected through a base metal layer; a second set of polysilicon gate lines connected to the first set of polysilicon gate lines through a first metal line; a second metal line connected to the first metal line through a plurality of metal layers higher than the base metal layer; and the second metal line co-planar with the first metal line.
The cross couple design for high density standard cells of the present disclosure may be manufactured in a number of ways using a number of different tools. In general, though, the methodologies and tools are used to form structures with dimensions in the micrometer and nanometer scale. The methodologies, i.e., technologies, employed to manufacture the cross couple design for high density standard cells of the present disclosure have been adopted from integrated circuit (IC) technology. For example, the structures are built on wafers and are realized in films of material patterned by photolithographic processes on the top of a wafer. In particular, the fabrication of the photonic chip security structure uses three basic building blocks: (i) deposition of thin films of material on a substrate, (ii) applying a patterned mask on top of the films by photolithographic imaging, and (iii) etching the films selectively to the mask.
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A standard gate contact 20 contacts each of the FETs 80, 90. A diagonal gate contact 40 connects the FETs 70, 100. The diagonal contact 40 spans across or over the gate cut 30. The standard gate contact 20, the gate cut 30, and the diagonal contact 40 are within shallow trench isolation (STI) regions. The diagonal gate contact 40 allows a connection between the FETs 70, 100, without requiring insertion of a dummy gate structure (which also saves area). A metal layer 25 (on a first metal layer, M1), extends over the diagonal gate contact 40 and connects to the active regions 50. A gate structure (i.e., transistor) 55 may be provided on sides of the FETs 70, 80, 90, 100.
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It should be understood by those of skill in the art, though, that the FETs 70, 80, 100 may be polysilicon gate structures (i.e., a polysilicon gate line) or metal gate structures using conventional workfunction metals, e.g., tungsten, etc. Also, in embodiments, the FETs 70, 80, 90, 100 may be fabricated using known first gate processes or replacement gate processes such that no further explanation is required herein for a complete understanding of the present disclosure. For example, the FETs 70, 90, 100 may be finFETs manufactured using conventional sidewall image transfer (SIT) or self-aligned couple patterning (SADP) processes. In embodiments, the diagonal gate contact 40 may have a same material or different material as the FETs 70, 80, 90, 100.
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The cross couple design for high density standard cells may be utilized in system on chip (SoC) technology. The SoC is an integrated circuit (also known as a “chip”) that integrates all components of an electronic system on a single chip or substrate. As the components are integrated on a single substrate, SoCs consume much less power and take up much less area than multi-chip designs with equivalent functionality. Because of this, SoCs are becoming the dominant force in the mobile computing (such as in Smartphones) and edge computing markets. SoC is also used in embedded systems and the Internet of Things.
The method(s) as described above is used in the fabrication of integrated circuit chips. The resulting integrated circuit chips may be distributed by the fabricator in raw wafer form (that is, as a single wafer that has multiple unpackaged chips), as a bare die, or in a packaged form. In the latter case the chip is mounted in a single chip package (such as a plastic carrier, with leads that are affixed to a motherboard or other higher level carrier) or in a multichip package (such as a ceramic carrier that has either surface interconnections and buried interconnections or both surface interconnections and buried interconnections). In any case the chip is then integrated with other chips, discrete circuit elements, and/or other signal processing devices as part of either (a) an intermediate product, such as a motherboard, or (b) an end product. The end product may be any product that includes integrated circuit chips, ranging from toys and other low-end applications to advanced computer products having a display, a keyboard or other input device, and a central processor.
The descriptions of the various embodiments of the present disclosure have been presented for purposes of illustration, but are not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein was chosen to best explain the principles of the embodiments, the practical application or technical improvement over technologies found in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.
