The present disclosure relates to a three-dimensional circuit pattern inspection and measurement technique by cross sectioning of integrated circuits. More particularly, the present disclosure relates to a method of obtaining a 3D volume image of an integrated semiconductor sample and to a corresponding computer program product and a corresponding semiconductor inspection device. The method, computer program product and device can be utilized for quantitative metrology, defect detection, defect review, and inspection of an edge shape of the pattern and to derive a line edge roughness or surface roughness of a fine pattern by using a scanning charged particle microscope.
Semiconductor structures are amongst the finest man-made structures and suffer from very few imperfections only. These rare imperfections are the signatures which defect detection or defect review or quantitative metrology devices are looking for. Fabricated semiconductor structures are based on prior knowledge. For example, in a logic type sample, metal lines are running parallel in metal layers or HAR (high aspect ratio) structures and metal vias run perpendicular to the metal layers. The angle between metal lines in different layers is either 0° or 90°. On the other hand, for VNAND type structures it is known that their cross sections are spherical on average.
In the fabrication of integrated circuits, the features size is becoming smaller. The current minimum feature size or critical dimension is below 10 nm, for example 7 nm or 5 nm, and approaching below 3 nm in near future. Therefore, measuring edge shapes of patterns, and to determine the dimensions of features or the line edge roughness with high precision can become challenging. Edge shapes of patterns or roughness of lines can be subject to several influences. Generally, the edge shape of a line or pattern may be subject to the property of involved materials itself, the lithography exposure or any other involved process step, such as etching, deposition, or implantation. The measurement resolution of charged particle systems is typically limited by the sampling raster of individual image points or dwell times per pixel on the sample, and the charged particle beam diameter. The sampling raster resolution can be set for the imaging system, but should be adapted to the charged particle beam diameter on the sample. The typical raster resolution is 2 nm or below, but the raster resolution limit can be reduced with no physical limitation. The charged particle beam diameter has a limited dimension, which can depend on the charged particle beam operation conditions and lens. The beam resolution is generally limited by approximately half of the beam diameter. The resolution can be below 2 nm. However, well known deconvolution techniques can be applied to improve, for example, edge detection. Despite the high measurement resolution of actual charged particle systems of few, for example below 2 nm, it is challenging to obtain a measurement accuracy in 3D volumes with accuracy better than 10 nm. As an example, reference is made to Dunn, Kubis and Hull “Quantitative Three-Dimensional Analysis using Focused Ion Beam Microscopy” in “Introduction to Focused Ion Beams” edited by Gianuzzi and Stevie (2005). Here, the demonstrated 3D resolution is about 30 nm.
A common way to generate 3D tomographic data from semiconductor samples on nm scale is the so-called slice and image approach elaborated for example by a dual beam device. In such an apparatus, two particle optical systems are arranged at an angle. The first particle optical system can be a scanning electron microscope (SEM). The second particle optical system can be a focused ion beam optical system (FIB), using for example gallium (Ga) ions. A focused ion beam (FIB) of Ga ions is used to cut off layers at an edge of a semiconductor sample slice by slice and every cross section is imaged using a scanning electron microscope (SEM). The two particle optical systems might be oriented perpendicular or at an angle between 45° and 90°.
With the finer detail and the smaller feature sizes in modern integrated circuits, the reconstruction of the 3D tomographic image implies several challenges. Lateral stage drifts or drifts of the SEM column may cause offsets in the lateral positions of the structures from slice to slice. Variations in the FIB cutting rate may cause the intersection surfaces to be at varying distances. Image distortions may lead to cross section images with for example pin-cushion or shear distortion.
It is a common method to derive the lateral position of each slice as well as the distance from layer to layer with the help of so called fiducials. U.S. Pat. No. 9,633,819 B2 discloses an alignment method based on guiding structures (“fiducials”) exposed to the top of the sample.
U.S. Pat. No. 7,348,556 discloses a method to derive the line edge roughness based on a fiducial. Here, the fiducial is either already present on the surface of the workpiece or probe, or is milled at the location within a field of view.
However, the precision by using the fiducials can be limited by the fiducial generation process as well as the measurement precision of the charged particle optical column for measuring the fiducial position. The fiducial markers are typically coarse and may measure several 20 nm up to 100 nm and may also change arbitrarily their shape from the first to last slice such that the precision of the reconstruction is not sufficient for recent semiconductor structures of much smaller size and better overlay accuracy.
This and other effects can lead to artificially inhomogeneous edge shapes and positions and can limit the precision metrology of interconnected circuit patterns. In a 3D-reconstruction, wavy metal lines can be created and for example a line edge roughness measurement can be deteriorated by alignment errors. The metrology of dimensions of a fine pattern, or the derivation of a line edge roughness or surface roughness with high accuracy of a fine 3D pattern by cross sectioning may not be possible. At least certain known approaches are not able to address issues related to the recent high precision measurement for integrated circuits with minimum features sizes down to critical dimensions (CD) of 7 nm and below.
The present disclosure seeks to provide an improved method of obtaining a 3D volume image of an integrated semiconductor sample by cross sectioning of the integrated semiconductor sample. Desirably, the method can allow for an increased 3D reconstruction accuracy.
The present disclosure can provide a method for high precision, 3D reconstruction of 3D volume images of three-dimensional circuit pattern inspection by cross sectioning of the integrated circuits and a method, computer program product and apparatus for obtaining 3D volume images of an integrated semiconductor sample free of measurement artefacts induced by stage drift, imaging column drift or image distortion.
The method can allow for quantitative metrology of line edge positions, line edge roughness, feature dimensions or areas, for defect detection or defect review with high accuracy. Furthermore, the disclosure can provide a method, computer program product and apparatus for inspecting an edge shape of the fine pattern and to derive a line edge roughness or surface roughness of a fine pattern with high accuracy.
A concept provided in the present disclosure is basing the reconstruction of the 3D volume image on characteristic data that is known and/or provided with higher accuracy than the accuracy with which fiducials can be provided. As already explained above, the accuracy of the fiducials themselves can be limited. Therefore, according to the present disclosure, the characteristic data used for alignment of cross section images for the reconstruction of the 3D volume image can be no positional data of fiducials, but the characteristic data can be based on more accurately known and/or provided inner structures or features of an integrated semiconductor sample. These inner structures or features are for example metal lines, interconnects, a via, HAR structures or a gate structure. The alignment applied in the method of obtaining a 3D volume image of an integrated semiconductor sample according to the disclosure can therefore be termed a feature based or structure based alignment which expressions are used as synonyms within the present patent application.
In more detail, the feature based alignment can apply an inventive precision alignment of a sequence of cross section images to reconstruct a 3D tomographic data set or 3D volume image. The precision alignment can include methods for applying an alignment correction scheme and adjusting the slice positions according to the alignment correction scheme. The alignment correction scheme can be based on image or feature registration. Image registration generally refers to precision placement of cross section images in 3D volumes. Image registration can utilize features of integrated circuits such as metal lines, which are present in at least a part of the cross section images. With these features, present in at least two of consecutive cross sections images, the relative lateral position and rotation of the two consecutive cross section images can be determined with high accuracy. With this feature-based alignment, a higher accuracy can be obtained by the positions of features of integrated circuits, which are fabricated with high precision of current integrated semiconductor fabrication techniques.
Additionally, the accuracy can be improved by statistical methods, such as centroid extraction of features of structures present in integrated semiconductor samples, such as gates, metal lines or HAR structures, for example HAR channels. Other statistical methods can include averaging of measurement positions of several image features, or may consider outliers which deviate too much relative to a statistical expectation value. Thereby, a subpixel accuracy of the image alignment of individual cross section images can be achieved. Thereby, image registration of 2D cross section images can be achieved in 3D volume images with high, sub-pixel accuracy.
According to the disclosure, influences of a lateral stage drift as well as errors of the scanning charged particle image acquisition method can be reduced.
Furthermore, imaging aberrations such as distortion errors of the scanning charged particle imaging method and apparatus can be extracted and removed by image processing, utilizing the features or structures of integrated semiconductor samples. Low-order distortion aberration changes between consecutive image slices can be extracted and removed from the cross section images.
The disclosure will now be described in more detail.
According to a first aspect of the disclosure, the disclosure is directed to a method of obtaining a 3D volume image of an integrated semiconductor sample by feature based alignment, characterized by: obtaining at least a first cross section image and a second cross section image parallel to the first cross section image, wherein obtaining the first and second cross section images includes subsequently removing a cross section surface layer of the integrated semiconductor sample using a focused ion beam to make a new cross section accessible for imaging, and imaging the new cross section of the integrated semiconductor sample with an imaging device; and obtaining a feature based alignment of the at least first and second cross section images by image registration of each of the at least first and second cross section images, wherein the image registration is performed based on at least one common feature of the integrated semiconductor sample in the at least first and second cross section images.
The common feature that is present in the at least first and second cross section images is provided within the integrated semiconductor sample with high positional precision. Therefore, using data of this at least one common feature as a reference for image registration can allow for a higher accuracy in alignment as well.
According to an embodiment of the disclosure, the at least one common feature includes at least one of a metal line, a via, a HAR structure, a HAR channel or a gate structure. All these features can be linear or linearly elongated. They are provided and/or their position(s) are known in integrated semiconductor samples with a relatively high accuracy which can be for example in the range of 4 nm to 2 nm or even below 1 nm precision for the lowest and finest layers in the samples.
The image registration can be performed based on two or more common features. It can for example be performed based on three, four, five, ten, twenty or even more common features. The more common features contribute to the image registration performed, the better the alignment accuracy can become: The imaging accuracy for imaging the new cross section of the integrated semiconductor sample with an imaging device can be limited, but statistical approaches can be used to statistically improve the imaging accuracy and therefore the image registration process.
According to an embodiment, the image registration includes a statistical evaluation. This statistical evaluation can operate on the data of the individual cross section images and/or on the data of the 3D volume image. Here, the more cross section images are obtained, the more powerful statistical evaluation becomes. The statistical evaluation can include at least one of a computation of a centroid, a feature detection or a statistical averaging. In these cases, the statistical evaluation can operate on the data of the individual cross section images.
According to an embodiment of the disclosure, the method includes providing a fiducial based alignment of the at least first and second cross section images by measuring and evaluation of the position of alignment marks previous to the feature based alignment. In this way, a stepwise alignment can be carried out. The fiducial based alignment has a lower accuracy than the feature based alignment of the present disclosure. However, in some situations, stepwise alignment is desired, for example when the cross section images include highly repetitive structures/features.
According to an embodiment of the present disclosure, imaging of the new cross section of the integrated semiconductor sample is performed with at least one of a charged particle device, an atomic force microscope or an optical microscope. Different imaging techniques can be combined, for example for getting an overview image with comparatively low resolution first before taking an image with higher or highest resolution. An example for a charged particle device operating with high resolution is a scanning electron microscope employing a single electron beam (SEM) or a plurality of electron beams (multi SEM).
According to an embodiment, imaging the new cross section of the integrated semiconductor sample is performed with a charged particle device operating with electrons, wherein the focused ion beam and the electron beam are arranged and operated at an angle to each other and a beam axis of the focused ion beam and a beam axis electron beam intersect each other. The angle between the focused ion beam and the electron beam can for example be 90°, however, other angles are also possible.
According to an embodiment of the present disclosure, the at least a first and second cross section images are formed perpendicular to a top surface of the integrated semiconductor sample. Here, the top surface of the integrated semiconductor sample is assumed to be flat or it can be approximated as a flat surface or a flat surface can be fitted to the real surface mathematically. The top surface can also include a protective layer and/or a cap in which fiducials can be provided.
The at least a first and second cross section images can be formed perpendicular to metal lines or gates of at least one metal layer of the integrated semiconductor sample. These features are provided in a respective layer of the integrated semiconductor sample. They consequently intersect with the cross section images and are normally visible in more than one cross section image and can thus be used for the feature based high precision alignment. According to the geometric arrangement of this embodiment, the position of these features does not/shall not vary in different cross section images. This geometric arrangement is therefore suited for a lateral alignment in the x-y plane.
According to an embodiment of the disclosure, the at least a first and second cross section images are formed inclined at an angle deviating from 90° to metal lines or gates of at least one metal layer of the integrated semiconductor sample. The angle can deviate from 90° in several, for example all, metal layers of the integrated semiconductor sample. When the angle deviates from 90°, the geometric arrangement can also be suited for a precision alignment in the z-direction, say for precisely determining the distance of the plurality of cross section images with respect to each other in z-direction. According to an embodiment, the angle is 45°, but it can be also 30° or 60° or another angle.
According to an embodiment of the present disclosure, the at least a first and second cross section images are formed inclined to a top surface of the integrated semiconductor sample to reveal cross section images of at least one HAR channel perpendicular to the top surface of the integrated semiconductor sample. These HAR channels are comparatively fine, often pillar like and elongated structures extending through significant parts of the integrated semiconductor sample. The finer and the more elongated a structure is, generally the more precise is an alignment based on this structure. According to this embodiment, the cross section images are normally also formed inclined to layers of the integrated semiconductor sample. The top surface and the layers can be provided parallel to each other. According to this embodiment, it is possible to determine the positions of the HAR channels, to determine the distance dz between subsequent cross section images and to carry out a lateral alignment in the x-y plane.
According to an embodiment of the present disclosure, the at least a first and second cross section images are formed inclined to a top surface of the integrated semiconductor sample and a distance between the at least first and second cross section images is determined based on a position of fiducials provided on the top surface. As already explained above, the accuracy of fiducial based alignment is in principle smaller than the accuracy of feature based alignment according to the present disclosure. However, if a fiducial based alignment is applied prior to a feature based alignment, the accuracy of the fiducial based alignment can be increased by a factor of sin (3, wherein the angle (3 determines the angle between the axis of the focused ion beam and the top surface of the integrated semiconductor circuit. The smaller and therefore more glancing the angle (3 is, generally the better the accuracy of fiducial based alignment becomes.
Similarly, according to an embodiment of the disclosure, the at least a first and second cross section images are formed inclined to a top surface of the integrated semiconductor sample and a distance between the at least first and second cross section images is determined based on a position of features, for example HAR channels, provided inside the integrated semiconductor sample and perpendicular to the top surface. Here, the accuracy of determining a distance between subsequent features, for example HAR channels, can be enhanced by the factor sin (3, wherein the angle (3 determines the angle between the axis of the focused ion beam and the top surface of the integrated semiconductor circuit.
According to an embodiment of the disclosure, the image alignment includes subtraction of an image distortion deviation between the at least first and second cross section images. The subtraction of the image distortion deviation can include an approximation of the image distortion deviation by a basis distortion function.
According to an embodiment of the present disclosure, the method further includes the following steps: determining a curtaining signature of the new cross section; and using the curtaining signature for representing the cross section images as 3D cross section images.
The material removal rate of a focused ion beam can depend on the type of material being removed. For this reason, the surface of a new cross section obtained with a constant feed, but including different materials, may not be ideally flat, but may show a certain topography. It is often wavy like a curtain (“curtaining effect”). The images of a respective wavy surface show lines as artefacts which can in principle be misinterpreted as a feature or structure. Therefore, it is possible to carry out a curtaining correction. In certain known approaches, a curtaining correction is carried out by the so-called rocking stage method applying certain movements of the stage to remove a surface layer with the focused ion beam from different directions, thereby averaging out the wavy structure. However, the rocking stage method may not be suited for tomographic appliances, since slices of to be removed are too thin and respective errors or the drift of the stage is too big. Therefore, according to the present disclosure, another approach is taken: The wavy topography of the surface is measured and appropriately taken into consideration in the further procedure. Curtaining, or more general topography effects, can deteriorate the quality of the 3D reconstruction in that, e.g. reconstructed metal line cross sections are not rectangular but sheared or show bulges. Topography means that not all points in the image belong to the same plane, but they have an individual out of plane (z-) coordinate. If this information is not available, in the reconstruction the voxels are placed incorrectly.
Determining the curtaining signature therefore includes determining the 3D topography of the new cross section. The term signature indicates that the wavy topography is like a fingerprint/characteristic of the new cross section that is imaged. However, the term curtaining signature is not limited to a 3D topography generated because of a curtaining effect. The term curtaining signature covers a 3D topography of a cross section image or slice in general.
Methods for determining the 3D topography of a surface are in principle known. An example is given by Tadao Sugunuma in “Measurement of Surface Topography Using SEM with Secondary Electron Detectors”, J. Electron. Microsc., Vol. 34, No. 4, 428-337, 1985. Shadowing effects of 3D structures during imaging can be overcome. A solution is to use at least two different detectors for detecting the same signal from different directions. In more detail, particles emanating from the surface that is scanned are detected under two different angles. The arrangement of the detectors can be symmetric with respect to a normal of the surface to be imaged. Using the differential signal of the at least two detector signals allows for determining the 3D topography with high precision. Thus, the 3D topography of the new cross section image is obtained and the curtaining signature is determined. In a next step of the method according to the present disclosure, the curtaining signature is used for representing the cross section images as 3D cross section images. These 3D cross section images are not exactly flat, but often slightly curved and the position of image data is characterized in three dimensions x, y, z. The image registration is then performed on the basis of the 3D or wavy cross section images. This can significantly enhance the accuracy of the claimed method. Furthermore the measured 3D topography can be used in the reconstruction of the 3D volume: If this information is available, instead of simply stacking up slices, the true (x,y,z) positions of every point are used, i.e. a mathematical correction of the topography effects in the reconstruction can be performed.
According to an embodiment, the method further includes the following steps: determining a curtaining signature of the new cross section; and using the determined curtaining signature in a feedback loop for controlling the focused ion beam while removing the next cross section surface layer of the integrated semiconductor sample.
As already explained above, a new delayered cross section surface is not exactly flat, but exhibits a 3D topography defining the curtaining signature. So when delayering the next cross section to exhibit the next new cross section, this 3D topography can be taken into consideration and the focused ion beam can be controlled respectively to get a new cross section that is as flat as possible. The ion beam can be controlled to act longer and/or more often at positions representing a maximum in topography and shorter and/or less often at positions representing a minimum in topography. Thus, the next new surface will be more flat per se. Practically, the described kind of control can be integrated into the inventive method in terms of a feedback loop.
According to an embodiment of the disclosure, the method further includes aligning the at least first and second cross section images based on a predetermined footprint shape of features and/or a spatial distribution of the features in the cross section images. This kind of alignment(s) is useful when there exists prior knowledge about features/structures within the sample that is investigated and these features/structures are of a specific known geometric shape and/or when these features/structures are regularly spatially arranged. Based on prior knowledge about the features/structures, the ideal geometric shape of these features/structures in cross section images is known and a reference or footprint of these features/structures can be defined. If the features are for example pillar like features, for example pillar like HAR channels, then their footprint in a cross section image perpendicular to the main axis of the pillar like features is ideally circular. If the cross section images are taken inclined to the main axis of the pillar like features, their footprint is elliptical. If the imaged footprints deviate from the previously known and ideally assumed shape, the reason can be a misalignment in the direction perpendicular to the cross section images that can be corrected. In other words, the distance between subsequent cross section images shows a variation. Varying the distance of the cross section images in the direction of the virtual image plane can eliminate the distortion error in this direction.
According to an embodiment, the footprint shape of the features is circular or elliptical. These well-defined geometric shapes can allow for a very precise determination of deviations from the ideal shape and/or position.
According to an embodiment, the aligning is carried out in a direction perpendicular to the image planes of the cross section images and/or the aligning is carried out within the image plane of the cross section images. This can allow for a high precision alignment.
According to an embodiment of the present disclosure, after the image registration the at least first and second cross section images are combined to a 3D volume image. This 3D volume image is a tomographic image.
According to an aspect of the disclosure, the disclosure is directed to a computer program product with a program code for executing the method according to any one of the embodiments described above. The code can be written in any possible programming language and can be executed on a computer control system. The computer control system as such can include one or more computers or processing systems.
According to an aspect of the disclosure, the disclosure is directed to a semiconductor inspection device adapted to perform any of the methods according to any one of the embodiments as described above.
According to an embodiment, the semiconductor inspection device includes: a focused ion beam device; and a charged particle operating device operating with electrons and adapted for imaging of the new cross section of the integrated semiconductor sample, wherein the focused ion beam and the electron beam are arranged and operated at an angle to each other and a beam axis of the focused ion beam and a beam axis electron beam intersect each other.
The beam axis of the focused ion beam and the top surface of the integrated semiconductor sample can form an angle of about 90° with one another, and the focused ion beam and the electron beam form an angle of about 90° with one another. This geometric arrangement is one of the standard geometric arrangements of the semiconductor inspection device, since the directions of the cross section images for image registration fit to the geometric shape of the integrated semiconductor sample and a 3D volume image can be easily determined.
According to an embodiment, the beam axis of the focused ion beam and the top surface of the integrated semiconductor sample form an angle of about 25° with one another, and the focused ion beam and the electron beam form an angle of about 90° with one another. With this arrangement, a glancing incidence by angle β of the focused ion beam onto the integrated semiconductor sample can be realized which allows for higher precision when determining the distance between subsequent cross section images by a factor sin β. Other angles, for example 30°, or 60° are also possible. Additionally, the space for arrangement of the charged particle operating device operating with electrons becomes bigger which facilitates the overall arrangement and design of a cross beam device. For example, a more flat objective lens can be applied resulting in a reduced working distance for the electron beam which can be for example 5 mm or less. A typical working distance of the FIB is then for example in the range of 12 mm.
According to an embodiment, an imaging device for imaging the new cross section of the integrated semiconductor sample includes at least two detection units arranged at different positions for detecting particles emanating from the new cross section at different angles. This arrangement can be applied for determining a curtaining signature/3D topography of a cross section as described above. The arrangement of the detection units can be symmetric with respect to angles formed with a normal of the surface of the cross section and/or the detection units are provided opposite to one another in a scanning direction of the focused ion beam. The imaging device can include exactly two or exactly four detection units. Two detectors forming a pair are sufficient to determine the topography of the surface in one direction. Therefore, with four detection units, it is possible to determine the topography of the surface in two orthogonal directions, for example the topography (height, depth) of the x-y-plane. Generally, the detection units can be of any suitable kind. However, it is optional that at least two detection units forming a pair are of the same kind. This can facilitate signal processing. The detection units can detect for example back scattered electrons or secondary electrons emanating from the surface of the new cross section.
According to an aspect of the disclosure, the disclosure is directed to a method of obtaining a 3D volume image of an integrated semiconductor sample, characterized by: obtaining a sequence of N cross section images, wherein obtaining the sequence of N cross section images includes subsequently removing a cross section surface layer of the integrated semiconductor sample using a focused ion beam to make a new cross section accessible for imaging, and imaging the new cross section of the integrated semiconductor sample with a charged particle imaging device, wherein each of a cross section image planes of the sequence of N cross section images is oriented perpendicular to a z-direction, and wherein the integrated semiconductor sample is arranged that the direction parallel to a set of L metal lines of at least one metal layer Mk of the integrated semiconductor sample forms an angle with a cross section images plane, and wherein at least a subset of the sequence of N cross section images includes cross section image segments of the L metal lines; extracting a position P(x,y;l) of each of the cross section image segments of the l=1 to L metal lines; forming traces T(x,y;z;l) of the positions P(x,y;l) through the z-direction of at least a subset of the sequence of N cross section images; decomposing the traces T(x,y;z;l) into an average common wavy structure TA(x,y;z) and a residual deviation dT(x,y;z;l); and correcting the position of at least the subset of the sequence of N cross section images within the 3D volume image by displacing the subset of the sequence of N cross section images with the common wavy structure TA(x,y;z).
According to an embodiment, the extraction of at least one position P(x,y;l) includes at least one of edge extraction, corner localization or feature localization of the cross section image of the metal line l.
According to an embodiment, the extraction of at least one position P(x,y;l) includes centroid or center of gravity computation.
According to an aspect of the disclosure, the disclosure is directed to a computer program product with a program code for executing the method according to the fourth aspect of the disclosure.
According to an aspect of the disclosure, the disclosure is directed to a semiconductor inspection device adapted to perform any of the methods according to the fourth aspect of the disclosure.
The embodiments as described above can be fully or partly combined with one another, as long as no technical contradictions occur. This also holds for embodiments describing different aspects of the disclosure.
The present disclosure will be even more fully understood with reference to the following drawings, in which:
With the method, at least a first and second cross section images includes subsequently removing a cross section surface layer of the integrated semiconductor sample with a focused ion beam to make a new cross section accessible for imaging, and imaging the new cross section of the integrated semiconductor sample with a charged particle beam. From the sequence of these 2D cross section images 1000, a 3D image of the integrated semiconductor structure can be reconstructed. The distance dz of the cross section images 100 can be controlled by the FIB milling or polishing process and can be between 1 nm and 10 nm, such as about 3-5 nm.
An embodiment of the disclosure for fine alignment based on features or structures in the integrated semiconductor sample is described in of
The cross section image segments of the perpendicular metal lines in layers M1, M3, . . . , M7 can be extracted by image processing such as corner or edge detection, thresholding, or morphologic operations. Positions of detected metal lines can be computed based on centroid computation or computation of center of gravity. Alternatively, position determination of metal lines can be achieved by for example feature based registration. Generally, pattern recognition and position detection techniques, also called feature registration, can employ comparison of design shapes to the cross section image segments of the metal lines, or of reference cross section image segments of metal lines.
Feature registration can employ image correlation with a reference cross section image segment of for example a metal line, or can be based on the Euclidean image distances between the cross section image and a reference cross section image segment of for example a metal line. Those skilled in the art will be able to use methods equivalent to the above mentioned methods for the position computation of the cross section image segments of metals lines.
In
By connecting the centroids of the metal lines from slice to slice the traces of the centroids T(x,y;z;l) through z direction or a sequence of cross section images can be generated.
The extraction of the common wavy component TA(x,y;z) reveals an x-y-displacement vector (x,y) for each cross section images slice at position z, which is based on statistical evaluation of the lateral cross section image displacement. The statistical evaluation improves the accuracy and reduces errors of few individual structures or alignment marks such as the fiducials. Statistical evaluation includes for example averaging, centroid computation and can consider outliers. Examples are averaging of line edges by averaging multiple line edge points, the centroid computation, feature based registration or the statistical averaging over a set of multiple centroid points. Image processing algorithms and registration algorithms can be applied in order to remove artefacts or outliers by comparison of the feature or structure sets between two consecutive cross section images.
It should be mentioned, that the metal lines do not need to extend through the whole measured volume. As illustrated in
Comparisons between fiducial based alignment and structure-based alignment are shown in
A quantitative comparison of the improvement can be achieved through extracting a contour and calculating the standard deviation of the contour from its mean value. From the examples in
Another embodiment method is illustrated at
In the above embodiments, the cross section image planes are oriented perpendicular to the top surface 55 of the integrated semiconductor wafer, with the normal to the wafer top surface 55 oriented parallel to the y-direction, as shown in
The distance dx is measured and the angle α is in principle known, so ds can be calculated. This is in principle known.
Now, referring to
On the other hand, the distance ds now inclined to z-direction is
ds=dsz sin β
which leads to
In
However, also when back scattered electrons are detected as a signal for imaging, curtaining is still a problem, since the image information still stems from different depth on the surface. By a standard image reconstruction, it is assumed that the cross section image obtained by a back scattered electron signal is flat. However, this is not exactly the case. This contradiction leads to errors in image reconstruction and limits the resolution of the 3D image in the virtual, say mathematically reconstructed, image plane.
Therefore, according to the present disclosure, the resolution of the 3D image in the virtual image plane is improved by carrying out a curtaining correction. In more detail, the curtaining signature of a new cross section is determined.
When imaging a maximum 94 with the SEM 90, the signal strength that the detection units 95 and 96 receive in the form of particles emanating from the same position is slightly different because of a shadowing effect due to the topography. For example, when particles emanating from position x1, the detection unit 95 receives a slightly stronger signal than the detection unit 92. Similarly, when particles emanating from position x2 are detected, the detection signal of detection unit 96 is slightly stronger than the detection signal at detection unit 95. This difference in signal strength can be analyzed easily in the differential signal of both detection units 95, 96. Therefore, it is possible to determine the 3D topography of the surface 93 by scanning the surface 93 for example line by line. The curtaining signature of the surface 93 can therefore be determined and used in reconstruction of the cross section images. The resulting cross section images are themselves 3D images. An example is depicted in
According to the present embodiment, it is proposed to adjust the individual slice position/thickness such that the aforementioned distortion is minimized allowing one to investigate the actual geometrical properties of the individual pillars. The idea of the method is to use the information about the actual shape and the spatial layout of the pillar footprints available, e.g., from the design data or from other considerations (like symmetry). For example, it can be sufficient to assume that the actual pillar cross-sections are on average perfect circles whose centroids form a regular hexagonal grid as described above—a very common design of a VNAND chip. Then the position/thickness of the individual slices are adjusted until the pillar footprints match the assumed geometry (circles on a regular grid) as shown in the right part of
Since the actual probe may deviate from design or an assumption about a feature shape may not be accurate enough, the reconstructed pillar cross-sections obtained after the slice position adjustment may still deviate from the actual ones. However, in most cases, one expects the deviations of the pillars from design to be rather local (defects!). For example, a certain pillar might have a shape or a radius deviating from those of its neighbors. Also, its centroid might be offset from a respective position on the regular grid formed by other centroids. Such local deviations or defects will remain after the described adjustment of the slice positions and can thus be investigated. Indeed, the adjusted position of each slice is affected by all the pillar cross-sections “touched” by the slice. The effect of a single pillar cross-section on the adjusted slice position is expected to be relatively small. That is, the proposed adjustment allows to search for local defects while significantly reducing image distortion due to inaccurate slice position determination.
In general, data from any chip containing features with known footprint shapes and spatial distribution in a cross-section (or multiple cross-sections) perpendicular to the actual slices can be processed with the proposed method. The VNAND-memory chip layout is only used as an example with a relatively simple feature footprint.
The described method is also extensible to a case where the slices/cross section images suffer from small lateral offsets. That is, the slices may also be adjusted in a direction parallel to the slice plane (cross section image plane) such that a lateral alignment can be further improved.
A specific example of a workflow for the proposed adjustment of the slice positions is as follows: The available information about the actual shape of the pillar footprints (e.g., circles) and their spatial distribution (e.g. a certain regular grid) is used to construct a “reference image” R in the plane perpendicular to the pillars (and to the actual slices) which one expects in the absence of any distortions. An example of such a reference image is shown in
Other merit functions can be alternatively defined.
If the range of the tested X-positions is not too large (i.e., the uncertainty of the initial slice position determination is not too high), M will reach a unique minimum at a certain position xadjusted) which can be used as the final position for the individual slice S. The described procedure can be repeated for each individual slice S to obtain the final aligned (adjusted) 3D stack.
The superior precision alignment of the embodiments becomes evident when considering several advantages of the embodiments of the disclosure. First, the metal lines, gates, vias and HAR channels are running each in known planes and under known angles at 90° to each other, respectively, and are manufactured with much more elaborated fabrication technologies than any fiducial marks can be fabricated. Semiconductor fabrication technologies, such as immersion lithography exposure, metal deposition or ion implantation, directed RIE etching, and polishing for integrated circuits are tailored to critical dimensions of few nm, for example 7 nm, 5 nm or 3 nm in near future, and result in a typical pattern placement or overlay accuracy below 2 nm or even below 1 nm precision for the lowest and finest layers such as gate layers and lower metal layers such as M0. Generally, the overlay accuracy of metal lines is about a factor ⅓ better than the shortest dimension of the metal lines, and as a consequence, the low metal layer and gate layer overlay accuracy is in the order of or below 1 nm. The position accuracy or placement and dimensions of the gates or metal lines is thus much better than the typical fiducials produced by the coarse FIB assisted deposition process, with FIB beam diameter in the order of for example 20 nm and FIB scanning positioning accuracy of above 3-5 nm. The metal lines of recent integrated semiconductor samples with minimum feature sizes (CD) of few nm, such as 5 or 3 nm, allow thus a feature based alignment which is at least a factor 3 improved over a fiducial based alignment of the prior art. As a result, the position computation, such as the centroid computation for metal lines or gates leads to a much higher precision and the displacement of the cross section images can be determined much more precise compared to the position of fiducials. The extraction of the metal lines with image processing techniques, optional in combination with the evaluation and subtraction of image distortions, lead such to an improved precision alignment of cross section images via feature or structure based registration.
Second, from the cross section images the position of a metal line, a via, a HAR channel or a gate is derived for example from a contour line. The computation for example of the centroid of a single common feature in two subsequent slices includes statistical averaging and is thus more robust to e.g. image noise and thereby improves accuracy of the alignment of the two image slices. Third, the typical larger number L of metal lines, for example two, five, 10 or up to 100, further improves the statistics of the position determination for purposes of image registration and alignment. Line edge roughness derivation can be improved at least by a factor of 1.5, factors of 2-3 can easily be achieved. Since defects are rare they do not affect the overall quality of alignment methods using many structures at once. The statistical evaluation of feature based alignment is demonstrated to thus enable an improvement of at least factor 1.5 over the fiducial based alignment of the prior art.
In addition, defect candidates can be detected as outliers from the statistical evaluation.
In another embodiment, or in addition to the described above, integrated semiconductor structures are a priory known structures. Design information or 3D CAD information can be used to improve the edge extraction of the metal lines and HAR channels, the position extraction as well as image registration. For example, CAD information can be used to identify locations were metal lines end and therefore should not be visible in cross section images any more. Thereby, outliers of the image processing methods can be reduced. In addition, defect candidates can be detected as outliers from the statistical evaluation.
In another embodiment, the structure or feature-based alignment is combined with fiducial based alignment. Integrated semiconductor samples may include highly repetitive features such as gates in the gate layer, which might lead to ambiguities in the image registration. Generally, a coarse registration with fiducials formed on top of the integrated semiconductor sample can reduce the ambiguity and increase the speed of fine image registration by feature or structure-based alignment according to any of the embodiment of the disclosure.
Image processing methods as described above, such as corner or edge detection, thresholding, or morphologic operations, or similar operations, are well known in the art. Image processing is recently improved by the increase of computation speed for example by usage of computer clusters including several 100s of processors. Image processing methods to extract features or structures of integrated semiconductor samples can also involve or be replaced by Machine Learning algorithms.
The above-described embodiments are intended to be examples only. Despite the embodiments are described at the example of semiconductor structures as probes, the method may as well be applied to materials or probes of comparable structures which allow precise image registration. Alterations, modifications, variations and combinations can be effected to the particular embodiments by those of skill in the art without departing from the scope, which is defined by the claims appended hereto.
Number | Date | Country | Kind |
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102019006645.6 | Sep 2019 | DE | national |
The present application is a continuation of, and claims benefit under 35 USC 120 to, international application PCT/EP2020/000101, filed May 25, 2020, which claims benefit under 35 USC 119 of German Application No. 10 2019 006 645.6, filed Sep. 20, 2019, and U.S. Provisional Application No. 62/858,470, filed Jun. 7, 2019. The entire disclosure of each of these applications are incorporated by reference herein.
Number | Date | Country | |
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62858470 | Jun 2019 | US |
Number | Date | Country | |
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Parent | PCT/EP2020/000101 | May 2020 | US |
Child | 17540976 | US |