CURRENT CONTROLLED OSCILLATOR WITH REGULATED SYMMETRIC LOADS

Abstract

An integrated circuit incorporating a bias circuit for a current-controlled oscillator (ICO) with improved power supply rejection ratio (PSRR) is described. The bias circuit for the ICO includes two error amplifiers. The first error amplifier regulates the bias voltage, VBN, referenced to a ground supply (GND). The second error amplifier regulates the bias voltage, VBP, referenced to a positive power supply (VDD). The VBP and VBN bias voltages have improved PSRR relative to conventional ICO bias circuits for noise injected into VDD and GND.

Description

TECHNICAL FIELD

The present disclosure relates generally to integrated circuits, and more specifically to low-jitter/low-voltage phase-locked loop and current controlled oscillator circuits.

BACKGROUND

Low-jitter/low-voltage phase-locked loops and current-controlled oscillators (PLL-ICOs) operating in noisy power-supply environments with other digital circuits are increasingly important in integrated circuit (IC) designs. These PLL-ICOs are needed to generate clock frequencies for different functional blocks in an IC, such as general purpose processor/memory clocks, analog to digital and digital to analog converter clocks, audio CODEC clocks, digital signal processing clocks, external interface clocks, etc.

In particular, embedded analog circuits such as PLL-ICOs rely on a wide-band noise-free power-supply (V_DD) to meet clock phase-noise and timing-jitter requirements. As IC designs progress towards embedding more analog circuits along with digital processors in the same silicon die, it becomes more difficult in the IC design to include independent low-noise power-supply (V_DD) connections for each embedded analog core. Low Drop-Out (LDO) voltage regulators have been traditionally used to meet this requirement. However, designing wide-band power supply rejection ratio (PSRR) LDO voltage regulators, using only on-chip components is a difficult design task and there may be a substantial silicon die area penalty for each additional wide-band PSRR LDO voltage regulator.

Traditionally, on-chip PLL-ICOs use independent power-supply (V_DD) bumps to get a clean power supply (V_DD) connections. The number of power-supply (V_DD) bumps increases as multiple PLLs are integrated into an IC. The number of power-supply (V_DD) bumps and silicon die bond pads increases as multiple PLL-ICOs and other embedded analog cores are integrated into an IC. The power-supply (V_DD) bumps refer to a solder ball connection between a packaged integrated circuit (packaged IC) and the main application circuit board. By improving the PSRR of individual circuit blocks on the IC, such as any PLL-ICOS, the number of power-supply (V_DD) and ground (GND) connections can be minimized, thereby reducing the packaged IC pin count, IC and main application circuit board routing complexity.

There is a need for a low-jitter PLL-ICO with improved power supply rejection ratio (PSRR) for integration with other circuit blocks in an IC design. A substantial improvement in PLL-ICO PSRR allows a high-speed/low-jitter PLL-ICO to share power supply (V_DD) connection(s) with other circuit blocks within an IC design; thereby IC die size is reduced, die floor-plan and layout are simplified, IC package and die pin count are lessened, and ultimately IC cost is lowered.

SUMMARY

An integrated circuit is described incorporating a bias circuit for a current-controlled oscillator (ICO) with improved power supply rejection ratio (PSRR) is described. The bias circuit for the ICO includes two error amplifiers. The first error amplifier regulates the bias voltage, V_BN, referenced to a ground supply (GND). The second error amplifier regulates the bias voltage, V_BP, referenced to a positive power supply (V_DD). The V_BP and V_BN bias voltages have improved PSRR relative to conventional ICO bias circuits for noise injected into V_DD and GND.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows a block diagram of an integrated circuit (IC) with PLL and ICO circuit blocks sharing power supply connections with other digital and analog circuit blocks.

FIG. 2 shows a schematic diagram of a PLL-ICO circuit block.

FIG. 3 shows a schematic diagram of a conventional current-controlled oscillator (ICO) with symmetric loads, utilizing a VtoI bias circuit to convert V_ctrl to I_ctrl, V_BN and V_BP with error amplifier in the V_ctrl to V_BN signal path only.

FIG. 4 shows a schematic diagram of an improved current-controlled oscillator (ICO) with symmetric loads, utilizing a VtoI bias circuit to convert V_ctrl to I_ctrl, V_BN and V_BP with two error amplifiers—a first one in the V_ctrl to V_BN signal path and a second one in the V_ctrl to V_BP signal path.

FIG. 5 shows a graph of the power supply (V_DD) induced clock jitter vs. jitter frequency for CK_OUT=768 MHz.

To facilitate understanding, identical reference numerals have been used where possible to designate identical elements that are common to the figures, except that suffixes may be added, when appropriate, to differentiate such elements. The images in the drawings are simplified for illustrative purposes and are not necessarily depicted to scale.

The appended drawings illustrate exemplary configurations of the disclosure and, as such, should not be considered as limiting the scope of the disclosure that may admit to other equally effective configurations. Correspondingly, it has been contemplated that features of some configurations may be beneficially incorporated in other configurations without further recitation.

DETAILED DESCRIPTION

The device described therein may be used for various IC designs including, but not limited to wireless communication devices for cellular, PCS, and IMT frequency bands and air-interfaces such as CDMA, TDMA, FDMA, OFDMA, and SC-FDMA. In addition to cellular, PCS or IMT network standards and frequency bands, this device may be used for local-area or personal-area network standards, WLAN, Bluetooth, & ultra-wideband (UWB).

FIG. 1 shows a block diagram of an integrated circuit (IC) with PLL and ICO circuit blocks sharing power supply connections with other digital and analog circuit blocks in accordance with the present embodiment as shown. IC 100 includes one or more PLL-ICOs 105 that may generate any number of clock signals required to operate multiple circuit blocks within the IC or sent to external circuits and signal interfaces. Individual PLL(s) 110 and ICO(s) 120 may be customized for different frequency ranges and jitter specifications. IC 100 may integrate many different functions, including analog-to-digital/digital-to-analog 170, processor(s) 180, memory 190, and may be implemented in sub-micron semiconductor geometry (silicon for example) processes (65 nm or 45 nm CMOS are current example processes) and may be optimized for wireless communication device applications. In current silicon processes for wireless communication device applications with battery-powered operation, IC 100 must be designed with supply voltages as low as possible to operate with minimal power consumption and within the breakdown voltage of the silicon process. Although there are multiple external positive power supply (V_DD) and ground supply (GND) connections, ideally individual circuit blocks may need noise-free power supplies if the power-supply rejection ratio (PSRR) of individual circuit blocks is not optimal.

FIG. 2 shows a schematic diagram of a PLL-ICO circuit block 105 of FIG. 1 in accordance with the present embodiment as shown. PLL-ICO circuit block 105 includes PLL 110 and ICO 120. PLL 110 includes a reference clock input, CK_IN. PLL 110 also includes a phase-frequency detector (PFD 112), a charge pump (CP 114), a loop filter (LF 116), and a L+M/N divider 118. ICO 120 includes an input signal, V_ctrl, and an output signal, CK OUT. ICO 120 also includes a VtoI converter (VtoI 122), a current controlled oscillator (N-stage Ring Oscillator 124) with output frequency F_OSC, and a replica bias generation circuit (bias circuit 126).

Under normal PLL-ICO 105 operation, CK_IN is compared with the L+M/N divider 118 output clock utilizing PFD 112. PFD 112 generates a series of UP and DOWN pulses to indicate that the N-Stage Ring Oscillator 124 is either above or below the desired frequency at each phase comparison cycle with CK_IN.

The UP and DOWN pulses control CP 114. CP 114 outputs UP or DOWN current pulses of a pre-determined amplitude but with a duration that is dependent on the phase difference between the two input clock signals at a node labeled I_CP. I_CP is filtered by LF 116 to create an analog control voltage labeled V_ctrl. V_ctrl is the input signal to ICO 120. Within ICO 120, V_ctrl is converted to a control current (utilizing VtoI 122), I_ctrl, along with V_BP and V_BN by bias circuit 126, to adjust the N-Stage Ring Oscillator 124 output, CK_OUT, frequency, F_OSC.

There may be an inverter between PFD 112, CP 114, and LF 116 since VtoI 122 typically inverts the relationship between V_ctrl and N-Stage Ring Oscillator 124 output frequency (F_OSC˜−V_ctrl). The two frequencies of signals CK_IN and CK_OUT÷(L+M/N), are equal in the PLL locked state and V_ctrl, V_BP, V_BN, and I_ctrl converge to a set of stable bias voltages and current respectively.

As mentioned previously, designing PLL-ICOs to meet the requirements of these IC designs has been very challenging due to the tight jitter requirements required for high-speed operation and in wireless devices. The low-jitter and high-speed operational performance is impacted by the noise present on the power supply (V_DD) to the PLL-ICOs. This noise is increased in IC designs with a multitude of circuit blocks and processors integrated on the same silicon die. Each active circuit block may inject noise into the common power supply (V_DD) for individual PLL-ICOs and other functional blocks (both analog and digital power supplies).

The PLL-ICO circuit block 105 described herein may be used for various electronics circuits including communication circuits. For example, PLL-ICO circuit block 105 may be used in (1) a transmitter subsystem to generate a local oscillator (LO) signal used for frequency up-conversion, (2) a receiver subsystem to generate an LO signal used for frequency down-conversion, (3) a digital subsystem to generate clock signals used for synchronous circuits such as flip-flops and latches, and (4) other circuits and subsystems. For clarity, PLL-ICO circuit block 105 for a CMOS semiconductor IC device is described below.

FIG. 3 shows a schematic diagram of a conventional current-controlled oscillator (ICO) with symmetric loads, utilizing a VtoI bias circuit to convert V_ctrl to I_ctrl, V_BN and V_BP with error amplifier in the V_ctrl to V_BN signal path only of FIG. 2 in accordance with the present embodiment as shown. ICO 120 includes a VtoI 122, a replica bias generation circuit 126, an error amplifier 132, and an N-stage ring oscillator (with stages 124a, 124b . . . 124n).

ICO 120 includes an input control voltage, V_ctrl, which is converted to a set of two bias voltages, V_BP and V_BN by VtoI 122, error amplifier 132, and replica bias generation circuit 126. V_BP is a replica voltage of V_ctrl. V_BP and V_BN set the bias current, I_ctrl, in conventional ICO 120. Error amplifier 132 between V_ctrl and V_BN regulates the voltage relationship between V_ctrl and V_BN.

V_BP and V_BN control N-Stage Ring Oscillator 124 composed of stages 124a, 124b, through 124n. The output amplitude of N-Stage Ring Oscillator 124 may be restored to digital logic levels with a level translator 128. In N-Stage Ring Oscillator 124, the number of stages is odd and either 3 or 5, however more stages may be added depending on the application for ICO 120.

Different ring oscillator stage designs are possible that may still utilize the bias circuit components 122, 126, & 132. As V_ctrl is lowered in voltage, the bias current for the ICO 120, I_ctrl, increases along with V_BN. V_BP tracks V_ctrl or have the same polarity. As the bias current, I_ctrl, to the ICO 120 increases, the output frequency, CK_OUT (equal to F_OSC from FIG. 2) also increases since the delay of each stage (124a through 124n) is decreased and as the rise and fall times at each stage output (124a through 124n) decreases.

The error amplifier 132 regulates the V_BN voltage and optimizes the power supply rejection ratio (PSRR) from the ground (GND) rail connection only. The PSRR of the conventional ICO 120 circuit is limited by the match accuracy of VtoI 122 and replica bias generation circuit 126 that are tied to V_BN since the replica bias generation circuit 126 uses current regulation rather than voltage regulation. There is no error amplifier in the V_ctrl to V_BP signal path and the PSRR is not optimized from the positive power supply (V_DD) rail connection as a result.

The same bias control circuit composed of VtoI 122, replica bias generation circuit 126 and error amplifier 132 may be utilized to control a delay-locked loop (DLL) rather than a phase-locked loop (PLL). The control principles are the same as shown in FIG. 3, except the propagation delay of the cascaded stages is proportional to V_ctrl and V_BP (and inversely proportional to I_ctrl and V_BN).

FIG. 4 shows a schematic diagram of an improved current-controlled oscillator (ICO) with symmetric loads, utilizing a VtoI bias circuit to convert V_ctrl to I_ctrl, V_BN and V_BP with two error amplifiers- a first one in the V_ctrl to V_BN signal path and a second one in the V_ctrl to V_BP signal path of FIG. 2 in accordance with the present embodiment as shown. ICO 120a includes a VtoI 122 (same as the ICO 120 of FIG. 3), a replica bias generation circuit 126a (reconfigured in FIG. 4), error amplifiers 132 (same as the ICO 120 of FIG. 3) and 134 (new in FIG. 4), and an N-stage ring oscillator (with stages 124a, 124b . . . 124n) (same as the ICO 120 of FIG. 3).

ICO 120a includes an input control voltage, V_ctrl, which is converted to a set of two bias voltages, V_BP and V_BN by VtoI 122, error amplifiers 132 and 134, and replica bias generation circuit 126a. V_BP and V_BN set the bias current, I_ctrl, in the improved ICO 120a. As shown in both ICO 120 (in FIG. 3) and 120a (in FIG. 4), error amplifier 132, between V_ctrl and V_BN, regulates the voltage relationship between V_ctrl and V_BN. Within ICO 120a only, error amplifier 134, between V_ctrl and V_BP, regulates the voltage relationship between V_ctrl and V_BP.

V_BP and V_BN control N-Stage Ring Oscillator 124 composed of stages 124a, 124b, through 124n. The output amplitude of N-Stage Ring Oscillator 124 may be restored to digital logic levels with a level translator 128. In N-stage Ring Oscillator 124, the number of stages is odd and either 3 or 5, however more stages may be added depending on the application for ICO 120a. Different ring-oscillator stage designs are possible that may still utilize the bias circuit components 122, 126a, & 132. As V_ctrl is lowered in voltage, the bias current for the ICO 120a, I_ctrl, increases along with V_BN. V_BP tracks V_ctrl or have the same polarity.

As the bias current, I_ctrl, to the ICO 120a increases, the output frequency, CK_OUT (equal to F_OSC from FIG. 2) also increases since the delay of each stage (124a through 124n) is decreased and as the rise and fall times at each stage output (124a through 124n) decreases. The error amplifier 132 regulates the V_BN voltage and optimizes the power supply rejection ratio (PSRR) from the ground (GND) rail connection only as previously shown for ICO 120 in FIG. 3.

With the error amplifier 134 regulating the V_BP voltage, the power supply rejection ratio (PSRR) of the ICO 120a from the power supply (V_DD) rail connection is improved relative to ICO 120 in FIG. 3. The power supply rejection ratio (PSRR) is improved in ICO 120a by observing that the output impedance of the V_BP signal path is reduced relative to the conventional ICO 120 circuit as previously shown in FIG. 3.

The additional error amplifier 134 in FIG. 4 sets the V_BP node output impedance to 1/(A(s)*R_out), where A(s) is the additional error amplifier 134 loop gain. The A(s) should be a low-pass transfer function with a unity gain bandwidth of 100 MHz or greater and a DC gain of 40 to 50 dB. R_out is the output impedance of additional error amplifier 134 is in the range of several hundred ohms.

As described for the conventional ICO 120 circuit as shown in FIG. 3, the V_BP node output impedance is equal to the current mirror output impedance, 1/gm, where gm is the trans-conductance of the PMOS devices in the replica bias generation circuit 126a and is in the range of tens of milliamps/volt. Since A(s)*Rout>>gm over a wide frequency range, the output impedance of the V_BP node is much lower in the improved ICO circuit 120a of FIG. 4 than the conventional ICO 120 circuit of FIG. 3; thereby the PSRR of the ICO 120a circuit in FIG. 4 is superior, over a range of noise frequencies present on V_DD in comparison to the ICO 120 circuit of FIG. 3.

Another benefit of utilizing error amplifiers 132 and 134 in FIG. 4 for both V_BP and V_BN nodes, is to achieve the regulated symmetric loads, which further improves ICO 120a noise suppression in the presence of coupling paths from other circuit blocks into either the ground (GND) or positive power supply (V_DD) connections of the circuit.

The same bias control circuit composed of VtoI 122, replica bias generation circuit 126a, error amplifiers 132 and 134 may be utilized to control a delay-locked loop (DLL) rather than a phase-locked loop (PLL). The control principles are the same as shown in FIG. 3, except the propagation delay of the cascaded stages is proportional to V_ctrl and V_BP (and inversely proportional to I_ctrl and V_BN).

FIG. 5 shows a graph of the power supply (V_DD) induced clock jitter vs. jitter frequency for CK_OUT=768 MHz of FIGS. 3-4 in accordance with the present embodiment as shown. The PSRR of ICO 120 (from FIG. 3) and ICO 120a (from FIG. 4) are compared for an output frequency, F_OSC, equal to 768 MHz, with a 50 mV AC noise frequency sweep applied on V_DD from 10 MHz to 1 GHz. For V_DD noise below 500 MHz, the ICO 120a circuit in FIG. 4 demonstrates lower peak-to-peak jitter than a conventional ICO 120 circuit as previously shown in FIG. 3.

The definition of peak-to-peak jitter is given as

$\Delta T_{\mathrm{pk}-\mathrm{pk}}=\mathrm{Vm}\times \frac{\mathrm{Kvco}}{{\mathrm{Fosc}}^2}\times \sqrt{1-\cos \left(2\pi \times \mathrm{Fm}/\mathrm{Fosc}\right)},$

where Vm is the amplitude of the V_DD noise, Fosc is the ICO frequency (Hz), Kvco is the gain control slope (Hz/V) between V_ctrl and ICO output frequency, and Fm is the frequency (Hz) of the V_DD noise. As can be calculated with the peak-to-peak jitter equation, the peak-to-peak jitter reaches a maximum value for both ICO 120 and ICO 120a circuits when Fm=½×Fosc or 384 MHz.

Those of skill in the art would understand that signals may be represented using any of a variety of different techniques. For example, data, instructions, signals that may be referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, or any combination thereof

Those of skill would further appreciate that the various illustrative radio frequency or analog circuit blocks described in connection with the disclosure herein may be implemented in a variety of different circuit topologies, on one or more integrated circuits, separate from or in combination with logic circuits and systems while performing the same functions described in the present disclosure.

The previous description of the disclosure is provided to enable any person skilled in the art to make or use the disclosure. Various modifications to the disclosure will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other variations without departing from the scope of the disclosure. Thus, the disclosure is not intended to be limited to the examples and designs described herein but are to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A current-controlled oscillator (ICO) comprising: a first voltage to current converter having a first receiving an input control voltage, and a first output for producing a control current inversely proportional to the input control voltage;a first error amplifier negative input having a first receiving the input control voltage, the first error amplifier positive input having a second receiving the first voltage to current converter first output, and the first error amplifier second output producing a bias voltage inversely proportional to the input control voltage;a current mirror having a third receiving an input control current from a first voltage to current converter first output, a fourth input coupled to the bias voltage of the first error amplifier second output for regulating the control current proportionally to the bias control voltage of the first error amplifier second output;a replica stage having a fifth receiving an input bias voltage from the first error amplifier second output, and the replica stage third output producing a control current equivalent to the first voltage to current converter first output control current; anda second error amplifier negative input having a sixth receiving the input control voltage, the second error amplifier positive input having a seventh coupled to the replica stage third output, and the second error amplifier fourth output producing a bias voltage inversely proportional to the first error amplifier second output bias voltage, the first error amplifier output second output and the second error amplifier fourth output forming a pair of regulated symmetric loads to control the bias current of an N-stage current-controlled oscillator.

2. The ICO as recited in claim 1, wherein the ICO is configured to be controlled by a phase-locked loop (PLL).

3. The ICO as recited in claim 2, wherein the ICO and PLL are integrated circuits on a common substrate.

4. The ICO as recited in claim 3, wherein the ICO output is configured to clock a general purpose processor.

5. The ICO as recited in claim 3, wherein the ICO output is configured to clock a digital signal processor.

6. The ICO as recited in claim 3, wherein the ICO output is configured to clock an analog-to-digital converter (ADC).

7. The ICO as recited in claim 3, wherein the ICO output is configured to clock a digital converter (DAC).

8. The ICO as recited in claim 3, wherein the ICO output is configured to generate a local oscillator for a radio frequency circuit.

9. A current-controlled clock delay line comprising: a first voltage to current converter having a first receiving an input control voltage, and a first output for producing a control current inversely proportional to the input control voltage;a first error amplifier negative input having a first receiving the input control voltage, the first error amplifier positive input having a second receiving the first voltage to current converter first output, and the first error amplifier second output producing a bias voltage inversely proportional to the input control voltage;a current mirror having a third receiving an input control current from a first voltage to current converter first output, a fourth input coupled to the bias voltage of the first error amplifier second output for regulating the control current proportionally to the bias control voltage of the first error amplifier second output;a replica stage having a fifth receiving an input bias voltage from the first error amplifier second output, and the replica stage third output producing a control current equivalent to the first voltage to current converter first output control current; anda second error amplifier negative input having a sixth receiving the input control voltage, the second error amplifier positive input having a seventh coupled to the replica stage third output, and the second error amplifier fourth output producing a bias voltage inversely proportional to the first error amplifier second output bias voltage, the first error amplifier output second output and the second error amplifier fourth output forming a pair of regulated symmetric loads to control the bias current of an N-stage current-controlled delay line.

10. The clock delay line as recited in claim 9, wherein the clock delay line is configured to be controlled by a delay-locked loop (DLL).

11. The clock delay line as recited in claim 10, wherein the clock delay line and DLL are integrated circuits on a common substrate.

12. The clock delay line as recited in claim 11, wherein the clock delay line output is configured to provide a master clock and one or more time delayed clock signals.

13. The clock delay line as recited in claim 12, wherein the master clock and time delayed clock signals are configured to clock an analog-to-digital converter (ADC).

14. A method of regulating output bias voltages, VBN and VBP, of an N-stage ring oscillator for improved power supply rejection ratio, comprising: identifying a control voltage Vctrl;generating a control current Ictrl on the basis of the control voltage Vctrl;generating, using the control voltage Vctrl and control current Ictrl, a regulated bias voltage VBN referenced to a ground supply GND;generating, using the regulated bias voltage VBN and control voltage Vctrl, a regulated bias voltage VBP referenced to a positive power supply VDD; andcoupling the regulated bias voltages VBP and VBN to the input of the N-stage ring oscillator to adjust the N-stage ring oscillator output frequency.

15. The method of claim 14, wherein VBP and VBN are regulated symmetric loads.

16. A method of regulating output bias voltages, VBN and VBP, of an N-stage clock delay line with improved power supply rejection ratio, comprising: identifying a control voltage Vctrl; generating a control current Ictrl on the basis of the control voltage Vctrl;generating, using the control voltage Vctrl and control current Ictrl, a regulated bias voltage VBN referenced to a ground supply GND;generating, using the regulated bias voltage VBN and control voltage Vctrl, a regulated bias voltage VBP referenced to a positive power supply VDD; andcoupling the regulated bias voltages VBP and VBN to the input of the N-stage clock delay line to adjust the N-stage clock delay line input to output clock delay time.

17. The method of claim 16, wherein VBP and VBN are regulated symmetric loads.