This disclosure relates generally to electronics and more particularly to microcontroller systems.
Low power consumption is an increasingly important parameter for microcontroller systems. The wakeup time from a power saving mode is also an important parameter. Various components of the system can add to the time for the system to exit a power saving mode. For example, a memory module can increase the wakeup time from a power saving mode by waiting on a reference current source to reach a target reference current, which can vary depending on temperature or other environmental conditions or both.
Conventional systems rely on a system clock to determine how long it takes a reference current source to reach a target reference current. The length of time to wait for the reference current source is fixed based on a maximum estimated time for reaching the target reference current.
A microcontroller system is determining to exit a power saving mode and, in response, enable a reference current source to begin providing a reference current for a memory module. The microcontroller system determines that the reference current has reached a substantial fraction of a target reference current, and, in response to determining that the reference current has reached a substantial fraction of the target reference current, enables the memory module to begin performing one or more memory operations.
Particular implementations of the microcontroller system can provide one or more of the following advantages: 1) the wakeup time of a memory module can be reduced; 2) power consumption can be reduced by virtue of not always having the reference current circuit active; and 3) the wakeup time can be tailored to the environmental conditions that affect the system.
The details of one or more disclosed implementations are set forth in the accompanying drawings and the description below. Other features, aspects, and advantages will become apparent from the description, the drawings and the claims.
The reference current circuit can be, for example, internal to the memory module. In some implementations, the memory module is a flash memory module, and the reference current circuit is internal to the flash memory module. The flash memory module can also be configured to use an external reference current circuit. For example, the flash memory module can use the reference current circuit upon exiting a power saving mode, which the external reference current circuit is stabilizing.
To increase the wakeup speed of the memory module, it is useful to monitor the output of the reference current circuit and determine when the output reference current has reached a substantial fraction of a target reference current. The memory circuit can begin performing memory operations when the output reference current reaches the substantial fraction of the target reference current, instead of waiting, e.g., until a predetermined amount of time has passed. The output reference current will reach the substantial fraction of the target reference current in differing amounts of time due to differences in temperature and other environmental factors.
The reference current circuit includes an internal reference voltage 102. The internal reference voltage may produce a reference voltage of lower accuracy then a bandgap reference voltage with a slower wakeup time. The internal reference voltage is coupled to a matching element 104.
The matching element is matched to the memory cells of the memory module. For example, where the memory module is a flash memory module, the matching element can be a memory cell, from the same process as the other memory cells, lacking a floating gate. The matching element is used to compensate for process variations that may exist in the memory cells.
The matching element is coupled to a calibration module 106. The calibration module can multiply a current output from the matching element by a factor, e.g., to increase speed or reduce power consumption as needed. The factor can be received from the microcontroller by a “calibrate” signal. The calibration module also optionally receives a “reset” signal which can be used to reset the calibration module, e.g., cause the calibration module to reinitialize the output current.
The calibration module outputs the “output” reference current. Because the output is coupled to a capacitive load, it takes some time for the reference current to reach a target reference current when the system is exiting a power saving mode where the reference current is disabled. The capacitive load can be, for example, one or more sense amplifiers of the memory module. An optional output booster 108 is also coupled to the output and can be configured to output a pulse to decrease the time for the reference current to reach the target reference current.
The reference current circuit includes a copy branch 110 that generates a “ready” signal. The copy branch is configured so that the ready signal is set when the output reference current is at least a substantial fraction of a target reference current. The memory module can read the ready signal and then begin performing memory operations.
The copy branch is a mirror view of the circuitry for producing the output reference voltage, e.g., having a capacitive load about equal to the capacitive load at the output. The copy branch can include a comparator configured to determine whether the copy branch output is at least a substantial fraction of the target reference current. For example, the comparator can be a low power comparator using simplified circuitry.
Prior to time t1, the system is in a power saving mode. The reference current circuit is disabled. At time t1, the system determines to exit the scenario. The enable signal rises and the output current starts rising while it charges a capacitive load. The read signal stays low, and the reference voltage rises quickly and then continues to rise while the output current charges the capacitive load.
At time t2, the output current reaches a substantial fraction of a target current. For example, the target current can be 20 micro amps, and the substantial fraction can be 90%. The ready signal rises as a result of monitoring the output current by a monitoring circuit, e.g., as described above with reference to
The system determines to exit a power saving mode (302). For example, the system can receive a request from a user system requiring the system to activate one or more modules. In response, the system enables a reference current source for a memory module (304). The reference current source can be, for example, an internal reference current source inside the memory module that the memory module uses while a system voltage reference is waking up.
The system monitors the reference current from the reference current source and, determines that the reference current has reached at least a substantial fraction of the target reference current (308). For example, the system can monitor the reference current via a copy branch as described above with reference to
While this document contains many specific implementation details, these should not be construed as limitations on the scope what may be claimed, but rather as descriptions of features that may be specific to particular embodiments. Certain features that are described in this specification in the context of separate embodiments can also be implemented in combination in a single embodiment. Conversely, various features that are described in the context of a single embodiment can also be implemented in multiple embodiments separately or in any suitable sub combination. Moreover, although features may be described above as acting in certain combinations and even initially claimed as such, one or more features from a claimed combination can, in some cases, be excised from the combination, and the claimed combination may be directed to a sub combination or variation of a sub combination.
This application claims the benefit and priority of U.S. Provisional Application Ser. No. 61/704,065, filed Sep. 21, 2012, the entire contents of which is hereby incorporated by reference.
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