CURRENT SOURCE OF MAGNETIC RANDOM ACCESS MEMORY

Abstract

A current source for magnetic random access memory (MRAM) is provided, including a band-gap reference circuit, a first stage buffer, and a plurality of second stage buffers. The band-gap reference circuit provides an output reference voltage which is locked by the first stage buffer. The plurality of second stage buffers generate a stable voltage in response to the locked voltage, so as to provide a current for the conducting wire after being converted, such that magnetic memory cell changes its memory state in response to the current. The current source may reduce the discharge time under the operation of biphase current, so as to raise the operating speed. Further, the circuit area of the current source for the MRAM is also reduced. The operation of multiple write wires may be provided simultaneously to achieve parallel write.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention will become more fully understood from the detailed description given herein below for illustration only, and which thus is not limitative of the present invention, and wherein:

FIG. 1 is a circuit diagram of the current source for the MRAM provided by the prior art;

FIG. 2 is an architectural view of the current source for the MRAM provided by the present invention;

FIG. 3 is a circuit diagram of one embodiment of the band-gap reference circuit in the current source for the MRAM provided by the present invention;

FIG. 4 is a circuit diagram of another embodiment of the band-gap reference circuit in the current source for the MRAM provided by the present invention;

FIG. 5 is a diagram of the operating principle of the current source for the MRAM provided by the present invention; and

FIG. 6 is a diagram of one embodiment of the memory adapted to the current source for the MRAM provided by the present invention.

Claims

1. A current source of magnetic random access memory (MRAM), which comprising: a band-gap reference circuit, for providing a reference voltage;a first stage buffer, connected to the band-gap reference circuit, for locking the reference voltage output by the band-gap reference circuit; anda plurality of second stage buffers, for generating a stable voltage in response to the locked reference voltage, so as to provide a current for a conducting wire after being converted.

2. The current source as claimed in claim 1, wherein each second stage buffer comprises two electrically interconnected switches both controllably switched between a voltage source and a ground end.

3. The current source as claimed in claim 1, wherein the first stage buffer is a unit-gain buffer amplifier.

4. The current source as claimed in claim 1, wherein the band-gap reference circuit at least comprises: a voltage regulator; andan output reference current circuit, connected to the voltage regulator.

5. The current source as claimed in claim 4, wherein the output reference current circuit comprises an amplifier.

6. The current source as claimed in claim 4, wherein the voltage regulator is a resistor.

7. The current source as claimed in claim 1, wherein the band-gap reference circuit comprises: a plurality of resistors connected in series;a plurality of metal-oxide-semiconductor field effect transistors (MOSFET), wherein the source of each MOSFET is connected between each two adjacent resistors; andan output reference current circuit, connected to an end of the plurality of resistors connected in series.

8. The current source as claimed in claim 7, wherein the output reference current circuit comprises an amplifier.

9. A magnetic random access memory (MRAM), comprising: a band-gap reference circuit, for providing a reference voltage;a first stage buffer, connected to the band-gap reference circuit, for locking the reference voltage output by the band-gap reference circuit;a plurality of second stage buffers, for generating a stable voltage in response to the locked reference voltage, so as to provide a current for a conducting wire after being converted; anda magnetic memory cell with its memory state changed in response to the current.

10. The MRAM as claimed in claim 9, wherein each second stage buffer comprises two electrically interconnected switches controllably switched between a voltage source and a ground end.

11. The MRAM as claimed in claim 9, wherein the first stage buffer is a unit-gain buffer amplifier.

12. The MRAM as claimed in claim 9, wherein the band-gap reference circuit at least comprises: a voltage regulator; andan output reference current circuit, connected to the voltage regulator.

13. The MRAM as claimed in claim 12, wherein the output reference current circuit comprises an amplifier.

14. The MRAM as claimed in claim 12, wherein the voltage regulator is a resistor.

15. The MRAM as claimed in claim 9, wherein the band-gap reference circuit comprises: a plurality of resistors connected in series;a plurality of MOSFETs, wherein the source of each MOSFET is connected between each two adjacent resistors; andan output reference current circuit, connected to an end of the plurality of resistors connected in series.

16. The MRAM as claimed in claim 15, wherein the output reference current circuit comprises an amplifier.