Patent Application
20050204255
The present invention relates to Turbo Product Code (TPC). More particularly, the present invention relates to TPC decoding techniques.
Turbo code using iterative decoding algorithms has been shown to give a significant performance advantage over existing partial response maximum likelihood (PRML) channels. Turbo Product Code (TPC) with single parity check (TPC/SPC), which belongs to a family of turbo codes, presents the potential for less complex implementations with minimal performance losses. See for example J. Li, K. R. Narayanan, E. Kurtas, and C. N. Georghiades, “On the Performance of High-Rate TPC/SPC Codes and LDPC codes over Partial Response Channels”, IEEE Trans. Commun., Vol. 50, pages 723-734, May 2002. TPC generally utilizes “square” code words (i.e., code words having the same number of rows and columns of bits), with each code word being comprised of square code blocks. An example of a 512 byte (4,096 bit) TPC code word is a code word having four 32 bits by 32 bits code blocks.
When using a TPC (such as a TPC/SPC) to encode data for transmission or storage, it is common to utilize a soft decision algorithm in conjunction with the TPC decoder to iteratively decode the data. Examples of soft decision algorithms include Soft Output Viterbi Algorithms (SOVAs) and Bahl, Cocke, Jelinek, and Raviv (BCJR) algorithms. As the decoding process advances, message data is passed iteratively between the soft decision algorithm and the TPC decoder. The message data can include, for example, all of the code blocks of the code word being decoded, along with probability data and the like. When using soft decision algorithms such as a SOVA, the probability data typically takes the form of log-likelihood values for the various bits of the code word. With each additional iteration, the error rate is typically improved. However, increased iterations come at the expense of increased power dissipation, hardware complexity and data latency.
Embodiments of the present invention provide solutions to these and/or other problems, and offer other advantages over the prior art.
A method of decoding a turbo product code (TPC) code word comprises performing a cyclic redundancy check (CRC) on each of a plurality of code blocks of the TPC code word. The bits of code blocks of the TPC code word which pass the CRC are assigned an artificially high probability confidence measure, such as an artificially high log-likelihood ratio. Assigning these bits an artificially high probability confidence measure allows an iterative process, between a soft decision algorithm and a TPC decoder, to be less complex and to converge on a correct decoding solution more quickly. Apparatus for implementing the method are also provided.
In some embodiments, iteratively decoding the TPC code word comprises iteratively decoding the TPC code word using a soft decision algorithm such as a soft output viterbi algorithm (SOVA) or a Bahl, Cocke, Jelinek, and Raviv (BCJR) algorithm and a TPC decoder. Also, in some embodiments, the TPC code word is a single parity check TPC code word (TPC/SPC).
In some embodiments, the step of performing the CRC on each of the plurality of code blocks further comprises performing the CRC on each of the plurality of code blocks during a first iteration between the soft decision algorithm and the TPC decoder. Performing the CRC on each of the plurality of code blocks during the first iteration between the soft decision algorithm and the TPC decoder can further comprise performing the CRC on each of the code blocks after decoding using the TPC decoder and before the corresponding probability confidence measures represented by the extrinsic information from the plurality of code blocks are sent back to the soft decision algorithm.
In some embodiments, performing the CRC on each of the plurality of code blocks further comprises performing the CRC on each of the plurality of code blocks during each of a plurality of iterations between the soft decision algorithm and the TPC decoder. In these embodiments, assigning the artificially high probability confidence measure to bits of any of the plurality of code blocks which pass the CRC further comprises assigning the artificially high probability confidence measure to bits of each code block which passes the CRC during the iteration in which the code block passes the CRC.
Other features and benefits that characterize embodiments of the present invention will be apparent upon reading the following detailed description and review of the associated drawings.
Referring to
Disc drive 100 includes a housing with a base 102 and a top cover (not shown). Disc drive 100 further includes a disc pack 106, which is mounted on a spindle motor (not shown), by a disc clamp 108. Disc pack 106 includes a plurality of individual discs, which are mounted for co-rotation about central axis 109. Each disc surface has an associated disc head slider 110 which is mounted to disc drive 100 for communication with the disc surface. Sliders 110 support MR heads for reading data from the disc surface. The MR heads include MR readers or sensors, or in the alternative, the MR heads can be considered to be the MR readers.
In the example shown in
The methods of the present invention are practiced, for example, in channel circuitry (diagrammatically included within electronics 128) of disc drive 100. As noted previously, while disc drive 100 is shown in
Each code block 200 can include P1 columns of parity bits and P2 rows of parity bits. When TPC code word 220 is a two-dimensional turbo product code based on a single parity check (TPC/SPC), then P1=P2=1, resulting in the overall dimensions of each code block being N1=N2=33. The resulting code rate in this example is 0.94. The four code blocks 200-1 through 200-4 are concatenated and interleaved to produce one TPC/SPC code word. The code word length is 4,096 user bits (4*32*32=4,096) or 4,356 channel bits (4*33*33=4,356).
The acronym “CRC” defined as being a “Cyclic Redundancy Check” is also frequently used in the art to denote a “Cyclic Redundancy Code.” Used in this manner, the “Cyclic Redundancy Check” can be referred to as a “Cyclic Redundancy Code check” or a “CRC check.” When adding CRC bits to a TPC (for example a TPC/SPC) code word, any addition of CRC bits has to occur before the insertion of the rows and columns P1 and P2 of parity bits in order to obtain the protection from the TPC. In other words, CRC bits must also be added before the TPC encoding. Further, with the addition of a few CRC bits, the potential exists for the remaining user data space to be less than the dictated user data sector length (for example 512 bytes in typical data storage systems) and the code block length required in the TPC. These same implementation issues also occur with the addition of ECC bits.
As seen in
Referring now to
As shown in
The TPC/SPC encoded user data and ECC/CRC data bits are then provided to interleaver block or circuitry 415 which scrambles the locations (order) of the bits of the code blocks which make up the code word. The interleaved code word is then provided to precoder 420 which precodes the code word using any of a variety of well-known techniques which aid in avoiding error propagation. The interleaved and precoded bits are then provided to storage medium or transmission medium 425. In embodiments in which the present invention is used in a data storage system, storage medium 425 can be a data storage disc or other storage medium on which the TPC/SPC encoded data is stored. In order to store the encoded data on the storage medium, and in order to retrieve the stored encoded data from the storage medium, block 425 in
During read back or receipt of the encoded data, an electrical signal indicative of the encoded data is generated and provided to equalizer 430 for conversion to a specific desired spectrum or target shape. In the equalizer circuit or block 430, the signal can be sampled at a baud rate, with the sampled values sent to the soft decision algorithm implementing block or circuitry 440 of iterative decoder 435. In exemplary embodiments, the invention is described with reference to the soft decision algorithm being a Soft Output Viterbi Algorithm (SOVA). However, the present invention is not limited to use with a SOVA, but rather applies to iterative decoding between a soft decision algorithm (such as a SOVA or a BCJR algorithm) and a TPC decoder.
As is well known in the art, SOVA (or soft decision algorithm) 440 is a sequence detector which considers not only the value of a current bit, but also the values of entire sequences of bits. Generally speaking, the SOVA considers which of multiple possible sequences is the maximum likelihood sequence corresponding to a particular encoded bit stream. Thus, the SOVA outputs with (or associates with) each possible sequence a probability of that sequence (and of the particular bits in that sequence) being correct. These probabilities are typically in the form of path metric distances in the Viterbi trellis. This information is provided through de-interleaver 445 to TPC/SPC decoder 450.
TPC/SPC decoder 450 places all of the de-interleaved bits into the code blocks of the code word, using the probabilities of whether each bit of the code blocks are ones or zeros to minimize errors in the decoding process. In a conventional format, the TPC decoder 450 redefines the probability for each of these bits being a one or a zero based on the row and the column parity checks, and passes this extrinsic information (new probability information added on by TPC) back to the SOVA 440 through interleaver circuitry 455 for the SOVA to re-process the data. This process can be repeated a number of times to perform multiple iterations. The more iterations between the TPC decoder and the SOVA (or other soft decision algorithm) which are performed, the lower the resulting error rate in the code word. However, as the number of iterations performed increases using conventional methods, increases in power dissipation, hardware complexity requirements and data latency also result. The present invention improves the efficiency of this iterative process, thereby providing one or more of reduced processing requirements, reduced power consumption, and reduced data latency.
In order to improve the efficiency of the iterative process, in accordance with the invention after each iteration between the SOVA or soft decision algorithm 440 and TPC decoder 450, a cyclic redundancy code check (CRC check) is performed on each of the individual code blocks 210 of the code word 220/300 by CRC decoder 460. CRC decoder 460 then passes the results of the CRC check back to TPC decoder 450. For any bits which have passed the CRC check, TPC decoder 450 re-assigns those bits artificially large log-likelihood values (or other probability confidence measures). In other words, for any code block of the code word which passes the CRC check, the log-likelihood values associated with the bits of that code block are assigned a probability confidence measure indicative of a very high confidence that these bits are correctly decoded.
After re-assigning the log-likelihood values for the bits of code blocks which pass the CRC check, this extrinsic information is passed back to SOVA or soft decision algorithm 440 (via interleaver 455) in additional iterations. It should be understood that references herein made to passing or sending probability confidence measures from the TPC decoder to the SOVA are intended to include the passing of the extrinsic information representative of the probability confidence measures. Since SOVA 440 can readily determine that the bits of the code blocks which passed the CRC check are correct, the SOVA need not change the values of these bits and the SOVA processing steps associated with the bits in these code blocks can be reduced or eliminated in future iterations. Also, having one or more of the code blocks assigned artificially high log-likelihood values allows SOVA 440 to converge more quickly and with less computations in each iteration since it can safely assume that the code blocks assigned artificially high log-likelihood values are correctly decoded. Further, when assigning the artificially high log-likelihood values to code blocks which have passed a CRC, these code blocks can also be waived from additional decoding or parity check computations (typically implemented within decoder 450) in subsequent iterations. This further fine tunes the message passing at the code block level, as opposed to the code word level, to reduce the number of iterations and improve the bit error rate (BER) performance. It is also not necessary to repeat the CRC on code blocks which have passed a CRC in a previous iteration.
After the iterative decoding is terminated, the decoded data can optionally be provided to an ECC decoder 465. ECC decoder 465 is not required in all embodiments because the number of error bits after the iterative decoding process will be minimal if each of the code blocks of the code word pass their respective CRC checks. However, in other embodiments, inclusion of ECC decoder 465 is desirable, particularly if different termination criteria are used. For example, if a predetermined maximum number of iterations is used to terminate the iterative process in the event that the CRC equations are not satisfied, inclusion of ECC decoder 465 to correct remaining errors can still be beneficial. As will be understood, if ECC decoder 465 is not included, then ECC bits need not be added to the code words prior to encoding.
Referring now to
As shown in
In contrast, consider the code word iteratively decoded using the code block CRC check of the present invention. As illustrated in
In the example shown, when creating the CRC, after input bits of “1010001101”, the bits “00000” are appended at the end of the input stream to flush out the content of the register. The content of the register is then “01110”. When checking the CRC, the input stream “101000110101110” is fed into the shift register. If the contents of the register after the sequence has passed through the register is then “00000”, the CRC equation is satisfied, and the data has been decoded properly.
Referring now to
In operation, SOVA or soft decision algorithm 740 initially processes all code blocks of the code word as discussed above with reference to
After setting the probability confidence measures for the bits of the code words which pass the CRC check, the extrinsic information is passed back to the soft decision algorithm via interleaver 755 for a subsequent iteration. With the bits of some code blocks assigned the artificially high log-likelihood ratios, the processing implemented by SOVA 740 can be reduced significantly.
Referring back to
Referring now to
The results of the CRC check on the code block being processed are provided at 811 to finite state machine 815 which uses the results to generate a control parameter or signal 816 for controlling which of its two inputs multiplexer 825 provides at output 826. Output 826 of multiplexer 825 is coupled to interleaver 455/755 shown in
Referring also to
It is to be understood that even though numerous characteristics and advantages of various embodiments of the invention have been set forth in the foregoing description, together with details of the structure and function of various embodiments of the invention, this disclosure is illustrative only, and changes may be made in detail, especially in matters of structure and arrangement of parts within the principles of the present invention to the full extent indicated by the broad general meaning of the terms in which the appended claims are expressed. For example, the particular elements may vary depending on the particular application for the decoding systems while maintaining substantially the same functionality without departing from the scope and spirit of the present invention. In addition, although the embodiment described herein is primarily described with reference to a data storage system, it will be appreciated by those skilled in the art that the teachings of the present invention can be applied to communication and other systems, without departing from the scope and spirit of the present invention.
