Claims
- 1. An integrated circuit, comprising:a conductive plug having a top surface and a cavity, said cavity having a lower surface and side surfaces; wherein a plug is disposed in a dielectric layer having an upper surface and said plug has a top surface substantially coplanar with said upper surface of said dielectric layer; a layer of dielectric material disposed on said lower surface, said side surfaces and at least a portion of said top surface; and a conductive layer disposed on said dielectric layer.
- 2. An integrated circuit as recited in claim 1, wherein said layer of dielectric material is selected from the group consisting of tantalum pentoxide, silicon oxide, titanium oxide and barium strontium titinate.
- 3. An integrated circuit as recited in claim 1, wherein said plug is tungsten.
- 4. An integrated circuit as recited in claim 1, wherein said layer of dielectric material is selected from the group consisting of tantalum oxide, silicon oxide, titanium oxide and barium strontium titinate.
- 5. An integrated circuit as recited in claim 1, wherein said plug is tungsten.
- 6. An integrated circuit as recited in claim 1, wherein said plug is partially disposed in a dielectric layer.
- 7. An integrated circuit, comprising:a conductive plug having a top surface, and a cavity, said cavity having side surfaces and said plug being disposed in a dielectric layer of the integrated circuit; a layer of dielectric material disposed on said side surfaces of said cavity and at least a portion of said top surface; and a conductive layer disposed on said dielectric layer; wherein said conductive layer is selected from the group consisting of titanium nitride, tantalum nitride, tungsten nitride.
- 8. An integrated circuit as recited in claim 7, wherein said cavity has a lower surface and said layer of dielectric material and said conductive layer are further disposed on said lower surface.
- 9. An integrated circuit as recited in claim 7, wherein said layer of dielectric material is selected from the group consisting of tantalum oxide, silicon oxide, titanium oxide and barium strontium titinate.
- 10. An integrated circuit as recited in claim 7, wherein said conductive plug further comprises at least one outer surface, and said layer of dielectric material is further disposed on at least a portion of said at least one outer surface.
- 11. An integrated circuit as recited in claim 7, wherein said conductive plug further comprises at least one outer surface, and said layer of dielectric material is further disposed on at least a portion of said at least one outer surface.
- 12. An integrated circuit as recited in claim 7, wherein said plug is tungsten.
- 13. An integrated circuit, comprising:a conductive plug having a top surface and a cavity, said cavity having side surfaces and at least one outer surface; a layer of dielectric material is disposed on said side surfaces of said cavity, and at least a portion of said top surface and at least a portion of said at least one outer surface of said plug; and a conductive layer disposed on said layer of dielectric material; wherein said conductive layer is selected from the group consisting of titanium nitride, tantalum nitride, tungsten nitride.
- 14. An integrated circuit as recited in claim 13, wherein said cavity has a lower surface and said layer of dielectric material and said conductive layer are further disposed on said lower surface.
- 15. An integrated circuit as recited in claim 13, wherein said layer of dielectric material is selected from the group consisting of tantalum oxide, silicon oxide, titanium oxide, and barium strontium titinate.
- 16. An integrated circuit as recited in claim 13, wherein said plug is tungsten.
- 17. An integrated circuit comprising:a conductive plug having a top surface and a cavity, said cavity having side surfaces and at least one outer surface; a layer of dielectric material is disposed on said side surfaces of said cavity, and at least a portion of said top surface and at least a portion of said at least one outer surface of said plug; and a conductive layer disposed on said layer of dielectric material; wherein said plug is disposed in a dielectric layer having an upper surface and said top surface of said plug is substantially coplanar with said upper surface of said dielectric layer.
- 18. An integrated circuit as recited in claim 17, wherein said cavity has a lower surface and said layer of dielectric material and said conductive layer are further disposed on said lower surface.
- 19. An integrated circuit as recited in claim 17, wherein said layer of dielectric material is selected from the group consisting of tantalum oxide, silicon oxide, titanium oxide, and barium strontium titanate.
- 20. An integrated circuit as recited in claim 17, wherein said plug is tungsten.
CROSS-REFERENCE TO RELATED APPLICATION
This application claims priority of Provisional Application Serial No. 60/115,520 which was filed on Jan. 12, 1999.
US Referenced Citations (9)
Foreign Referenced Citations (1)
Number |
Date |
Country |
11-26461 |
Jan 1999 |
JP |
Non-Patent Literature Citations (1)
Entry |
“Stacked High-ε Gate Dielectric For Gigascale Integrateion Of Metal-Oxide-Semiconductor Techniques,” P.K. Roy et al., Applied Physics Letters, vol. 72, No. 22, Jun. 1998, pp. 2835-2837. |
Provisional Applications (1)
|
Number |
Date |
Country |
|
60/115520 |
Jan 1999 |
US |