Claims
- 1. A circuit comprising:
a data-path circuit configured to (i) independently shift each of a plurality of data items and (ii) multiplex said plurality of data items after said shift to present an output data item.
- 2. The circuit according to claim 1, wherein said data-path circuit is further configured to multiplex said plurality of data items to present a second output data item.
- 3. The circuit according to claim 1, wherein said data-path circuit is further configured to:
buffer a cache write data item to present a buffered data item; and multiplex said cache write data item with said buffered data item to present a cache input data item.
- 4. The circuit according to claim 3, wherein said data-path circuit is further configured to multiplex said buffered data item with said plurality of data items prior to said shift.
- 5. The circuit according to claim 3, wherein said data-path circuit is further configured to multiplex an input data item with a predetermined one of said plurality of data items prior to said shift.
- 6. The circuit according to claim 3, wherein said data-path circuit is further configured to present said cache write data item as a second output data item. ,
- 7. The circuit according to claim 3, wherein said data-path circuit is further configured to:
buffer a write data item to present a buffered write data item; multiplex said buffered write data item with an input data item to present said cache write data item; and multiplex said write data item with said cache write data item and said buffered data item to present said cache input data item.
- 8. The circuit according to claim 7, wherein said data-path circuit is further configured to multiplex a second input data item with said buffered write data item and said input data item to present said cache write data item.
- 9. The circuit according to claim 3, wherein said data-path circuit is further configured to:
multiplex said buffered data item with said plurality of data items prior to said shift; buffer a write data item to present a buffered write data item; multiplex said buffered write data item with an input data item and a second input data item to present said cache write data item; multiplex said write data item with said cache write data item and said buffered data item to present said cache input data item; multiplex a third input data item and said cache write data item with a predetermined one of said plurality of data items prior to said shift; present said cache write data item as a second output data item; and multiplex said plurality of data items to present a third output data item.
- 10. The circuit according to claim 1, wherein said data-path circuit comprises:
a plurality of load aligners configured to shift said plurality of data items.
- 11. The circuit according to claim 1, further comprising:
a first data bus configured to route said output data item; and a second data bus configured to route cache write data items.
- 12. A method for improving a data transfer delay for a cache memory comprising the steps of:
(A) independently shifting each of a plurality of cache output data items from said cache memory; and (B) multiplexing said plurality of cache output data items in response to step (A) to present an output data item.
- 13. The method according to claim 12, further comprising the step of:
multiplexing said plurality of cache output data items prior to step (A) to present a second output data item.
- 14. The method according to claim 12, further comprising the steps of:
buffering a cache write data item to present a buffered data item; and multiplexing said cache write data item with said buffered data item to present said cache input data item.
- 15. The method according to claim 14, further comprising the step of:
multiplexing said buffered data item with said plurality of cache output data items prior to step (A).
- 16. The method according to claim 14, further comprising the step of:
multiplexing an input data item with a predetermined one of said plurality of cache output data items prior to step (A).
- 17. The method according to claim 14, further comprising the step of:
presenting said cache write data item as a second output data item.
- 18. The method according to claim 14, further comprising the steps of:
buffering a write data item to present a buffered write data item; multiplexing said buffered write data item with an input data item to present said cache write data item; and multiplexing said write data item with said cache write data item and said buffered data item to present said cache input data item.
- 19. The method according to claim 18, further comprising the step of:
multiplexing a second input data item with said buffered write data item and said input data item to present said cache write data item.
- 20. A circuit comprising:
means for independently shifting each of a plurality of data items from a plurality of sources; and means for multiplexing said plurality of data items to present an output data item in response to said means for independently shifting.
Parent Case Info
[0001] This is a continuation of U.S. Ser. No. 09/731,476, filed Dec. 6, 2000.
Continuations (1)
|
Number |
Date |
Country |
Parent |
09731476 |
Dec 2000 |
US |
Child |
10405839 |
Apr 2003 |
US |