Claims
- 1. A data delay/memory circuit for an integrated circuit (IC) comprising:
- a plurality of data shift circuits, each formed of a plurality of clock-controlled data latch circuits which are cascade-connected in a data transfer direction from an initial stage data latch circuit to a final stage data latch circuit, said data shift circuits being arranged in parallel in the IC and parallel to the data transfer direction; and
- means for supplying each of the plurality of data latch circuits of each of said data shift circuits with clock signals having more than four different individual clocked phases and being sequentially generated for providing the clocking phase for each of the final stage data latch circuits to said final stage before the clocking phase for each of the initial stage data latch circuits, said supplying means including wirings, formed in said IC across the data transfer direction, for feeding said clock signals to said data latch circuits.
- 2. A data delay/memory circuit according to claim 1 wherein each of said data latch circuits includes a clocked inverter.
- 3. A digital data delay/memory circuit comprising:
- a plurality of data delay/memory circuits each being formed of at least three clock-controlled and cascade-connected data latch circuits, each of which data latch circuits stores and outputs digital data, one of which data latch circuits constitutes an initial stage of the respective data delay/memory circuit and the input of said one data latch circuit is the input terminal of the respective data delay/memory circuit, and another of which data latch circuits, coupled to said one data latch circuit via remaining data latch circuits, constitutes a final stage of the respective data delay/memory circuit and the output of said another data latch circuit is the output terminal of the respective data delay/memory circuit;
- means for supplying each of said plurality of data latch circuits with clock signals having more than four different individual clocking phases and being sequentially generated for providing the clocking phase for the final stage of each of said data delay/memory circuits to said final stage before the clocking phase for the initial stage of each of said data delay/memory circuits, all said data latch circuits being continuously clocked by said clock signals in the order from said final stage through said initial stage of said data delay/memory circuits;
- serial/parallel converter means, coupled to the input terminals of said data delay/memory circuits and responsive to digital data delay/memory circuit serial input data, for supplying the respective input terminals of said data delay/memory circuits with first data, the first data for each of said respective input terminals having a different phase with respect to said serial input data; and
- parallel/serial converter means, coupled to the output terminals of said data delay/memory circuits, for converting second data delivered from the respective output terminals of said data delay/memory circuits into digital delay data/memory circuit serial output data.
- 4. A data delay/memory circuit according to claim 3, wherein each of said serial/parallel converter means and said parallel/serial converter means is controlled by a master clock signal and formed of a plurality of cascade-connected data delay circuits.
- 5. A data delay/memory circuit according to claim 3, wherein each delay time of the respective signals in said plural data delay/memory circuits, which are associated with said serial/parallel converter means and said parallel/serial converter means, is set at a prescribed length of time.
Priority Claims (1)
| Number |
Date |
Country |
Kind |
| 59-165132 |
Aug 1984 |
JPX |
|
SUMMARY OF THE INVENTION
This application is a continuation of application Ser. No. 761,708, filed Aug. 2, 1985, now abandoned.
BACKGROUND OF THE INVENTION
The present invention relates to a data delay/memory circuit which memorizes input data for a given period of time and, thereafter, outputs the memorized data.
Signal processing for temporary memorizing and delaying a digital signal is conventionally effected in a digital 1H memory which delays by one horizontal period of time (1H) a horizontal video signal of a digital TV, in a digital filter, in a deinterleave circuit of a compact disc player, or in the like.
In a prior art data delay/memory circuit used for the above exemplified applications, a plurality of cascade-connected one-bit shift registers are conventionally adapted. The number of the cascade connections depends on the circuit design. Each of these one-bit shift registers comprises a pair of clocked inverters for latching input data. One clocked inverter of the pair operates in synchronism with a clock signal, while the other clocked inverter operates in synchronism with an antiphase clock signal. According to such a prior art data delay/memory circuit, a one bit shift register is inevitably provided for storing each one bit data. Consequently, the necessary number of the data latching, clocked inverters has to be twice the number of the one bit shift registers. If a 1H memory of a digital TV which requires a large memory capacity of, e.g., 1135 bits is constituted by such a data delay/memory circuit, the number of circuit elements becomes numerous. For this reason, when such a data delay/memory circuit is circuit-integrated, a prominently large chip size is required, resulting in a decrease of the yield of IC manufacture while increasing the cost thereof.
It is, accordingly, an object of the present invention to provide a data delay/memory circuit which allows for a decrease in the necessary number of circuit elements for one bit, thereby reducing the size of the IC chip and improving the yield of IC manufacture.
To achieve the above object, the present invention employs a data shift circuit formed with a plurality of multiply or serially cascade-connected data latch circuits, the plural data latch circuits being controlled by different clock signals. These clock signals have individual clocking phases and are sequentially generated in such a manner that the clocking phase for a final stage of the data latch circuits is ahead of that for an initial stage thereof. According to the present invention, (N+1) data latch circuits satisfactorily constitute an N bit data delay/memory circuit.
According to the present invention, the necessary number of circuit elements per one bit can be effectively decreased, thereby reducing the chip size of the IC and lowering the manufacturing cost.
US Referenced Citations (11)
Foreign Referenced Citations (3)
| Number |
Date |
Country |
| 55-129912 |
Oct 1980 |
JPX |
| 59-63093 |
Apr 1984 |
JPX |
| 0607697 |
Jan 1985 |
JPX |
Non-Patent Literature Citations (3)
| Entry |
| IBM Technical Disclosure Bulletin, vol. 12, No. 12, May 1970, pp. 2144-2145, "Complementary FET Shift Register Using a Single Phase Line", by Gaemssler. |
| The Electronic Engineer, Mar. 1970, pp. 59-61, "MOS Shift Registers", by George Landers. |
| Patent Abstracts of Japan, vol. 8, No. 248 (P-313) [1685], Nov. 14, 1984 concerning Japanese Patent Document No. 59-119594 (Kimura). |
Continuations (1)
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Number |
Date |
Country |
| Parent |
761708 |
Aug 1985 |
|
Patent Grant
4802136
