This application claims the priority of Chinese Patent Application No. 201710300592.2, entitled “Data Driver and Display Panel”, filed on Apr. 27, 2017, the disclosure of which is incorporated herein by reference in its entirety.
The present invention relates to the field of display, and in particular to the field of data driver and display panel.
The display panel has been widely applied to display devices of various fields, such as, computers, mobile phone and TV.
The display panel uses the data driver to supply the image data signal to the pixel unit in the display panel through the data line, and the scan driver controls the corresponding pixel through the scan line when to receive the data signal so as to display the image signal to obtain the image to be displayed. However, in the actual use, the display panel often shows inconsistent image display at the two ends on the display panel; that is, the image displayed on the opposite ends of the display panel will show color differences, resulting in poor image display performance.
To solve the above problem, the present invention provides a data driver with better performance of display driving result.
Furthermore, the present invention also provides a display panel with the above data driver.
The present invention provides a data driver, applicable to providing image data to be displayed to a plurality of data lines. The data driver comprises: a data processing unit, a driving unit, and at least two sets of data outputs. The data processing unit is configured to receive and store one frame of image data to be displayed. The driving unit is to output at least two sets of data voltages having different driving capacities according to the image data. Each of the at least two sets of data outputs comprises a plurality of data outputs, and each set is connected to pixels in two areas with a different distance from the data driver. The driving unit provides the at least two sets of data voltages having different driving capabilities to the at least two sets of data outputs.
A display panel comprises: an active area and a plurality of data lines arranged with a distance apart along a first direction. The active area extends in a plane along mutually perpendicular first and second directions, and the active area defines at least two active sub-areas in the second direction. The data lines extend along the second direction and are disposed independently at the at least two active sub-areas. The data driver is provided at one end of the data lines in the second direction for providing a data voltage for image display for the data lines, and the at least two active sub-areas and the data driver are spaced apart with different distances.
Compared with the prior art, the data driver respectively supplies the data voltages having different driving capabilities so that the pixels of the display panel with different distance from the data driver can obtain the data voltage with corresponding driving capability; thus, the display panel can display the consistently and uniformly to achieve better display result.
To make the technical solution of the embodiments according to the present invention, a brief description of the drawings that are necessary for the illustration of the embodiments will be given as follows. Apparently, the drawings described below show only example embodiments of the present invention and for those having ordinary skills in the art, other drawings may be easily obtained from these drawings without paying any creative effort.
To further explain the technical means and effect of the present invention, the following refers to embodiments and drawings for detailed description. Apparently, the described embodiments are merely some embodiments of the present invention, instead of all embodiments. All other embodiments based on embodiments in the present invention and obtained by those skilled in the art without departing from the creative work of the present invention are within the scope of the present invention.
Refer to
Specifically, a plurality of data lines Di-Dj are arranged in parallel with each other with a predetermined distance apart and mutually insulated along a first direction X. The plurality of scan lines Gx-Gy are arranged in parallel with each other with a predetermined distance apart and mutually insulated along a second direction Y. Wherein the first direction X and the second direction Y are perpendicular to each other, and 1≤i<j, 1≤x<y, i, j, x and y are natural numbers. The plurality of data lines Di-Dj and the plurality of scan lines Gx-Gy form an array region in which the pixels Px are located in the array region and are electrically connected to the corresponding data lines and scan lines, respectively. Wherein, the first direction X and the second direction Y are perpendicular to each other.
The data driver 12 is disposed at one end of the plurality of data lines Di-Dj, wherein the data driver 12 comprises a plurality of data outputs Pi, with each data output Pi correspondingly connected to a data line Di, for outputting a data signal to the corresponding data line Di.
Correspondingly, the scan driver (not shown) is disposed at one end of the plurality of scan lines Gxi-Gy, wherein the scan driver comprises a plurality of scan outputs, with each scan output correspondingly connected to a scan line Gx, for outputting a data signal to the corresponding scan line Gx.
When the display panel 10 performs image display, the scan driver sequentially transmits the scan signals to the scan lines Gx, Gx+1, . . . Gy, along the second direction Y, that is, scanning sequentially; in the mean time, when the scan driver provides a scan signal to one of the scan lines Gx, the data driver 12 simultaneously provides data lines Di, Di+1, . . . , Dj with a data signal of the image to be displayed. Thus, the data line and the scan line must cooperate to load the image signal into the pixel electrode of the pixel Px. The pixel electrode cooperates with a common voltage to generate an electric field to drive the liquid crystal (LC) molecules to produce a corresponding rotation angle, thereby achieving displaying the image signal.
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The display panel 10 comprises a timing control circuit 11, a data driver 12, and a scan driver 13; wherein, the scan driver 13 is disposed at the non-active area 10b on a side of the active area 10a along the first direction X; and the data driver 12 is disposed at the non-active area 10b on a side of the active area 10a along the second direction Y. The timing control circuit 11 can be disposed at the non-active area 10b of the display panel 10 or at other circuit board independent of the display panel 10.
The data driver 12 is for providing image data to be displayed to the pixels 101 in the active area 10a, and uses the plurality of data lines 120 to transmit in a form of data voltage to the pixels 101. The scan driver 13 is electrically connected to the plurality of scan lines 130, for controlling through the plurality of scan lines 130 the pixels 101 when to receive the image data for image display. The timing control circuit 11 is electrically connected to the data driver 12 and scan driver 13 respectively, for controlling the operation timing of the data driver 12 and the scan driver 13, i.e., outputting corresponding timing control signals to the data driver 12 and the scan driver 13.
Moreover, the active area 10a is divided into three areas along the second direction Y the three areas are defined as a first active area AA1, a second active area AA2, and a third active area AA3. The first active area AA1 is spaced apart from the data driver 12 with a first distance L1, the second active area AA2 is spaced apart from the data driver 12 with a second distance L2, and the third active area AA3 is spaced apart from the data driver 12 with a third distance L3. The first distance L1 is less than the second distance L2, and the second distance L2 is less than the third distance L3. In other words, the distance from the data driver 12 in the second distance Y increases from the first active area AA1, the second active area AA2 to the third active area AA3.
The first active area AA1, the second active area AA2 and the third active area AA3 mutually independently obtain the data voltage of the image signal from the data driver 12, i.e., the first active area AA1, the second active area AA2 and the third active area AA3 mutually independently obtain data voltage from the data output Pi of the data driver 12. In other words, the data voltage outputted from the data driver 12 is independently provided to the first active area AA1, the second active area AA2 and the third active area AA3 so that the data voltage does not need to propagate from the pixels 101 closer to the data driver 12 to the pixels 101 farther from the data driver 12.
Because the first active area AA1, the second active area AA2 and the third active area AA3 mutually independently obtain data voltage from the data driver 12, the data voltage received by the three areas will be under the same effect of the RC circuit so that the pixels 101 in the entire active area 10a have basically the same data voltage, and leading to a more uniform image display result. As such, the present invention can effectively prevent the data voltage on the data line affected by the RC circuit along the propagation from the pixel 101 close to the data driver 12 to the father pixel 101 to aggregate the distortion.
It should be noted that, in the present embodiment, the display panel 10 is a liquid crystal display (LCD), and each pixel 101 comprises at least a thin film transistor (TFT) as a switch. Therefore, the TFT has a gate electrically connected to the scan line 130, and a source electrically connected to the data line 120. Thus, the data line 120 is also called source line and the scan line 130 is also called gate line. Correspondingly, the data driver 12 is called source driver, and the scan driver 13 is also called gate driver.
It should be understood that the display panel 10 is applied to a display device 100. The display device 100 further comprises other auxiliary circuits to complete image display, such as, graphics processing unit (GPU), power supply circuit, and so on, and the details will not be repeated in the present embodiment.
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Correspondingly, the active area 10a comprises a plurality of m*n pixel 101 arranged in an array, 3m data lines 120, and n scan lines 130, m and n are both natural numbers greater than 1. The plurality of data lines 120 extend along the first direction X and are arranged in parallel with each other with a predetermined distance apart and mutually insulated. The plurality of scan lines 130 extend along the second direction Y and are arranged in parallel with each other with a predetermined distance apart and mutually insulated. The plurality of scan lines 130 and the plurality of data liens 120 are mutually insulated.
The 3m data lines 120 are also divided into three sets, each set comprises m lines, and each set corresponds to an active area. Specifically, the three sets of the data lines 120 are defined as the first data line set 120a, a second data line set 120b and a third data line set 120c. For convenience of explanation, the data lines are denoted as D1-1, D1-2, . . . , D1-m; D2-1, D2-2, . . . , D2-m; D3-1, D3-2, . . . , D3-m, respectively.
Wherein, the first data line set D1-1, D1-2, . . . , D1-m is disposed correspondingly at the first active area AA1, and electrically connecting the first set of data outputs P1-1, . . . , P1-m to the pixels 101 respectively in the active area AA1. The second data line set D2-1, D2-2, . . . , D2-m is disposed correspondingly at the second active area AA2, and electrically connecting the second set of data outputs P2-1, . . . , P2-m to the pixels 101 respectively in the active area AA2. Apparently, the second data line set D2-1, D2-2, . . . , D2-m passes through the first active area AA1 insulated to extend to the second active area AA2 along the second direction Y, and the second data line set D2-1, D2-2, . . . , D2-m do not form electrical connection with any pixels 101 in the first active area AA1. The third data line set D3-1, D3-2, . . . , D3-m is disposed correspondingly at the third active area AA3, and electrically connecting the third set of data outputs P3-1, . . . , P3-m to the pixels 101 respectively in the active area AA3. Apparently, the third data line set D3-1, D3-2, . . . , D3-m passes through the first active area AA1 and the second active area AA2 insulated to extend to the third active area AA3 along the second direction Y, and the third data line set D3-1, D3-2, . . . , D3-m do not form electrical connection with any pixels 101 in the first active area AA1 and the second active area AA2.
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The data driver 12 further comprises: a line buffer 121, a shift register 122, a level shifter 123, a digital-to-analog converter (DAC) 124, a gamma voltage output module 125, an output buffer amplifier 126, and a bias current module 127. For explanation, the line buffer 121, shift register 122, level shifter 123, DAC 124, and gamma voltage output module 125 are used for processing inputted image signal, and are defined as a data processing unit; the output buffer amplifier 126 and bias current module 127 are used for enhancing the driving capability of the image signal, and are defined a driving unit.
Specifically, the line buffer 121 is for buffering the inputted image signal, and outputting the buffered image signal to the shift register 122. The image signal can be RGB video signal.
The shift register 122 is for shifting and locking the image signal outputted by the line buffer 121 under the control of horizontal synchronization signal, and transmitting the locked image signal to the level shifter 123.
The level shifter 123 is for enlarging the voltage of the image signal to activate the DAC 124.
The gamma voltage output module 125 is for outputting a plurality of continuous equal-duration reference voltage signals to the DAC 124, wherein the reference voltage signals comprise a gamma reference voltage signal, at least one of the reference voltage signals further comprising a low voltage signal having a voltage value less than a voltage value of the gamma reference voltage signal, wherein the duration of the reference voltage signal is equal to the duration of the existing gamma reference voltage signal.
The DAC 124 is for, after activation, converting the reference voltage signal to obtain corresponding analog voltage signal, and transmitting the analog voltage signal to the output buffer amplifier 126.
The output buffer amplifier 126 is for amplifying the analog voltage signal to enhance the driving capability to obtain a gray-scale voltage signal. The gray-scale voltage signal is the data signal, and the data signal is transmitted to the corresponding data outputs P1-1, . . . , P3-m. In the present embodiment, the output buffer amplifier 126 comprises a plurality of amplifiers OP, and the number of the amplifiers OP is the same as the number of the data output ends. Correspondingly, the plurality of amplifiers OP are also divided into three sets of amplifiers OP, denoted as the first set of amplifiers OP1-1, . . . , OP1-m; a second set of amplifiers OP2-1, . . . , OP2-m; and a third set of amplifiers OP3-1, . . . , OP3-m.
The bias current module 127 is electrically connected to the output buffer amplifier 126, for outputting a bias current to the output buffer amplifier 126 to control the amplification extent of the output buffer amplifier 126 on the analog voltage signal, i.e., controlling the driving capability of the data signal; wherein, the bias current serves as the driving current for the amplifier to control the driving capability of the data signal by the output buffer amplifier 126.
In the present embodiment, the bias current module 127 comprises three bias current units, and the three bias current units are defined as a first bias current unit 127a, a second bias current unit 127b, and a third bias current unit 127c; wherein the first bias current unit 127a, second bias current unit 127b, and third bias current unit 127c are electrically connected to the three sets of amplifiers respectively and output different bias currents to the three sets of amplifiers. Specifically, the first bias current unit 127a outputs a first bias current, the second bias current unit 127b outputs a second bias current, and the third bias current unit 127c outputs a third bias current; the second bias current is greater than the first bias current, and the third bias current is greater than the second bias current.
The first bias current is provided to the first set of amplifier OP1-1, . . . , OP1-m; the second bias current is provided to the second set of amplifier OP2-1, . . . , OP2-m; and the third bias current is provided to the third set of amplifier OP3-1, . . . , OP3-m. As a result, the amplification power of the first set of amplifier OP1-1, . . . , OP1-m, second set of amplifier OP2-1, . . . , OP2-m, and third set of amplifier OP3-1, . . . , OP3-m increases by that order.
Preferably, the bias current module 127 further comprises a switch unit 128, for controlling the bias current module 127 and output buffer amplifier 126 to conduct or cut off. The switch unit 128 correspondingly comprises three switches: a first switch 128a, a second switch 12b8 and a third switch 128c, respectively; wherein the first switch 128a is electrically connected to the first bias current unit 127a and the first set of amplifiers OP1-1, . . . , OP1-m; the second switch 128b is electrically connected to the second bias current unit 127b and the second set of amplifiers OP2-1, . . . , OP2-m; and the third switch 128c is electrically connected to the third bias current unit 127c and the third set of amplifiers OP3-1, . . . , OP3-m.
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The first set of data outputs P1-1, . . . , P1-m receive the data voltage driven by the first bias current from the first set of amplifiers OP1-1, . . . , OP1-m, and output to the pixels 101 in the first active area AA1 distanced from the data driver 12 with the first distance L1;
The second set of data outputs P2-1, . . . , P2-m receive the data voltage driven by the second bias current from the second set of amplifiers OP2-1, . . . , OP2-m, and output to the pixels 101 in the second active area AA2 distanced from the data driver 12 with the second distance L2;
The third set of data outputs P3-1, . . . , P3-m receive the data voltage driven by the third bias current from the third set of amplifiers OP3-1, . . . , OP3-m, and output to the pixels 101 in the third active area AA3 distanced from the data driver 12 with the third distance L3.
Accordingly, as shown in
Alternatively, the active area 10a can be divided into a plurality of areas depending on the application, such as, two, four, five, or other number of areas.
Refer to
Specifically, as shown in
Therefore, the bias current outputted by the bias current module 227 has a linear relation with the effect by the RC circuit on the data voltage received by the pixels 101 of the active area. Because the bias current module 227 is a linear programmable module, the design of the bias current module 227 is simpler and easier to control.
Embodiments of the present invention have been described, but not intending to impose any unduly constraint to the appended claims. Any modification of equivalent structure or equivalent process made according to the disclosure and drawings of the present invention, or any application thereof, directly or indirectly, to other related fields of technique, is considered encompassed in the scope of protection defined by the clams of the present invention.
Number | Date | Country | Kind |
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201710300592.2 | Apr 2017 | CN | national |
Filing Document | Filing Date | Country | Kind |
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PCT/CN2017/086186 | 5/26/2017 | WO | 00 |