Electrical devices can include many components arranged in a variety of physical arrangements. Describing the physical arrangements, i.e., physical layout or circuit layout, to a computer can often be time consuming. An electrical device can be defined using a complex computer programming language that involves many hours to produce.
In accordance with the present invention, a computer-readable medium having computer-readable instructions for performing a method of forming a model of an electrical device is provided. In accordance with the method, a graphical user interface is generated. A plurality of blocks are made available for selection. The blocks include component blocks and orientation blocks. Each component block represents a component of the electrical device and each orientation block determines the position of a block that is a child to the orientation block relative to other blocks that are children of the orientation block. Selections of a plurality of blocks are received, wherein the selected blocks include a plurality of component blocks and one or more orientation blocks. A display is generated in the graphical user interface using the selected blocks. The display includes graphical representations of the selected component blocks that are arranged in a manner corresponding to the physical arrangement of the components in the electrical device so as to form an overall graphical representation of the electrical device. A metadata text file is generated using the selected blocks. The metadata text file defines a physical layout of the electrical device.
Also provided in accordance with the present invention is a computer-readable medium having computer-readable instructions for performing a method of forming a model of an electrical device. In accordance with the method, a graphical user interface is generated. A plurality of blocks are made available for selection. The blocks include component blocks, segment blocks and node blocks. Each component block represents a component of the electrical device, each segment block represents a subcomponent of one of the components of the electrical device and each node represents an end of one of the components of the electrical device or a junction of a plurality of the components of the electrical device. Selections of a plurality of blocks are received, wherein the selected blocks comprise component blocks, segment blocks and node blocks. A display is generated in the graphical user interface using the selected blocks. The display includes graphical representations of the selected blocks that are arranged in a manner so as to form an overall graphical representation of a circuit layout of the electrical device. A metadata text file is generated using the selected blocks. The metadata text file defines the circuit layout of the electrical device.
The present invention will become apparent to those skilled in the art upon reading this description in conjunction with the accompanying drawings, in which like reference numerals have been used to designate like elements, and in which:
Exemplary embodiments of the present invention are directed to accurately defining and producing an electrical device in a manner which eliminates manual encoding by a programmer using a complex programming language. Methods, systems, and data models are employed to define a physical configuration (i.e., physical characteristics, such as the geometry of a physical layout and/or a circuit layout) of an electrical device. Metadata and a recursive data structure are used to produce a text file according to a metamarkup language, such as Extensible Markup Language (“XML”). Other metamarkup languages can be used to produce a text file.
Electrical devices can include, but are not limited to, capacitors, resistors, coils, switchgear, transformers, and the like. A transformer will be used for purposes of this description, but one of ordinary skill in the art will recognize that the techniques described herein can be extended to many other electrical devices.
A geometrical layout of a cross section of a transformer is shown in
The physical layout of the barriers and windings can be described using a hierarchical data model. The data model includes an abstract component called a block to arrange barriers and windings either horizontally or vertically. A block can be either a horizontal block or a vertical block. A block can also include sub-blocks. For example, in
The physical layout in
The vertical block defines the entire physical layout. The horizontal block 110 defines the middle section of the physical layout between the top and bottom barriers. Because blocks can contain sub-blocks any physical layout can be described using a hierarchical data model. Any metadata created to describe this physical layout must reflect this data model and its hierarchical nature.
A data model for defining a geometry of a physical layout of the electrical device of
The data model includes a metadata element for each block, and a metadata element, referred to herein as a child metadata element, for each sub-block associated with a respective block. The metadata elements are arranged in a hierarchical format. For example, indented under the metadata element <block layout=“horizontal”>are the child metadata elements for barrier B3, winding W1, barrier B4, winding W2, and barrier B5, in that order, as shown in
Initially, the left pane 310 contains only a single block, called “Physical Layout” in
Many methods can be used to add the block identifiers into the left pane of the graphical user interface. For example, a user can right click “Physical Layout” using a computer mouse and a popup menu appears allowing the user to add a barrier, winding or a block. Alternatively, the user can type the block identifiers in using a keyboard. As block identifiers are added in the left pane 310, the blocks are generated and displayed in the right pane 320. For example, the user adds block identifiers for B1330, B2360, and the block 340 to the Physical Layout. Then the user would right click the block 340 and add block identifiers for B3, W1, B4, W2, and B5350.
Once the physical layout is defined, a text file is generated by a computer processor and stored in a computer memory. The user can launch a command with the user interface, e.g., selects a file menu command, to initiate the generation of the text file, or it can be done automatically by the computer processor.
Exemplary functionality which can be performed by the computer processor to draw a physical layout of a transformer coil is embodied in the following pseudocode:
A system for creating a metadata text file corresponding to a physical configuration, such as a geometry of a physical layout, of an electrical device is shown in
The input means 710 can be used to define a geometry of a physical layout of an electrical device as blocks and sub-blocks. The system also includes processor means 720 for processing the physical layout and producing a text file having metadata elements corresponding to the blocks in a hierarchical format, and memory means 730 for storing the text file 740. Display means 760 display a graphical representation of the physical layout of the electrical device. File output means 750 forward the text file to an application for processing. The file output means 750 can output the text file 740 to an application within the same computer 700 or to an application in another computer 790 via a communication network 780, wired or wireless, such as a LAN, the Internet, a WiFi connection, infrared, and the like.
The foregoing describes use of a hierarchical data model to describe a geometry of a physical layout of an electrical device. According to another embodiment, a hierarchical data model can be used to describe a circuit layout of an electrical device. For example,
A hierarchical data model is used to describe a circuit layout. At the top of the hierarchy is the entire circuit layout. At the next level of the hierarchy are windings and circuits. Below windings are the segments and below segments are the start and finish leads. Below circuits are the nodes. Below each node are the nodes' sources and destinations.
A data model for defining a circuit layout of an electrical device as windings, segments, and nodes using a metamarkup language includes a metadata element for each winding and a metadata element, referred to herein as a child metadata element, for each segment associated with a respective winding. The child metadata element is a child of a parent metadata element that corresponds to the respective winding. A node metadata element for each node is located at one of an end of a winding or a junction of multiple windings. The metadata elements and child metadata elements are arranged in a hierarchical format. Each child metadata element is positioned in the data model between a start tag and an end tag of the parent metadata element. The electrical device can be a transformer, for example, and a winding represents a winding of the transformer, one or more segments represent a winding configuration, and a node represents an end of a winding or a junction of multiple windings, as described above.
A data model for defining a circuit layout of
The system of
Many methods can be used to add circuit layout components into the left pane. For example, a user right clicks “Coil” using the mouse 702 and a popup menu appears allowing the user to add a winding or circuit. Segments and nodes, respectively, can be added to the winding and circuit the same way. Alternatively, the user can type in the components using a keyboard 701. As circuit layout components are added in the left pane 610, the blocks are generated and displayed in the right pane 620. In this example, windings 1, 2, and 3 have one segment each. However, five segments were added to winding 4. Segment 3 in winding 4 is a break segment and can be designated as such on the right side by a different color. Sources and destinations can be added to each node 660.
Once the phase circuit is defined, the text file 740 is generated by the processor 720 and stored in the memory 730. The user can launch a command with the user interface, e.g., selects a file menu command, to initiate the generation of the text file 740, or it can be done automatically by the processor 720 for drawing a phase circuit diagram.
Exemplary functionality which can be performed by the processor 720 is embodied in the following pseudocode:
It should be emphasized that the terms “comprises”, “comprising”, “includes”, and “including”, when used in this description and claims, are taken to specify the presence of stated features, steps, or components, but the use of these terms does not preclude the presence or addition of one or more other features, steps, components, or groups thereof.
To facilitate an understanding of exemplary embodiments, many aspects are described in terms of sequences of actions that can be performed by elements of a computer system. For example, it will be recognized that in each of the embodiments, the various actions can be performed by specialized circuits or circuitry (e.g., discrete logic gates interconnected to perform a specialized function), by program instructions being executed by one or more processors, or by a combination of both.
Moreover, the sequences of actions can be embodied in any computer readable medium for use by or in connection with an instruction execution system, apparatus, or device, such as a computer based system, processor containing system, or other system that can fetch the instructions from a computer readable medium and execute the instructions.
As used herein, a “computer readable medium” can be any means that can contain, store, communicate, propagate, or transport the program for use by or in connection with the instruction execution system, apparatus, or device. The computer readable medium can be, for example but not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, device, or propagation medium. More specific examples (a non exhaustive list) of the computer readable medium can include the following: an electrical connection having one or more wires, a portable computer diskette, a random access memory (RAM), a read only memory (ROM), an erasable programmable read only memory (EPROM or Flash memory), an optical fiber, and a portable compact disc read only memory (CDROM).
Thus, the invention can be embodied in many different forms, and all such forms are contemplated to be within the scope of what is claimed. Any such form of embodiment can be referred to herein as “logic configured to” perform a described action, or alternatively as “logic that” performs a described action.
It will be appreciated by those of ordinary skill in the art that the invention can be embodied in various specific forms without departing from its essential characteristics. The disclosed embodiments are considered in all respects to be illustrative and not restrictive. The scope of the invention is indicated by the appended claims, rather than the foregoing description, and all changes that come within the meaning and range of equivalents thereof are intended to be embraced thereby.
This application is a continuation patent application of, and claims priority from, U.S. patent application Ser. No. 10/933,535, filed on Sep. 3, 2004, which is hereby incorporated by reference in its entirety.
Number | Name | Date | Kind |
---|---|---|---|
4986124 | Byrne et al. | Jan 1991 | A |
6211766 | Goseborg et al. | Apr 2001 | B1 |
6239557 | Chang et al. | May 2001 | B1 |
6360357 | Cesare | Mar 2002 | B1 |
6473139 | George | Oct 2002 | B1 |
6516451 | Patin | Feb 2003 | B1 |
6606731 | Baum et al. | Aug 2003 | B1 |
6961918 | Garner et al. | Nov 2005 | B2 |
7168035 | Bell et al. | Jan 2007 | B1 |
7263672 | Cox et al. | Aug 2007 | B2 |
7421648 | Davis | Sep 2008 | B1 |
7475000 | Cook et al. | Jan 2009 | B2 |
20020156929 | Hekmatpour | Oct 2002 | A1 |
20030208365 | Avery et al. | Nov 2003 | A1 |
20040007994 | Ribarich et al. | Jan 2004 | A1 |
20040060014 | Khalil | Mar 2004 | A1 |
20040172603 | Collmeyer et al. | Sep 2004 | A1 |
20040207487 | Hayashi | Oct 2004 | A1 |
20040220791 | Lamkin et al. | Nov 2004 | A1 |
20050080502 | Chernyak et al. | Apr 2005 | A1 |
20050096772 | Cox et al. | May 2005 | A1 |
20050096774 | Bayoumi et al. | May 2005 | A1 |
20050096886 | Smiley et al. | May 2005 | A1 |
20050193361 | Vitanov et al. | Sep 2005 | A1 |
20050278670 | Brooks et al. | Dec 2005 | A1 |
20050289484 | Whitefoot et al. | Dec 2005 | A1 |
20060053398 | Cox et al. | Mar 2006 | A1 |
20060064667 | Freitas | Mar 2006 | A1 |
20060085781 | Rapp et al. | Apr 2006 | A1 |
20060155529 | Ludviksson et al. | Jul 2006 | A1 |
20060178864 | Khanijo et al. | Aug 2006 | A1 |
20070027883 | Cox et al. | Feb 2007 | A1 |
20070234263 | Cox et al. | Oct 2007 | A1 |
20080244491 | Ganesan et al. | Oct 2008 | A1 |
Number | Date | Country |
---|---|---|
0 991 091 | Apr 2000 | EP |
0991092 | Apr 2000 | EP |
PCTUS2007025153 | Jul 2008 | WO |
Number | Date | Country | |
---|---|---|---|
20070283309 A1 | Dec 2007 | US |
Number | Date | Country | |
---|---|---|---|
Parent | 10933535 | Sep 2004 | US |
Child | 11772486 | US |